and I suspect, 68LC040 and 68040V machines. Method used:
1. do NOT use the frames effective address at all
2. do NOT use the frames next instruction address, but
3. restore the "this instruction" pc into the pc field of the frame at the
beginning of the emulation, if we got a frame format 4.
TODO:
A. find the bug in the usage of the frame EA, and revert to using it.
B. find the bug in the usage of the frames next instruction address, and
consider whether it's worthwhile to use it.
C. make the emulation complete.... FEXP FETOM1, and the trigonometric functions
are missing.
the fmovecr constant table has the internal format
of the constants. So, when changing the mantissa size by a
non-multiple of 32 bits, we'd have to change this table, too. As
all other code changes just chopped of the least significand
32bit word of the mantissa, we correct the mantissa size instead
to (115 - 32 == 83) bits.
fpu_fmovecr.c:
put a safety belt in, to catch the next person who doesn't know this.
fpu_int.c:
in one place, the reduction of the mantissa size was overlooked.
fpu_log.c:
as the most significand 32bit word of the mantissa was changed back to the
old format, change back the table indexing code, too.
This should fix PR 11045.
I've fixed most (not all) m68k FPE bugs that give bogus
calculation results, esp. fsqrt instruction. Also, the internal FP
representation has been reduced from 115-bit mantissa to 67-bit
mantissa which reduced the required mantissa operation roughly by one
fourth. I've done an extensive (though not exhaustive - it's
impossible!) test on the internal routines by feeding them randomly
generated FP numbers, and found that the new code is more precise than
MC68040 FPU (it seems to have a rounding bug).
[ Only change was to keep fpu_calcea.c's name instead of renaming to
fpu_ea.c in Ken's patch. --akb ]
destination register bit pattern with 1.0), which automatically provides
corner case handling.
Missing ftwotox emulation originally reported by Norman Mackenzie in PR 4237,
but he proposed a different implementation.
- don't erase FPSR exception bits _after_ doing most of the operations in
fpu_implode(), erase them before doing arith and store operations. This fixes
losing the DZ bit.
- create FPSR_OVFL and FPSR_UNFL bits in fpu_implode(). This showed up when
the first error was fixed.
XXX some more work needs to be done. E.g., creating OPERR together with
OVFL looks bogus, but I'm too tired know to re-check docs; and at least we
pass our own regression tests know.
exceptions, which puts the address of the instruction we faulted
on in a different location. Copy it and handle as we normally would,
restoring the saved PC before returning.
The FPE should probably be reworked to take advantage of the 68LC040's
precalculated effective address, at some point.
<kenn@remus.rutgers.edu>. This emulator does not yet emulate
the following functions:
FSINH, FETOXM1, FTANH, FATAN, FASIN, FATANH, FSIN, FTAN,
FETOX, FTWOTOX, FTENTOX, FCOSH, FACOS, FCOS, FSINCOS
It is sufficient, however, to allow programs like df, w, and newfs,
to run to completion with correct results.
Portions of this code were based on the sparc fpe and on initial
work by gwr.
