This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.
TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.
NOTES:
pmppc was removed as an arch, and moved to a evbppc target.
from doc/BRANCHES:
idle lwp, and some changes depending on it.
1. separate context switching and thread scheduling.
(cf. gmcgarry_ctxsw)
2. implement idle lwp.
3. clean up related MD/MI interfaces.
4. make scheduler(s) modular.
mace devices to their own mace/ directory. Alter conf/files.sgimips to
reflect this change in a sane manner (i.e., pull in dev/files.dev and
mace/files.mace when appropriate).
At the same time, allow crime_intr_establish() to fall through to
mace_intr_establish(). mace devices now call cpu_intr_establish().
The recommended workaround is a 5-10ms delay before and after accesses.
Therefore, move the affected bus_space_* operations from bus.h to bus.c
and special-case MACE accesses.
CRIME accesses are not affected, so introduce SGIMIPS_BUS_SPACE_CRIME and
use it as the CRIME tag.
My ip32 seems a little bit happier with this change, and my ip22 didn't
notice the change.
(with several cosmetic changes by me) which fixes O2 (IP32) support.
Now my R5000 O2 works fine in multiuser with on-board AIC7880 SCSIs
and several PCI network cards (but only on serial console yet).
L2 cache on R5000/Rm5200 is still disabled for now, but it will be
fixed later, hopefully.
See recent discussion on port-sgimips for details.
pass in an interrupt handle (which is currently to the CRIME interrupt the
device is attached to) so the interrupt handlers know which device was the
one looking for attention.
While here, fix up PCI interrupt routing for both the on-board devices and
the PCI slots -- even though there is only one PCI slot in the chasis, the
hardware can accomodate up to three and provides an interrupt mapping for
all the PCI interrupt pins for both the internal SCSI & PCI slot and the
two "extra" slots.
