6c00453054
__HAVE_PREEEMPTION -> __HAVE_PREEMPTION
2015-04-14 22:36:53 +00:00
302cbb59af
Enable DMA transfer.
2015-02-27 16:09:05 +00:00
e91ada0139
fix compile failure without DIAGNOSTIC.
2015-02-19 08:59:56 +00:00
6e15a820ba
Added Interrupt coalescing support.
2015-02-17 01:53:21 +00:00
3012a05a13
Avoid race condition between PTE update and TLB miss walk.
2015-01-26 04:47:53 +00:00
c74a9088fe
Initialize timer DR.
2015-01-23 09:02:42 +00:00
ef2e796f06
ddb MP support
2015-01-23 07:27:05 +00:00
5e43e8eb7b
Avoid if_snd race condition when MP.
2015-01-23 06:58:32 +00:00
d73789f810
- Use tlbivax instruction for TLB update/invalidate when MULTIPROCESSOR is
...
defined. Because TLB entry operation is not notified to another CPU.
- When TLB1 is updated, send IPI_TLB1SYNC to another CPU.
2015-01-23 06:52:55 +00:00
f34bd5be75
When pmap_bootstrap is called, kcpuset_running has not been created yet.
2015-01-23 06:39:41 +00:00
4466bef17e
Allow to share IPI interrupt.
2015-01-23 06:16:23 +00:00
5fc144642a
fix build failure with lockstat.
2015-01-21 06:11:39 +00:00
1b7941c205
Fix various conditions with setting IMASK.
2015-01-16 07:48:16 +00:00
7f75e37ab3
Added missing tx bpf_mtap().
2015-01-16 06:38:27 +00:00
c78b078a2a
Replace if_attach with if_initialize and if_register.
2015-01-16 05:50:15 +00:00
1296cd7938
Use IFQ_* macro instead of IF_*.
2015-01-16 05:36:47 +00:00
a95671af9d
Use correct register for next cacheline address.
2015-01-09 11:45:11 +00:00
836f08a84d
Remove non-printable character.
2015-01-07 01:11:47 +00:00
44e8d61c08
Initialize lock objects.
2015-01-05 07:40:05 +00:00
cb608a466d
include "opt_ppcparam.h" for VERBOSE_INITPPC.
2014-12-28 14:13:56 +00:00
217677d4fc
Preliminary support for P1023.
2014-12-27 16:19:33 +00:00
e9f8801340
fix typo.
2014-12-26 11:13:05 +00:00
f3b7cf62dc
Revert previous accidental commit.
2014-12-20 18:03:17 +00:00
9244f503f6
Revert previous commit.
2014-12-20 17:55:07 +00:00
e1001c1600
Pass ci->ci_cpuid as irq of IST_IPI.
...
Avoid "panic: e500_intr_cpu_hatch: failed to establish ipi interrupt!" on cpu1.
2014-12-19 04:00:35 +00:00
d88bc795d4
Added missing mutex_exit() at error path.
2014-12-19 03:51:38 +00:00
5e72dd2c82
Set correct stack pointer.
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Please handle %r0 with care.
2014-12-19 03:46:23 +00:00
aa7b422e15
Change insn mask to properly match instructions (bctr/blr)
2014-09-22 21:35:15 +00:00
501b7c86f0
Typo
2014-09-18 23:37:51 +00:00
5692aa1c7e
Skip .machine when building with clang.
2014-08-10 18:08:33 +00:00
a86549a1aa
Fix macro spelling.
2014-07-31 12:11:37 +00:00
4423977ff5
Use symbolic constant for SPR. Fix comment.
2014-07-31 01:04:00 +00:00
bf50eedd07
Don't use numeric constants for SPR. Use the symbolic name (SPR_PIR).
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Add DBSR_BRT to KASSERT
2014-07-31 01:01:55 +00:00
76da57e7f2
Replace mfpir with mfspr r, 286. The Power ISA and GAS disagree on the
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semantics of this instruction, so prefer the well defined replacement.
2014-07-30 23:56:01 +00:00
edb8772400
pq3pci_config_addr_read is only used in a #if 0 block, so hide it under
...
the same condition.
2014-07-30 10:50:54 +00:00
1c7643fc59
GC openpic_read.
2014-07-29 23:35:00 +00:00
4a4dc674c9
#if 0 copyout_le32 and friends, they are currently unused.
2014-07-24 23:29:02 +00:00
6bd7e0ed8c
#if 0 unused copyin_halfword.
2014-07-24 23:27:25 +00:00
8011b285c0
Implement MI IPI interface with cross-call support.
2014-05-19 22:47:53 +00:00
d67ab12c1d
pcu(9):
...
- Remove PCU_KERNEL (hi matt!) and significantly simplify the code.
This experimental feature was tried on ARM did not meet the expectations.
It may be revived one day, but it should be done in a much simpler way.
- Add a message structure for xcall function, pass the LWP ower and thus
optimise a race condition: if LWP is discarding its state on a remote CPU,
but another LWP already did it - do not cause an unecessary re-faulting.
- Reduce the variety of flags for PCU operations (only PCU_VALID and
PCU_REENABLE are used now), pass them only to the pcu_state_load().
- Rename pcu_used_p() to pcu_valid_p(); hopefully it is less confusing.
- pcu_save_all_on_cpu: SPL ought to be used here.
- Update and improve the pcu(9) man page; it needs wizd(8) though.
2014-05-16 00:48:41 +00:00
e58a356cba
make pci_intr_string and eisa_intr_string take a buffer and a length
...
instead of relying in local static storage.
2014-03-29 19:28:24 +00:00
e691d98f97
use cpu_{g,s}etmodel
2014-03-24 19:29:59 +00:00
6cb10275d0
Merge riastradh-drm2 to HEAD.
2014-03-18 18:20:35 +00:00
d860f590d4
Fix typo ("then" instead of "than")
2013-12-09 09:35:16 +00:00
b183b3ef97
Get rid of MDLWP_USED{FPU,VEC}
2013-08-23 06:19:46 +00:00
9b2362ab06
kcpuset_t changes for the pmap and removal of __cpuset_t
2013-07-17 23:27:02 +00:00
2b8030185c
Update to new pcu_state_{load,state,release} definitions
2012-12-26 19:05:03 +00:00
f82647e665
Make the 85xx get closer to spinning up the secondary CPUs.
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Don't assume TLB1[0] has the mapping for VA/PA 0.
Make sure the TLB1 entries that map physical memory have the M (memory
coherent) bit set.
2012-11-27 19:24:45 +00:00
2aa18ae8d4
Change a KASSERT to a KASSERTMSG.
2012-10-29 05:25:19 +00:00
57d76ca064
Make bus_dmamap_sync a noop for BookE.
2012-10-29 05:23:44 +00:00
jmcneill