destination register bit pattern with 1.0), which automatically provides
corner case handling.
Missing ftwotox emulation originally reported by Norman Mackenzie in PR 4237,
but he proposed a different implementation.
- Map in all physical memory first in system space. This reduces
pmap_copy_page() and pmap_zero_page to 3 resp. 2 instructions.
- Have fized position user page tables. Makes the pv_table smaller
and all reverse references faster (and simpler).
- Remove the wiring code. Nobody doesn't even know what a DR32 is anymore.
- Simulate page reference bit by setting page invalid, as suggested by
Rich Draves in a paper for 1991 Mach Usenix Symposium.
This reduced the time spent in the pmap module to between 70-75% of
the previous; and made process startup _much_ faster.
- Map in all physical memory first in system space. This reduces
pmap_copy_page() and pmap_zero_page to 3 resp. 2 instructions.
- Have fized position user page tables. Makes the pv_table smaller
and all reverse references faster (and simpler).
- Remove the wiring code. Nobody doesn't even know what a DR32 is anymore.
- Simulate page reference bit by setting page invalid, as suggested by
Rich Draves in a paper for 1991 Mach Usenix Symposium.
This reduced the time spent in the pmap module to between 70-75% of
the previous; and made process startup _much_ faster.
- Map in all physical memory first in system space. This reduces
pmap_copy_page() and pmap_zero_page to 3 resp. 2 instructions.
- Have fized position user page tables. Makes the pv_table smaller
and all reverse references faster (and simpler).
- Remove the wiring code. Nobody doesn't even know what a DR32 is anymore.
- Simulate page reference bit by setting page invalid, as suggested by
Rich Draves in a paper for 1991 Mach Usenix Symposium.
This reduced the time spent in the pmap module to between 70-75% of
the previous; and made process startup _much_ faster.
always located at the end of onboard RAM. This allows locore.s to zero
any offboard RAM to initialise the parity bit which most VMEbus RAM cards
have. Without this, many cards buserr on the first read access.
Thanks to Herb Peyerl for the idea.
From /sys/news3400/news3400/locore.s, with id
@(#)locore.s 8.3 (Berkeley) 9/23/93
Kazumasa Utashiro notes that the pmax cacheflush routines don't work:
#ifndef NOTDEF /* I don't know why Ralph's code doesn't work. KU:XXX */
It's because pmax hardware wries the COP0 bit to external branch
logic. news3400s don't, and so the bc0f loop fails. It will also
fail on some other models of pmax, but we dont' support them.
Surround the relevant framgents in locore_r200.S with "#ifdef pmax".
Longer-term, the cacheflush entry in the locore callback may have
to be a CPU baseboard-specific entry, not just CPU-version specific.
jonathan