The Console driver works now.
Added some fixes for Zorro2 mode, but keep it still disabled.
This commit is contained in:
veego
parent
6255639603
commit
6352bbdb7c
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@ -1,4 +1,4 @@
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/* $NetBSD: grf_cv3d.c,v 1.1 1997/10/19 18:55:21 veego Exp $ */
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/* $NetBSD: grf_cv3d.c,v 1.2 1997/10/29 20:00:47 veego Exp $ */
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/*
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* Copyright (c) 1995 Michael Teske
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@ -38,18 +38,15 @@
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*
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* Modified for CV64/3D from Michael Teske's CV driver by Tobias Abt 10/97.
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* Bugfixes by Bernd Ernest 10/97.
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* Many thanks to Richard Hartmann who gave us his board so we could make
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* driver.
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*
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* TODO:
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* - Console support
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* - ZorroII support
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* - Blitter support
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* - Memcheck for 2MB boards (if they exists)
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*/
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#ifdef CV3DCONSOLE /* XXX */
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#error A console driver for the CyberVision 3D is not yet supported
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#endif
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/* Thanks to Frank Mariak for these infos
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BOARDBASE
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+0x4000000 Memorybase start
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@ -251,7 +248,6 @@ static unsigned char clocks[]={
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static volatile caddr_t cv3d_boardaddr;
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static int cv3d_fbsize;
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static volatile caddr_t cv3d_memory_base;
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static volatile caddr_t cv3d_memory_io_base;
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static volatile caddr_t cv3d_register_base;
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static volatile caddr_t cv3d_vcode_switch_base;
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@ -387,7 +383,7 @@ grfcv3dattach(pdp, dp, auxp)
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(char *) &gp[1] - (char *) &gp->g_display);
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} else {
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if (cv3d_zorroIII == 1) {
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cv3d_memory_base =
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gp->g_fbkva =
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(volatile caddr_t)cv3d_boardaddr + 0x04800000;
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cv3d_memory_io_base =
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(volatile caddr_t)cv3d_boardaddr + 0x05000000;
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@ -398,7 +394,7 @@ grfcv3dattach(pdp, dp, auxp)
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cv3d_special_register_base =
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(volatile caddr_t)cv3d_boardaddr + 0x0C000000;
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} else {
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cv3d_memory_base =
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gp->g_fbkva =
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(volatile caddr_t)cv3d_boardaddr + 0x00000000;
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cv3d_memory_io_base =
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(volatile caddr_t)cv3d_boardaddr + 0x003E0000;
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@ -411,7 +407,6 @@ grfcv3dattach(pdp, dp, auxp)
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}
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gp->g_regkva = (volatile caddr_t)cv3d_register_base;
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gp->g_fbkva = (volatile caddr_t)cv3d_memory_base;
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gp->g_unit = GRF_CV3D_UNIT;
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gp->g_mode = cv3d_mode;
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@ -530,7 +525,7 @@ cv3d_boardinit(gp)
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/* Wakeup Chip */
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vgawio(cv3d_boardaddr, SREG_VIDEO_SUBS_ENABLE, 1);
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/* vgaw(ba, SREG_VIDEO_SUBS_ENABLE, 0x01); */
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vgaw(ba, SREG_VIDEO_SUBS_ENABLE, 0x01);
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vgaw(ba, GREG_MISC_OUTPUT_W, 0x03);
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@ -548,10 +543,8 @@ cv3d_boardinit(gp)
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*/
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vgaw32(cv3d_memory_io_base, MR_ADVANCED_FUNCTION_CONTROL, 0x00000011);
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/* Cpu base addr */
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#if 0 /* XXX */
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WCrt(ba, CRT_ID_EXT_SYS_CNTL_4, 0x00);
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#endif
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/* -hsync and -vsync */
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vgaw(ba, GREG_MISC_OUTPUT_W, 0xC3);
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/* Reset. This does nothing, but everyone does it:) */
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WSeq(ba, SEQ_ID_RESET, 0x03);
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@ -561,7 +554,6 @@ cv3d_boardinit(gp)
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WSeq(ba, SEQ_ID_CHAR_MAP_SELECT, 0x00); /* Character Font */
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WSeq(ba, SEQ_ID_MEMORY_MODE, 0x02); /* Complete mem access */
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WSeq(ba, SEQ_ID_MMIO_SELECT, 0x00);
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test = RSeq(ba, SEQ_ID_BUS_REQ_CNTL); /* Bus Request */
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@ -578,8 +570,6 @@ cv3d_boardinit(gp)
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WSeq(ba, SEQ_ID_SIGNAL_SELECT, 0x02);
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#endif
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vgawio(cv3d_boardaddr, VDAC_MASK, 0xFF); /* DAC Mask */
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test = RSeq(ba, SEQ_ID_CLKSYN_CNTL_2); /* Clksyn2 read */
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/* immediately Clkload bit clear */
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@ -669,11 +659,11 @@ cv3d_boardinit(gp)
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WCrt(ba, CRT_ID_MISC_1, 0x35);
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/* start fifo position */
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WCrt(ba, CRT_ID_DISPLAY_FIFO, 0x5a);
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WCrt(ba, CRT_ID_DISPLAY_FIFO, 0x5A);
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WCrt(ba, CRT_ID_EXT_MEM_CNTL_2, 0x02);
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WCrt(ba, CRT_ID_LAW_CNTL, 0x93);
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WCrt(ba, CRT_ID_LAW_POS_LO, 0x40);
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WCrt(ba, CRT_ID_EXT_MISC_CNTL_1, 0x81);
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WCrt(ba, CRT_ID_MISC_1, 0xB5);
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@ -697,13 +687,9 @@ cv3d_boardinit(gp)
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WAttr(ba, ACT_ID_OVERSCAN_COLOR, 0x01);
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WAttr(ba, ACT_ID_COLOR_PLANE_ENA, 0x0F);
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WAttr(ba, ACT_ID_HOR_PEL_PANNING, 0x00);
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WAttr(ba, ACT_ID_COLOR_SELECT, 0x00); /* now PIXEL_PADDING */
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WAttr(ba, ACT_ID_COLOR_SELECT, 0x00);
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#if 0 /* XXX */
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*((unsigned long *)(ba + ECR_FRGD_COLOR)) = 0xFF;
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*((unsigned long *)(ba + ECR_BKGD_COLOR)) = 0;
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#endif
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vgawio(cv3d_boardaddr, VDAC_MASK, 0xFF); /* DAC Mask */
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/* colors initially set to greyscale */
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@ -721,7 +707,7 @@ cv3d_boardinit(gp)
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WCrt(ba, CRT_ID_LAW_CNTL, 0x13);
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/* find *correct* fbsize of z3 board */
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if (cv3d_has_4mb((volatile caddr_t)cv3d_boardaddr + 0x04800000)) {
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if (cv3d_has_4mb(gp->g_fbkva)) {
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cv3d_fbsize = 1024 * 1024 * 4;
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WCrt(ba, CRT_ID_LAW_CNTL, 0x13); /* 4 MB */
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} else {
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@ -734,8 +720,6 @@ cv3d_boardinit(gp)
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vgaw32(cv3d_memory_io_base, BLT_COMMAND_SET, CMD_NOP);
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vgaw32(cv3d_memory_io_base, BLT_CLIP_LEFT_RIGHT, 0x000007ff);
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vgaw32(cv3d_memory_io_base, BLT_CLIP_TOP_BOTTOM, 0x000007ff);
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vgaw32(cv3d_memory_io_base, BLT_PATTERN_FG_COLOR, 0xFFFFFFFF);
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vgaw32(cv3d_memory_io_base, BLT_PATTERN_BG_COLOR, 0x00000000);
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vgaw32(cv3d_memory_io_base, L2D_COMMAND_SET, CMD_NOP);
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vgaw32(cv3d_memory_io_base, L2D_CLIP_LEFT_RIGHT, 0x000007ff);
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vgaw32(cv3d_memory_io_base, L2D_CLIP_TOP_BOTTOM, 0x000007ff);
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vgaw32(cv3d_memory_io_base, P2D_CLIP_LEFT_RIGHT, 0x000007ff);
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vgaw32(cv3d_memory_io_base, P2D_CLIP_TOP_BOTTOM, 0x000007ff);
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#if 0 /* XXX */
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/* Initialize graphics engine */
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GfxBusyWait(ba);
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vgaw16(ba, ECR_FRGD_MIX, 0x27);
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vgaw16(ba, ECR_BKGD_MIX, 0x07);
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vgaw16(ba, ECR_READ_REG_DATA, 0x1000);
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delay(200000);
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vgaw16(ba, ECR_READ_REG_DATA, 0x2000);
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GfxBusyWait(ba);
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vgaw16(ba, ECR_READ_REG_DATA, 0x3fff);
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GfxBusyWait(ba);
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delay(200000);
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vgaw16(ba, ECR_READ_REG_DATA, 0x4fff);
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GfxBusyWait(ba);
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vgaw16(ba, ECR_BITPLANE_WRITE_MASK, ~0);
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GfxBusyWait (ba);
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vgaw16(ba, ECR_READ_REG_DATA, 0xe000);
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vgaw16(ba, ECR_CURRENT_Y_POS2, 0x00);
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vgaw16(ba, ECR_CURRENT_X_POS2, 0x00);
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vgaw16(ba, ECR_READ_REG_DATA, 0xa000);
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vgaw16(ba, ECR_DEST_Y__AX_STEP, 0x00);
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vgaw16(ba, ECR_DEST_Y2__AX_STEP2, 0x00);
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vgaw16(ba, ECR_DEST_X__DIA_STEP, 0x00);
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vgaw16(ba, ECR_DEST_X2__DIA_STEP2, 0x00);
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vgaw16(ba, ECR_SHORT_STROKE, 0x00);
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vgaw16(ba, ECR_DRAW_CMD, 0x01);
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GfxBusyWait (ba);
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/* It ain't easy to write here, so let's do it again */
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vgaw16(ba, ECR_READ_REG_DATA, 0x4fff);
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vgaw16(ba, ECR_BKGD_COLOR, 0x01);
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vgaw16(ba, ECR_FRGD_COLOR, 0x00);
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#endif
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/* Enable Video Display */
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vgaw(ba, SREG_VIDEO_SUBS_ENABLE, 0x01);
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/* Enable Video Display (Set Bit 5) */
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WAttr(ba, 0x33, 0);
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gi = &gp->g_display;
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gi->gd_regaddr = (caddr_t) kvtop (ba);
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@ -1199,8 +1145,9 @@ cv3d_load_mon(gp, md)
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unsigned short mnr;
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unsigned short HT, HDE, HBS, HBE, HSS, HSE, VDE, VBS, VBE, VSS,
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VSE, VT;
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int cr50, sr15, sr18, clock_mode, test;
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int cr50, cr66, sr15, sr18, clock_mode, test;
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int hmul; /* Multiplier for hor. Values */
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int fb_flag = 2; /* default value for 8bit memory access */
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unsigned char hvsync_pulse;
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char TEXT, CONSOLE;
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@ -1255,17 +1202,31 @@ cv3d_load_mon(gp, md)
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HSS = gv->hsync_start * hmul;
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HSE = gv->hsync_stop * hmul;
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HBE = gv->htotal * hmul - 6;
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HT = gv->htotal*hmul - 5;
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HT = gv->htotal * hmul - 5;
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VBS = gv->vblank_start - 1;
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VSS = gv->vsync_start;
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VSE = gv->vsync_stop;
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VBE = gv->vtotal - 3;
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VT = gv->vtotal - 2;
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/* Disable enhanced Mode for text display */
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vgaw32(cv3d_memory_io_base, MR_ADVANCED_FUNCTION_CONTROL,
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(TEXT ? 0x00000000 : 0x00000011));
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/*
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* Disable enhanced Mode for text display
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*
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* XXX You need to set this bit in CRT_ID_EXT_MISC_CNTL_1
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* _and_ MR_ADVANCED_FUNCTION_CONTROL, because the same
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* function exists in both registers.
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*/
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cr66 = RCrt(ba, CRT_ID_EXT_MISC_CNTL_1);
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if (TEXT) {
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cr66 &= ~0x01;
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vgaw32(cv3d_memory_io_base, MR_ADVANCED_FUNCTION_CONTROL,
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0x00000010);
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} else {
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cr66 |= 0x01;
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vgaw32(cv3d_memory_io_base, MR_ADVANCED_FUNCTION_CONTROL,
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0x00000011);
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}
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WCrt(ba, CRT_ID_EXT_MISC_CNTL_1, cr66);
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if (TEXT)
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HDE = ((gv->disp_width + md->fx - 1) / md->fx) - 1;
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@ -1367,9 +1328,6 @@ cv3d_load_mon(gp, md)
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WCrt(ba, CRT_ID_MODE_CONTROL, 0xE3);
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test = RCrt(ba, CRT_ID_LAW_CNTL);
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WCrt(ba, CRT_ID_LAW_CNTL, (test | 0x10));
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/* text cursor */
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if (TEXT) {
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@ -1404,13 +1362,6 @@ cv3d_load_mon(gp, md)
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((TEXT || (gv->depth == 1)) ? 0x00 : 0x40));
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WGfx(ba, GCT_ID_MISC, (TEXT ? 0x04 : 0x01));
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/*
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* XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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*
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* There is no bit4 in the documentation of the Virge chip.
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* Where is this bit? This could be the reason for the black
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* console screen!!!!!!
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*/
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WSeq (ba, SEQ_ID_MEMORY_MODE,
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((TEXT || (gv->depth == 1)) ? 0x06 : 0x02));
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@ -1433,11 +1384,17 @@ cv3d_load_mon(gp, md)
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switch (gv->depth) {
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case 1:
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case 4: /* text */
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fb_flag = 2;
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HDE = gv->disp_width / 16;
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break;
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case 8:
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fb_flag = 2;
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if (gv->pixel_clock > 80000000) {
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clock_mode = 0x10; /* | 0x02 */
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/*
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* CR67 bit 1 is undocumented but needed to prevent
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* a white line on the left side of the screen.
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*/
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clock_mode = 0x10 | 0x02;
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sr15 |= 0x10;
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sr18 |= 0x80;
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}
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@ -1445,23 +1402,34 @@ cv3d_load_mon(gp, md)
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cr50 |= 0x00;
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break;
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case 15:
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fb_flag = 1;
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clock_mode = 0x30;
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HDE = gv->disp_width / 4;
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cr50 |= 0x10;
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break;
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case 16:
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fb_flag = 1;
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clock_mode = 0x50;
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HDE = gv->disp_width / 4;
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cr50 |= 0x10;
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break;
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case 24: /* this is really 32 Bit on CV64/3D */
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case 32:
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fb_flag = 0;
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clock_mode = 0xd0;
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HDE = (gv->disp_width / 2);
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cr50 |= 0x30;
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break;
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}
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if (cv3d_zorroIII == 1) {
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gp->g_fbkva = (volatile caddr_t)cv3d_boardaddr + 0x04000000 +
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(0x00400000 * fb_flag);
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} else {
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/* XXX This is totaly untested */
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Select_Zorro2_FrameBuffer(fb_flag);
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}
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WCrt(ba, CRT_ID_EXT_MISC_CNTL_2, clock_mode | test);
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WSeq(ba, SEQ_ID_CLKSYN_CNTL_2, sr15);
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WSeq(ba, SEQ_ID_RAMDAC_CNTL, sr18);
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@ -1527,7 +1495,7 @@ cv3d_load_mon(gp, md)
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}
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/* Set display enable flag */
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vgaw(ba, SREG_VIDEO_SUBS_ENABLE, 0x01);
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WAttr(ba, 0x33, 0);
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/* turn gfx on again */
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cv3d_gfx_on_off(0, ba);
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@ -1579,28 +1547,27 @@ cv3d_inittextmode(gp)
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}
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/* print out a little init msg */
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/* c = (unsigned char *)(fb) + (tm->cols - 9) * 4; */
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c = (unsigned char *)(fb) + (tm->cols - 6) * 4;
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c = (unsigned char *)(fb) + (tm->cols - 9) * 4;
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*c++ = 'C';
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*c++ = 0x0a;
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c +=2;
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*c++ = 'V';
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*c++ = 0x0b;
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c +=2;
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*c++ = '6';
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*c++ = 0x0c;
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c +=2;
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*c++ = 'V';
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*c++ = 0x0c;
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c +=2;
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*c++ = '6';
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*c++ = 0x0b;
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c +=2;
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*c++ = '4';
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*c++ = 0x0d;
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/* c +=2;
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*c++ = 0x0f;
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c +=2;
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*c++ = '/';
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*c++ = 0x0e;
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c +=2;
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*c++ = '3';
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*c++ = 0x0f;
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*c++ = 0x0a;
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c +=2;
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*c++ = 'D';
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*c++ = 0x10; */
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*c++ = 0x0a;
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}
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/*
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@ -1,4 +1,4 @@
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/* $NetBSD: grf_cv3dreg.h,v 1.1 1997/10/19 18:55:23 veego Exp $ */
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/* $NetBSD: grf_cv3dreg.h,v 1.2 1997/10/29 20:00:50 veego Exp $ */
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/*
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* Copyright (c) 1995 Michael Teske
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@ -67,10 +67,10 @@ struct grfcv3dtext_mode {
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*((volatile caddr_t)(((caddr_t)ba)+(reg ^ 3))) = ((val) & 0xff)
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/* MMIO access */
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#define BYTEACCIO(x) ( ((x) & 0x3ffc) | (((x) & 3)^3) | (((x) & 3) <<14) )
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#define ByteAccessIO(x) ( ((x) & 0x3ffc) | (((x) & 3)^3) | (((x) & 3) <<14) )
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#define vgario(ba, reg) \
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(*((volatile caddr_t)(((caddr_t)ba) + ( BYTEACCIO(reg) ))))
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(*((volatile caddr_t)(((caddr_t)ba) + ( ByteAccessIO(reg) ))))
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#define vgawio(ba, reg, val) \
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do { \
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@ -80,7 +80,7 @@ struct grfcv3dtext_mode {
|
|||
asm volatile ("nop"); \
|
||||
} \
|
||||
*((volatile caddr_t)(((caddr_t)cv3d_special_register_base) + \
|
||||
( BYTEACCIO(reg) & 0xffff ))) = ((val) & 0xff); \
|
||||
( ByteAccessIO(reg) & 0xffff ))) = ((val) & 0xff); \
|
||||
if (cv3d_zorroIII != 1) { \
|
||||
*((volatile caddr_t)(((caddr_t)cv3d_vcode_switch_base) + \
|
||||
0x04)) = (0x02 & 0xffff); \
|
||||
|
|
@ -102,6 +102,14 @@ struct grfcv3dtext_mode {
|
|||
#define vgaw16(ba, reg, val) \
|
||||
*((unsigned short *) (((volatile caddr_t)ba)+reg)) = val
|
||||
|
||||
/* XXX This is totaly untested */
|
||||
#define Select_Zorro2_FrameBuffer(flag) \
|
||||
do { \
|
||||
*((volatile caddr_t)(((caddr_t)cv3d_vcode_switch_base) + \
|
||||
0x08)) = ((flag * 0x40) & 0xffff); \
|
||||
asm volatile ("nop"); \
|
||||
} while (0)
|
||||
|
||||
int grfcv3d_cnprobe __P((void));
|
||||
void grfcv3d_iteinit __P((struct grf_softc *));
|
||||
static __inline void GfxBusyWait __P((volatile caddr_t));
|
||||
|
|
@ -161,7 +169,7 @@ static __inline unsigned char RGfx __P((volatile caddr_t, short));
|
|||
#define ACT_ID_OVERSCAN_COLOR 0x11
|
||||
#define ACT_ID_COLOR_PLANE_ENA 0x12
|
||||
#define ACT_ID_HOR_PEL_PANNING 0x13
|
||||
#define ACT_ID_COLOR_SELECT 0x14
|
||||
#define ACT_ID_COLOR_SELECT 0x14 /* ACT_ID_PIXEL_PADDING */
|
||||
|
||||
/* Graphics Controller: */
|
||||
#define GCT_ADDRESS 0x03CE
|
||||
|
|
|
|||
Loading…
Reference in New Issue