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235199 Commits

Author SHA1 Message Date
buhrow 3a2e9669fe Add a -b flag so that clients that return their acknowledgements to the 
broadcast address can inter-operate with the tftpd server.
Discussed in bin/49868
 2015-05-05 05:50:31 +00:00
pgoyette 58ba35d88f If module_autoload() returns an error, just return that value instead 
of overwriting with ENODEV.

Thanks, christos!
 2015-05-05 00:28:25 +00:00
jmcneill 8827e7890a Tegra K1 RTC driver. 2015-05-05 00:25:44 +00:00
mrg f3e894d0be libxcb-xkb.so has the wrong version, fix it. patch as provided by 
Yorick Hardy in PR 49873.
 2015-05-04 23:51:25 +00:00
pgoyette ed4e2530a5 If autoload of the subcomponent module fails, don't try to call its 
open routine.  Just return an error.

Hopefully this will fix the recently reported issues with atf tests
running on xen guest.
 2015-05-04 23:50:36 +00:00
jmcneill 1073e5cac0 For Tegra K1, set IE_RX_TIMEOUT (bit 4) in IER register. RX_TIMEOUT occurs 
when data has been sitting in the Rx FIFO for more than 4 character times
without being read because there is not enough data to reach the trigger
level. With this change, enable FIFO usage for Tegra UARTs.
 2015-05-04 22:59:36 +00:00
wiz 25fa64e429 Bump date for previous. 
Use .An.
 2015-05-04 21:29:38 +00:00
ryo 89eada3bfc PR/49819: Roberto E. Vargas Caballero: Add support for SystemBase SB16C1050 PCI serial card 2015-05-04 21:21:38 +00:00
ryo 51f34f06b3 regen 2015-05-04 21:18:34 +00:00
ryo f950c1d946 add SystemBase SB16C1050 UARTs 2015-05-04 21:18:22 +00:00
macallan 36f9ce90f2 fix pasto, use SET() and CLR() 
thanks jmcneill@
 2015-05-04 20:25:48 +00:00
ozaki-r fc9ba4a144 Fix configuration offset when MSI is enabled 
24 is correct.
 2015-05-04 14:08:57 +00:00
ozaki-r 4cc1fb05ea Add NULL check for TAILQ_FIRST 2015-05-04 14:02:13 +00:00
macallan abaafac606 - fix pclk calculation 
- report CPU clock
- pass mclk to child devices
- wire up pins for MSC / sdmmc
 2015-05-04 12:23:15 +00:00
macallan d74120f14c moar registers 
( clock and gpio related )
 2015-05-04 12:16:24 +00:00
martin 39780a1ced Cosmetics: hide an error message from sysctl (machdep.cpu_brand is not 
available on most architectures)
 2015-05-04 10:57:17 +00:00
msaitoh 2d647e75c6 For 82576 and newer devices, the PBA register is deleted. Don't write PBA 
for those chips. Also change the calculation of RX packet buffer size in
new way.
 2015-05-04 10:10:42 +00:00
msaitoh 7e09092336 Modify (E)ITR, TIDV and TADV related code: 
- ITR regiser are not documented in 82575 and newer devices'
   manual. The documets say "E"ITR(0) has no alias (to old ITR).
   But in reality, the alias really exists. When EITR(0) is
   written, the old ITR is changed. Before this commit, ITR was
   written after EITR was written. It causes that EITR's value
   (450) was overwritten with old ITR(1500). Set sc_itr first
   and use the value and don't set ITR if a device >= 82575
   (which has MSI-X multi queue function).
 - Older than 82540 devices have no TADV register.
 - 82575 and newer devices have no TIDV and TADV registers.
 2015-05-04 08:46:09 +00:00
pgoyette 1824fee224 Update the Dt macro to include the x86 subdir. 2015-05-04 08:16:28 +00:00
pgoyette a0820f0ebc Swap function names, so that xxx_bp() refers to the boot processor and 
xxx_ap() to the application processor. It doesn't make any sense to
have bp reference the application processor while ap references boot!

XXX The two function are now lexicographically mis-ordered.  If this
XXX is an issue, let me know and I will re-sequence them.
 2015-05-04 08:15:21 +00:00
wiz 0c6040f523 Sort SEE ALSO. 2015-05-04 08:07:02 +00:00
pgoyette cd4fbf1b4e Fix some more cross-refs to point at the x86-specific subdir 2015-05-04 08:04:50 +00:00
wiz f63d741004 New sentence, new line. 2015-05-04 07:44:18 +00:00
wiz d7601bc4b1 New sentence, new line. Linebreaks. Fix an article. 2015-05-04 07:40:53 +00:00
wiz f4f57f3254 Sort SEE ALSO, fix xref. 2015-05-04 07:39:00 +00:00
wiz 9b918b0962 Add .An -nosplit. 2015-05-04 07:14:03 +00:00
pgoyette 67915f131f One more typo. 
Message to self: when making multi-architecture changes, build on more
than one arch.
 2015-05-04 07:08:10 +00:00
msaitoh 215bd2a43d Set ICH9 and ICH10's PBA size to 14K if the RX buffer size is 
more than 4096. Almost the Same as other OSes
 2015-05-04 06:51:08 +00:00
msaitoh e3ceee8fd3 Remove WMREG_TQSA_LO and WMREG_TQSA_HIGH. Those registers 
are not described in documents and other OS's drivers don't
access it.
(I have no the first chip(82542)'s document. Those registers
might be described in the document).
 2015-05-04 06:44:13 +00:00
pgoyette 1921a9a8e3 Update mark-up 2015-05-04 06:14:47 +00:00
ryoon f45869d2bd Add missing .Sh SYNOPSIS 2015-05-04 05:30:48 +00:00
pgoyette b20ab9736b Remove extraneous blank line. 2015-05-04 03:53:41 +00:00
pgoyette 6722659ea8 Update the min and max interval values for the watchdog. The previous 
numbers were correct, but the units for those numbers was ticks, not
seconds!  (One tco watchdog tick is approximately 0.6 seconds.)
 2015-05-04 03:46:28 +00:00
pgoyette 392712d661 Add new tco(4) man page to sets list. 2015-05-04 02:43:45 +00:00
pgoyette ed66b501e0 Add new man page for tco(4), and update ichlpcib(4) man page. 2015-05-04 02:43:18 +00:00
jmcneill 10be22f9da Remove __HAVE_MM_MD_DIRECT_MAPPED_PHYS and re-enable 2GB support, fixed 
by arm32_kvminit.c r1.33
 2015-05-04 00:59:29 +00:00
matt 9ff8857237 Deal with 4GB overflow in arm32_kvminit.c 2015-05-04 00:55:30 +00:00
matt 78ddb4758e Deal with 2GB of ram or memory ending at or above 4GB. 2015-05-04 00:44:12 +00:00
matt 4287fca664 Fix 4GB wraparound math. 2015-05-04 00:41:42 +00:00
matt 5617d6aa97 If not using LPAE, if memory ends at 4GB ignore the last page so physical_end 
doesn't wrap to 0.
 2015-05-04 00:12:56 +00:00
pgoyette a53699f70e Teach a couple of i2cbus controllers how to rescan. This enables 
{,un}loading and {at,de}taching of the iic(4) driver/module at a
later time. Tested piixpm on QEMU, and ichsmb on my live server.
 2015-05-03 22:51:11 +00:00
jmcneill 6e27dfa8cf since we dont support SDR104 yet, dont try to optimize it; instead, optimize for HS mode, which brings us up from 34 MHz to 45.333 MHz 2015-05-03 22:40:02 +00:00
jmcneill c82d0cfd23 print some useful information at attach time 2015-05-03 22:37:27 +00:00
pgoyette 572ab4e2b8 Put the '/' back, but put it in the correct location! 2015-05-03 21:59:23 +00:00
jmcneill 5e96a9e7b1 disable MULTIPROCESSOR for now 2015-05-03 18:49:28 +00:00
jmcneill ec484ab4fe UART clock source is PLLP. Set com type to COM_TYPE_TEGRA. 2015-05-03 17:24:45 +00:00
jmcneill ecb2b6ae4b add COM_TYPE_TEGRA 2015-05-03 17:22:54 +00:00
jmcneill bcce07f3b2 add pllc and uart rate funcs 2015-05-03 16:40:12 +00:00
matt 40d5a9d580 On secondary cores, invalidate the caches to make them clean. 2015-05-03 16:18:51 +00:00
martin 2d0cfa998a PR 49870: pass the xsrc path to postinstall 2015-05-03 15:13:13 +00:00