Commit Graph

256797 Commits

Author SHA1 Message Date
skrll 366599d113 Switch hppa to gcc 6.4 2018-02-23 21:16:01 +00:00
maxv fb601e36f3 Fix off-by-one, we don't want the entry point to equal the maximum
address.
2018-02-23 19:43:08 +00:00
maxv 128a58ec1f Add a new entry in the TODO list. 2018-02-23 19:39:27 +00:00
wiz d4104cf420 Remove unnecessary macros. 2018-02-23 16:32:44 +00:00
maxv 9cfc8ac233 Revert previous, we'll need something better (and compatible with Clang). 2018-02-23 14:16:52 +00:00
maxv 679b615db6 Change the SVS node, from machdep.svs_enabled to machdep.svs.enabled. 2018-02-23 09:57:20 +00:00
maxv fa15de1fb8 Add -fno-shrink-wrap, to force GCC to push the frames at the very beginning
of the functions. Otherwise DDB is unable to display a correct stack trace
if a fault occurred in a function before the frame was pushed.

Discussed on tech-kern@, flag suggested by Krister Walfridsson. Should fix
PR/52560.
2018-02-23 09:00:55 +00:00
sevan 54d67daa03 BUFQ_PRIOCSCAN enabled on macppc port. 2018-02-23 03:33:36 +00:00
sevan b3bc30e9ee Enable BUFQ_PRIOCSCAN by default for NetBSD/macppc.
Drop references to NEW_BUFQ_STRATEGY and replace with currently available
options BUFQ_READPRIO and BUFQ_PRIOCSCAN.

ok <macallan>
2018-02-23 03:04:01 +00:00
sevan e30a52f94e Remove OFB_ENABLE_CACHE
from <macallan>
"it is outdated, genfb and friends don't need or use it, and it makes no sense
on accelerated drivers either. It tries to BAT-map the framebuffer cacheable,
which works on most macs but makes a few models lock up. Genfb doesn't have that
problem and is faster too."
2018-02-23 02:54:56 +00:00
mrg a23ad621f4 remove this obsolete file that has a lot of dated info from
about the time we started switching some ports to GCC 5.3.
2018-02-23 01:01:22 +00:00
mrg 7d1f9b1bbb regen ppc64 mknative gcc 6 files with biarch support. 2018-02-22 22:25:16 +00:00
mrg 7b8aed4e4d fix powerpc64 bi-arch support: provide a LINK_SECURE_PLT_SPEC.
with this, and mknative-gcc for it, powerpc64 builds with GCC 6.
2018-02-22 22:20:44 +00:00
maxv ce547de3df Adapt previous; put #ifdef SVS around the declaration directly. 2018-02-22 14:57:11 +00:00
sevan 664dbfa44d Improve description of ddb.commandonenter. 2018-02-22 14:49:29 +00:00
sevan 1c253e4545 Document ddb.dumpstack sysctl
Remove the mention of ddb.onpanic=2 as that functionality was removed with the
introduction of ddb.dumpstack.

Heads up by <pgoyette>
2018-02-22 14:37:53 +00:00
sevan 80722e99c3 Sort ddb section in alphabetical order.
Bump date.
2018-02-22 14:32:50 +00:00
martin 3cbaed46a2 PR lib/53044: remove tests not provided by OpenSSL 1.1.x 2018-02-22 14:24:03 +00:00
martin 20bd55c3fb Protect the SVS part of SYSCALL_ENTRY by #ifdef SVS to make non-SVS
kernels compile again.
2018-02-22 14:08:48 +00:00
maxv e95c8223d9 Remove svs_pgg_update(). Instead of manually changing PG_G on each page,
we can disable the global-paging mechanism in %cr4 with CR4_PGE. Do that.

In addition, install CR4_PGE when SVS is disabled manually (via the
sysctl).

Now, doing "sysctl -w machdep.svs_enabled=0" restores the performance
completely, exactly as if SVS hadn't been enabled in the first place.
2018-02-22 13:27:17 +00:00
maxv 53447ceddb Ensure the CPUs are all online. We take cpu_lock, so nobody can go offline
in the meantime.
2018-02-22 11:57:39 +00:00
maxv 5ab8a4e764 Make the machdep.svs_enabled sysctl writable, and add the kernel code
needed to disable SVS at runtime.

We set 'svs_enabled' to false, and hotpatch the kernel entry/exit points
to eliminate the context switch code.

We need to make sure there is no remote CPU that is executing the code we
are hotpatching. So we use two barriers:

 * After the first one each CPU is guaranteed to be executing in
   svs_disable_cpu with interrupts disabled (this way it can't leave this
   place).

 * After the second one it is guaranteed that SVS is disabled, so we flush
   the cache, enable interrupts and continue execution normally.

Between the two barriers, cpu0 will disable SVS (svs_enabled=false and
hotpatch), and each CPU will restore the generic syscall entry point.

Three notes:

 * We should call svs_pgg_update(true) afterwards, to put back PG_G on
   the kernel pages (for better performance). This will be done in another
   commit.

 * The fact that we disable interrupts does not prevent us from receiving
   an NMI, and it would be problematic. So we need to add some code to
   verify that PMCs are disabled before hotpatching. This will be done
   in another commit.

 * In svs_disable() we expect each CPU to be online. We need to add a
   check to make sure they indeed are.

The sysctl allows only a 1->0 transition. There is no point in doing 0->1
transitions anyway, and it would be complicated to implement because we
need to re-synchronize the CPU user page tables with the current ones (we
lost track of them in the last 1->0 transition).
2018-02-22 10:42:10 +00:00
maxv f929364d1e Mmh, add #ifdef SVS around svs_init(). 2018-02-22 10:26:32 +00:00
msaitoh 9e5f5b7ce0 Add Microchip EMC1501. 2018-02-22 10:12:54 +00:00
msaitoh 9e24688bc3 - Add Maxim MAX6604.
- Microchip EMC1501.
- ADT7408's device ID is not 0x80 but 0x08.
2018-02-22 10:09:12 +00:00
msaitoh ae5ab404d8 Fix a potential bug that TX/RX might stall when TX rate limit reached.
This change is almost the same as the RX rate limit bug fix in ixgbe.c
rev. 1.121. I've never got any stall, but this must be a bug.
2018-02-22 10:02:08 +00:00
maxv f2cbc9d834 Improve the SVS initialization.
Declare x86_patch_window_open() and x86_patch_window_close(), and globalify
x86_hotpatch().

Introduce svs_enable() in x86/svs.c, that does the SVS hotpatching.

Change svs_init() to take a bool. This function gets called twice; early
when the system just booted (and nothing is initialized), lately when at
least pmap_kernel has been initialized.
2018-02-22 09:41:06 +00:00
maxv ebc1f703f9 Add a dynamic detection for SVS.
The SVS_* macros are now compiled as skip-noopt. When the system boots, if
the cpu is from Intel, they are hotpatched to their real content.
Typically:

		jmp	1f
		int3
		int3
		int3
		... int3 ...
	1:

gets hotpatched to:

		movq	SVS_UTLS+UTLS_KPDIRPA,%rax
		movq	%rax,%cr3
		movq	CPUVAR(KRSP0),%rsp

These two chunks of code being of the exact same size. We put int3 (0xCC)
to make sure we never execute there.

In the non-SVS (ie non-Intel) case, all it costs is one jump. Given that
the SVS_* macros are small, this jump will likely leave us in the same
icache line, so it's pretty fast.

The syscall entry point is special, because there we use a scratch uint64_t
not in curcpu but in the UTLS page, and it's difficult to hotpatch this
properly. So instead of hotpatching we declare the entry point as an ASM
macro, and define two functions: syscall and syscall_svs, the latter being
the one used in the SVS case.

While here 'syscall' is optimized not to contain an SVS_ENTER - this way
we don't even need to do a jump on the non-SVS case.

When adding pages in the user page tables, make sure we don't have PG_G,
now that it's dynamic.

A read-only sysctl is added, machdep.svs_enabled, that tells whether the
kernel uses SVS or not.

More changes to come, svs_init() is not very clean.
2018-02-22 08:56:51 +00:00
msaitoh c12c1020e1 - Apply ixgbe.c rev. 1.124 to ixv.c. Fix a bug that RX may stall on heavy load
on ixv(4) derived from FreeBSD's AIM (Auto Interrupt Moderation) bug.
 ITR_INTERVAL value must be larger than 4us.

- The bitfield of EITR register is different between 82598 and others.
 ixv.c had a bug that it accessed 82598's way even though only 82599 and
 newer support virtual function. Fix it using with new ixv_eitr_write()
 function.
2018-02-22 08:49:42 +00:00
maxv 411ee66e5e Revert all my latest changes, and restore this file back to how it was
in rev1.24. I wanted to replace the functions dynamically for SVS, but
that was a dumb idea, we'll just hotpatch instead.
2018-02-22 08:36:31 +00:00
pgoyette d831ae84a0 Remove extra "an"
Thanks to J. Lewis Muir
2018-02-22 08:33:43 +00:00
msaitoh c0048f42c5 Regen. 2018-02-22 07:53:13 +00:00
msaitoh f65a80924c Add some Xeon E5 (v1) and E5 v2 devices. 2018-02-22 07:52:46 +00:00
mrg 374a4ca79b move "define tcbus {}" into files.alpha. it isn't wanted for general
ports, and generates an unused symbol for pmax.  with this both alpha
and pmax kernel work with gcc 5 and 6.
2018-02-22 07:30:43 +00:00
mrg da58b5e34c re-port the patch from https://gcc.gnu.org/bugzilla/attachment.cgi?id=15492.
- local HOST_WIDE_INT_CONSTANT macro same as new HOST_WIDE_INT_C macro,
  so use it instead, and remove the local macro.
- re-port the genrecog.c change which was missed in early GCC-6 port.

this makes sh3 work again.
2018-02-22 07:24:19 +00:00
mrg 67c67975c6 bump image size for gcc 6 bloaty mc bloat face. 2018-02-22 07:21:10 +00:00
msaitoh 9d47bd6cf6 Regen. 2018-02-22 05:23:55 +00:00
msaitoh a2ba4bf8b8 s/C62x9/C62x/ 2018-02-22 05:23:29 +00:00
msaitoh 3639a6a58d Add C620 devices. 2018-02-22 05:09:56 +00:00
msaitoh 9993be85ad Regen. 2018-02-22 03:13:38 +00:00
msaitoh c6b09d4225 Fix C62x9 sSATA Controller (RAID) device ID. 2018-02-22 03:13:18 +00:00
msaitoh 7ec4fc9862 Regen. 2018-02-22 03:03:52 +00:00
msaitoh 4cd4349560 Add C620 devices. 2018-02-22 03:03:28 +00:00
sjg b4dd1ca28c Avoid calling sysconf for every file loaded.
At start of a meta build this can be measurable overhead.

Patch from bdrewery at freebsd.org
2018-02-22 01:59:28 +00:00
christos 9ec2100f76 notyet an unused variable. 2018-02-22 01:50:26 +00:00
pgoyette 0ef61efcca Add config option for tpm at acpi 2018-02-22 01:40:49 +00:00
christos 63b13d00d5 gcc-6 needs -nosse 2018-02-22 01:37:04 +00:00
jdolecek f82a61429e KERNEL_PID is > 0 on powerpc/ibm4xx, need to mask all bits <0,
KERNEL_PID> to avoid triggering KASSERT() checking allocated asid
is bigger than KERNEL_PID; adjust also TLBINFO_ASID_INITIAL_FREE()
accordingly

discussed with Nick
2018-02-21 21:53:54 +00:00
maxv 790020449d Style, no functional change. 2018-02-21 17:04:52 +00:00
maxv 2256f36f66 Strengthen this check, to make sure there is room for an ip6_ext structure.
Seems possible to crash m_copydata here (but I didn't test more than that).
2018-02-21 16:55:53 +00:00