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2921 Commits

Author SHA1 Message Date
maya
48097a1e57 switch post-mfc0 call "hazard barrier" from NOP_L to MFC0_HAZARD. 
this means it will be applied if MIPS3 too, and now with the prior
commit, it will be a superscalar nop, not just a plain nop.
 2016-11-11 16:49:30 +00:00
maya
8eed97ac9a remove redundant NOP_L. we do not use the register immediately after 
load, so it's not needed.
 2016-11-11 16:45:14 +00:00
maya
5997445727 switch mfc0_hazard to be superscalar nop, some mips3 are superscalar 
and need this to do the right thing
 2016-11-11 16:41:32 +00:00
maya
9c53bef583 Move MFC0_HAZARD definition to asm.h instead of defining it twice 2016-11-09 11:50:09 +00:00
skrll
958325a389 Cmoment formatting. No functional change. 2016-11-04 08:24:36 +00:00
skrll
94b84ddb19 Pre-allocate some kcpuset_ts so that we don't try and allocate in the 
wrong context.
 2016-10-31 12:49:04 +00:00
skrll
7a18db2183 Fixup IPI interrupt delivery and splsched mask so that 
sys/uvm/pmap/pmap_tlb.c

    541 	KASSERTMSG(ci->ci_cpl >= IPL_SCHED,
    542 	    "%s: cpl (%d) < IPL_SCHED (%d)",
    543 	    __func__, ci->ci_cpl, IPL_SCHED);

doesn't fire.
 2016-10-31 12:27:22 +00:00
jdolecek
e1d3e1b041 add isa_intr_establish_xname() to MD isa headers so that it can be used 
by MI drivers
 2016-10-18 22:04:33 +00:00
maxv
f89daf891a Remove unused (and buggy) function. Not even compile-tested, but I've 
been told to go ahead anyway.
 2016-10-16 10:57:58 +00:00
macallan
7c498bf2e4 include locore.h for MIPS3_PLUS, while there annotate some #else and #endif 2016-10-13 18:58:00 +00:00
macallan
e16937d805 include locore.h so MIPS3_PLUS is visible and we build support for MIPS-III 
and newer FPUs as needed
no more SIGILLs on trunc.d.* with n32 userlands
 2016-10-13 18:54:46 +00:00
macallan
e47f75e641 sprinkle #ifndef __ASSEMBLER__ to make this file usable from .S - mostly for 
macros like MIPS3_PLUS
 2016-10-13 18:52:30 +00:00
skrll
1b2f83c8ef Trailing whitespace 2016-10-10 07:37:56 +00:00
skrll
79743a4d43 vaddr_t -> register_t in range cache ops 2016-10-10 07:37:17 +00:00
skrll
201a76373f Sign extend VA for cache operations. 
OK matt@
 2016-10-08 08:19:22 +00:00
macallan
e73779d781 - don't clear KX when disabling interrupts 
- sign extend addresses as needed
- use PAGE_SIZE instead of blindly assuming 4KB
now n32 kernels work again on my R5k SGIs
thanks to skrll@ for helping me with this
 2016-10-08 00:39:53 +00:00
ryo
4613293a54 add support MT7628/MediaTek LinkIt Smart 7688 
by @hiroshi and me.
 2016-10-05 15:54:58 +00:00
ryo
d721e9d6a1 KNF; indent, spaces and tabs. 
No functional change.
 2016-10-05 15:39:31 +00:00
maya
4b2f24ad42 Simplify. LOONGSON2 and MIPSNNR2 not possible. 2016-10-02 09:06:35 +00:00
jdolecek
f52dcd49ca remove last isolated islands using BUS_SPACE_BARRIER_SYNC and 
BUS_SPACE_BARRIER_X_BEFORE_X - these were only ever defined for mips and ia64,
and never actually implemented even there
 2016-09-15 21:45:37 +00:00
skrll
ad83f0c77c Remove stray assignment. 2016-09-10 13:42:11 +00:00
skrll
c6d5e9154c Fixup siginfo 2016-09-10 13:40:14 +00:00
skrll
328eb1ab0d Flush the dcache before syncing the icache as previous mappings (UBC) 
might have used the same colo(u)r and the dcache won't have been flush up
to now.
 2016-09-05 06:59:25 +00:00
skrll
87240e32e1 Another typo... that's what you get for not compile testing 2016-09-04 15:25:11 +00:00
skrll
7246cf077c Typo in previous 2016-09-04 15:23:14 +00:00
skrll
6a9bc54ee6 Safely remove non-PV_KENTER pages from pv_list 2016-09-04 15:21:54 +00:00
skrll
e149b2e619 Sign extend va for use with cache ops 2016-09-04 07:47:12 +00:00
skrll
9cd6c57a69 More debug 2016-09-04 07:38:45 +00:00
skrll
3b8780d834 Remove old and incorrect comments 2016-09-04 07:30:52 +00:00
skrll
16b46675c7 Fix pte_cached_p for MIPS_HAS_R4K_MMU 2016-09-04 07:27:49 +00:00
skrll
b37324e131 Comment consistency. No functional change. 2016-08-27 07:22:14 +00:00
skrll
81daccdc2c Trailing whitespace 2016-08-27 05:52:43 +00:00
skrll
4e8b65a17b Adjust evbmips_iointr to pass a clockframe pointer and use it for 
pwmclock @ voyager.

Suggested by matt@

Hi macallan!
 2016-08-26 15:45:47 +00:00
skrll
d2b6f0303e Whitespcae 2016-08-23 07:29:46 +00:00
skrll
0363604388 KNF 2016-08-22 11:34:42 +00:00
skrll
4ca51ca61a Can't KASSERT that a lock isn't held. 2016-08-22 11:34:06 +00:00
skrll
d12c93e8ec Fix a couple of (unsed) definitions 2016-08-20 06:34:22 +00:00
skrll
441d694c73 Need to set ci_request_ipis otherwise they won't get delivered. 
Correct the test for the IPL_HIGH ipis
 2016-08-20 06:31:15 +00:00
skrll
ce214d27a3 Fix insn #2 printf in octeon_fixup_cpu_info_references 2016-08-19 10:20:42 +00:00
skrll
1bd2f79dee Remove useless cast 2016-08-19 10:19:15 +00:00
skrll
a751e06a6e Trailing whitespace 2016-08-19 10:05:35 +00:00
martin
3757fcb029 Typo in #ifdef - the per cpu wdog softint wasn't initialized. 2016-08-19 07:51:29 +00:00
skrll
d256e8d7af Need to compile in cache alias support when MIPS3 or MIPS4 2016-08-18 22:23:20 +00:00
skrll
77999b67e7 Trailing whitespace 2016-08-18 19:25:34 +00:00
skrll
c341bcf48a Make the fixup code play nicely with the current exception handlers. 
From matt@
 2016-08-18 19:24:31 +00:00
skrll
06e42c9074 Initialise ci_pmap_kern_segtab in cpu_info_alloc 2016-08-18 14:39:04 +00:00
skrll
e02779accf Spelling in comment 2016-08-17 22:02:19 +00:00
skrll
c6c4b8f206 loongson whack-a-mole. 
- clear the top bits so the legal address check is correct.
- need to sign-extend the seg offset for kernel fault check
 2016-08-17 20:59:08 +00:00
skrll
60a6c9ad06 Code consistency. No functional change. 2016-08-16 09:55:14 +00:00
skrll
dd0d36ecfb Fix copy&pasto shift value - hopefully this will fix LOONGSON/GDIUM 2016-08-15 14:45:31 +00:00