d38e1fa853
Use "rxintr" for the name of the receive interrupts evcnt instead
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of "txintr". Much less confusing that way...
2003-03-27 01:21:52 +00:00
0a30e5fb17
Fix a grammatical nit.
2003-03-22 14:26:41 +00:00
3c7ff59b5b
Sprinkle some "volatile"; fixes problems with the {read,write}_{1,2}
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functions big-endian Au1xxx CPUs.
2003-03-13 03:04:13 +00:00
0f55132c91
Initialize the two new members of "struct console" to NULL so that
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this file compiles again.
2003-03-08 09:42:56 +00:00
67cca2386c
Protect uses of MIPS_R5000 with #ifndef ENABLE_MIPS_R3NKK in new code just
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as the old code does.
2003-03-08 05:18:25 +00:00
33fcc94c6f
Add support for R5k secondary caches, from code Chris Sekiya sent me a long
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time ago, with small tweaks by me. Since the R5k doesn't do VCE, the pmap
still needs to be whacked for R5kSC CPUs to work correctly, but this is a
start.
2003-03-08 04:43:24 +00:00
31e2cbf0b5
add some ISO C 1995 I18N functions and types:
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btowc, wctrans, towctrans, wcscoll, wcsxfrm, wctype_t and wctrans_t.
2003-03-02 22:18:11 +00:00
7a3efea0bf
Make whitespace in multi-way loops line up a bit nicer.
2003-02-17 12:32:13 +00:00
8883b06039
No need to protect headers with #ifdef _KERNEL if they're never installed
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in /usr/include.
2003-02-17 11:35:01 +00:00
bc735179e8
use COP0_HAZARD_FPUENABLE in a couple more places when turning on FP:
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In start (noticed after looking for more COP_1_BIT uses, and note
that there are extra nops here but really they don't hurt), and in
MachFPTrap (noticed by ... running regress!).
2003-02-08 00:50:33 +00:00
8a6b8c3b72
Update to consistently use Broadcom GPL-compatible license on all SiByte code.
2003-02-07 17:38:48 +00:00
045575c57d
add BCM112x A2 definition
2003-02-07 17:35:05 +00:00
e3e4805068
Replace machine/rnd.h with more appropriate name to share it
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with cycle counter based microtime in kern/kern_microtime.c.
2003-02-05 13:57:50 +00:00
cd7d9faeaf
Introduce BUS_DMA_NOCACHE, and bus_dmamem_map() of i386 supports it.
2003-01-28 01:07:51 +00:00
d77e3b36e0
Assign to pcb->pcb_context[] in the same order in cpu_lwp_fork() and
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cpu_setfunc().
2003-01-22 13:55:09 +00:00
c406903ac2
LWP'ify the svr4_mcontext stuff.
2003-01-22 04:32:17 +00:00
76cc21a34c
Fix a tyop and some white-space nits.
2003-01-21 04:26:01 +00:00
706b88727b
Fix typo in sigcontext conversion macros. From Christopher SEKIYA.
2003-01-20 16:28:13 +00:00
aa4186745b
Add '#define' for _MCONTEXT_TO_SIGCONTEXT().
2003-01-18 13:03:17 +00:00
a50e3bc1cb
Merge the nathanw_sa branch.
2003-01-17 22:58:53 +00:00
b2e8253950
Zero out the TX buffer when padding packet to ETHER_MIN_LEN-ETHER_CRC_LEN.
2003-01-17 12:40:20 +00:00
c018fbe68d
Tidy up event counter increments a little.
2003-01-16 01:14:17 +00:00
c69f520bc8
Removed unused register map; this info is now passed in with the attach
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args.
2003-01-16 01:05:39 +00:00
0cc0813590
Add the MIPS3_CONFIG_SE (name taken from Rm52xx manual) bit, which is the
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external cache enable bit -- this allows software to enable or disable the
(external) L2 cache on the R5k and Rm527x and the (external) L3 cache on
the Rm7k. If the (external) cache is disabled, treat it as if there were
no cache for the purposes of the cache setup code.
Also, update sgimips code to use the new name.
2003-01-10 03:22:48 +00:00
1035faff1d
writable, not writeable.
2003-01-06 20:30:28 +00:00
dbb0f0ebed
Use aprint_normal() for cfprint routines.
2003-01-01 01:47:30 +00:00
4a06119a9d
Pass the system call table to trace_enter() and ktrsys() so that it is
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possible to use alternate system call tables. This is usefull for
displaying correctly the arguments in Mach binaries traces.
If NULL is given, then the regular systam call table for the process is used.
2002-12-21 16:23:56 +00:00
5b6caeca74
Mark the Au1x00 CPUs as having a fully coherent data cache that doesn't
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require flushing (even in the instruction cache handlers). This gives
about a 4% improvement in a "make depend" benchmark.
Mark the SB-1 CPUs as having a fully coherent data cache that only
require flushing in the instruction cache handlers. This gives about
a 5% improvement in a "make depend" benchmark.
2002-12-17 12:07:50 +00:00
2c1a832f25
Add support for caches where the data cache is fully coherent, and
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either requires flushing either only when the I cache ops are used
or not at all. Currently only used by MIPS32/MIPS64 cache code.
2002-12-17 12:04:29 +00:00
e8cc3884de
Rename __LDPGSZ to AOUT_LDPGSZ, to accurately reflect what it is.
2002-12-10 17:14:02 +00:00
78ea2dd367
Use __LDPGSZ (which must be == USRTEXT) as the text address for a.out
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executables, and eliminate the USRTEXT constant, which was only used
by the a.out exec code.
2002-12-10 05:14:24 +00:00
6a5e492b57
Remove the explicit `makeoptions MACHINE_ARCH="mipse{b,l}"' for kernel
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builds and use the endianness of the toolchain being used to determine
the endianness of the kernel.
2002-12-09 22:54:09 +00:00
699bf96665
Drop the _KERNEL test; these functions are needed for SMP and other ports
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don't bother with a _KERNEL check.
2002-12-05 02:56:51 +00:00
d03ac2a783
Fix botch in previous. This is pcb.h, not reg.h.
2002-11-30 22:50:01 +00:00
9a87c0933c
make LKM friedlier - only include opt_* ifdef _KERNEL_OPT
2002-11-30 10:52:16 +00:00
fdd1e3b715
Standardise on #ifdef _MIPS_<header>_H_ for multiple inclusion tests.
2002-11-30 01:52:31 +00:00
d644dd9c43
Add multiple-inclusion protection.
2002-11-30 01:49:18 +00:00
0635de35a3
Remove KDIR=, since SYS_INCLUDE=symlinks and KDIR are not supported any more.
2002-11-26 23:30:07 +00:00
12c35ee2d2
New generic way-aware MIPS32/64 range-index cache functions with proper
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handling for phyiscally-indexed caches where the way size is greater than
the page size.
These work fine with pass 1 SB1 cores, so g/c those workarounds.
Much thanks to Chris Demetriou for many suggestions and helping me get
my head around all this.
2002-11-24 07:41:29 +00:00
3a72aadc2b
Add the VI bit in config 0.
2002-11-24 07:28:42 +00:00
3682edd3d4
Move the curpcb and segbase extern decls to cpu.h to better group together
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what will need to change for SMP.
Hide 'struct cpu_info' and some macros in #ifdef _KERNEL/#endif.
2002-11-24 07:26:04 +00:00
8935916d0a
initial support for mac features in new chip revs
2002-11-19 01:44:04 +00:00
5e3d4a224c
Add cache_r4k_op_8lines_{16,32} macros to perform cache ops on 8
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consecutive lines.
2002-11-17 06:40:43 +00:00
aa5595f691
Fix typo in the address of the Au1500 MAC1 enable register; 2nd MAC works
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on the Au1500 cpu now.
2002-11-17 04:57:34 +00:00
ba1c8ffa9d
Remove reference to mips_int5_evcnt from here; that is port-specific,
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not arch-specific.
2002-11-17 04:56:57 +00:00
d584ed9598
Add a realcode argument to trace_enter and ktrsyscall. realcode is the
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original system call number, which can be negative for a Mach trap.
We cannot just replace code by realcode, because ktrsyscall uses it as
an index in the system call table, thus crashing the kernel when the
value is negative.
2002-11-15 20:06:00 +00:00
5bdb1a36ce
Add a hack to mipsNN_pdcache_wbinv_range_index_32_4way() so that we
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use the index ops at a offset of the page size as well, controlled by
an MIPS64_SB1 check. The SB1 D-cache way size is physically indexed
and twice as big as the page size (4k), so we weren't flushing all the
addresses we needed too.
XXX: This is kinda gross; will be cleaned up and made more generic soon.
There are still other SB1-specific issues to be cleaned up too...
2002-11-15 01:23:17 +00:00
181d7f08c9
Use COP0_HAZARD_FPUENABLE instead of a hard-coded 4 NOPs when enabling
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the FPU.
2002-11-15 01:16:18 +00:00
2aabe4d4e2
Define COP0_HAZARD_FPUENABLE as four nops.
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Include <mips/sb1regs.h> if MIPS64_SB1 is defined.
2002-11-15 01:15:11 +00:00
383afcb5b6
Declare some CP0 hazards for the SB1 core.
2002-11-15 01:09:20 +00:00
simonb