we no longer need to guard against access from hardware interrupt handlers.
Additionally, if cloning a process with CLONE_SIGHAND, arrange to have the
child process share the parent's lock so that signal state may be kept in
sync. Partially addresses PR kern/37437.
proclist_mutex and proclist_lock into a single adaptive mutex (proc_lock).
Implications:
- Inspecting process state requires thread context, so signals can no longer
be sent from a hardware interrupt handler. Signal activity must be
deferred to a soft interrupt or kthread.
- As the proc state locking is simplified, it's now safe to take exit()
and wait() out from under kernel_lock.
- The system spends less time at IPL_SCHED, and there is less lock activity.
figuring out all the crazy nuances of getting this working, and to
Michael Lorenz for testing/fixing my changes on macppc. Tested with a
quad-proc 7044-270.
Summary of changes:
Bumped CPU_MAXNUM to 16 on ofppc.
Added md_* routines to ofppc/cpu.c, to sync the timebase, and awaken the CPUs.
Fixed a bug in the test for a 64bit bridge cpu early in locore.S
Added code to set the interrupt priority for all CPUs with an openpic.
Change rtas to probe before cpus, to allow use of the rtas freeze/thaw
timebase code routines.
Fix CPU_INFO_FOREACH macro to iterate through detected cpus, not CPU_MAXNUM.
Change most uses of ci_cpuid to ci_index, to deal with CPUs that do not allow
writing to SPR_PIR. Don't write SPR_PIR unless the secondary cpu identifies
itself as 0.
Change the hatchstack/interrupt stack allocations to allocate a 8192byte
interrupt stack, and a 4096 byte hatch stack, align them to 16 bytes, and
allocate them no lower than 0x10000. Allocate them separately to prevent the
hatch stack corrupting the interrupt stack later on.
If the CPU is a 64bit cpu, copy SPR_ASR in cpu_hatch()
Set the idle stack to ci->ci_data.cpu_idlelwp->l_addr->u_pcb.pcb_sp.
Add OF_start_cpu(). Add a routine to ofwoea_initppc to spin up secondary
procs early, and place them into a spinloop waiting for the hatch routines
to be ready.
Modify the ipi routines to deal with openpics that reverse byte order on read
from an ipi register. (such as on the 7044)
Change the rtas setup to allocate the rtas physical base address above
the kernel, to avoid mucking up the hatch/interrupt stacks.
required, because this function will be called for display-consoles only,
and it allows SmartFirmware to attach a rascons console.
Approved by garbled.
them in the mi "files" file, and remove include statements from md files.
These shouldn't pull in additional kernel code when not in use, so it
shouldn't do any harm except a risk of namespace collisions which
should be easy to fix.
1. The 'S' operand field has to be swapped with the 'A' operand in the
output, as long as it is not a store-instruction. To achieve that, I
have introduced a new operand type Op_ST for the store instructions.
2. srawi has an immediate shift count as third operand, not a register.
3. extsh has only two operands, not three.
Convert asm code to use %r register format. Done by comparison to
disassembled output, double checked with diff of dissasembled output
before and after, and test booted on my 7044.
PCI_NETBSD_CONFIGURE. Add some code to hopefully better handle the
firepower and powerstackII, based on the OFW dumps from those machines.
Untested on those machines, but doesn't break anything on pegasos/7044.
gain any benefit from them. This nets a small speedup on the POWER3, and
is probably needed for POWER5, which might not emulate BATs like the 3 does.
Also, thanks to Matt Thomas, who suggested re-using alitrap rather than
writing a new dsinobattrap that would have looked remarkably identical
when finished.
Instead of passing the (un)real system call code and syscall table pointer,
just pass the number of arguments - which is what ktrace really wants.
Ride forthcoming 4.99.53
possibility of running on an MPC601, are infected with all the extra code
and nops that it added.
Also, fix compilation that I broke with the pmap code, by adding
oeacpufeat to the locores of various ppc arches. Noted by mlelstv.
deal with the 64bit bridge mode. pmap changes by Matt Thomas, rest by myself.
Change pmap.c to work similar to exec_elf.c to allow us to compile in
multiple pmaps to a single kernel. This allows the pmap for bridge64 to
co-exist with the 32bit pmap.
Yank __HAVE_PMAP_PHYSSEG from all the oea code.
Add a new global, "oeacpufeat", which is used early in locore to determine
certain cpu features. This allows us to conditionalize code early in the boot
for certain CPUs that have special needs.
Yank most of the ifdef PPC_OEA_BRIDGE64 code from almost every file it was
found in. Some of it seemed incorrect, and my 7044 booted just fine
without it. It would appear that the bridge cpus treat BAT instructions
as nops, so they seem to be safe.
In ofppc, check the oeacpufeat, and if we are on a 64bit proc, clear
MSR[SF], and ASR[V].
With all of these changes, a kernel with both PPC_OEA and PPC_OEA_BRIDGE64
will boot on the POWERIII-2 cpu. However, it will not yet boot on a 32bit
cpu, because of CACHELINESIZE. Work remains to be done there to fix that.
Fix FIRMWORKSBUGS. The #else on one of the ifdefs for it made it so that
it would never work on a machine that didn't need it. This caused IBM
machines to be unable to talk to OFW if the option was enabled. Replace
the #else with a branch and call it good.
Change the pegasos PCI_NETBSD_CONFIGURE arguments around to wire up mem
space into the correct area, and move the io regs a little to make it
work properly. Just avoid the secondary PCI entirely.
Change the list of things that we fiddle with in pci_conf_hook. Map mem
on the fwohci, avoid display cards, avoid IO on the auvia.
Change some printf's to aprint_*
Yank a call to genppc_pci_indirect_make_tag and change it to the
bus-independant pci call instead. (in pci_conf_hook)
