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64 Commits

Author SHA1 Message Date
skrll
4e8e66439e Merge nick-nhusb 
- API / infrastructure changes to support memory management changes.
- Memory management improvements and bug fixes.
- HCDs should now be MP safe
- conversion to KERNHIST based debug
- FS/LS isoc support on ehci(4).
- conversion to kmem(9)
- Some USB 3 support - mostly from Takahiro HAYASHI (t-hash).
- interrupt transfers now get proper DMA operations
- general bug fixes
    - kern/48308
    - uhub status notification improvements
    - umass(4) probe fix (applied to HEAD already)
    - ohci(4) short transfer fix
 2016-04-23 10:15:27 +00:00
macallan
06576a066a moar registers, less tpyos 2016-04-07 01:00:05 +00:00
macallan
677061ce2a Adapt CI20 HWRNG to synchronous on-demand callback. 
Omit needless softint/locking dance.
from riastradh@
 2016-02-17 20:12:42 +00:00
macallan
1ae1c2335b properly initialize the EHCI 
from Alexander Kabaev ( kan at freebsd.org )
 2016-01-02 16:50:52 +00:00
macallan
21e70d0c91 zero out struct i2cbus_attach_args before messing with it 2015-12-14 23:21:23 +00:00
macallan
b9de1f8955 Long overdue suggestions from Taylor Campbell and a few syntax/style 
tweaks from myself.

From Michael McConville
 2015-11-17 16:53:21 +00:00
macallan
6c39fa1448 add some comments 2015-10-14 15:44:57 +00:00
macallan
eaf482297b fix build with INGENIC_DEBUG 2015-10-08 18:20:31 +00:00
macallan
816f56832b use the MAC address passed as a property if available instead of relying on 
u-boot to program it into the chip for us ( which it may not do if we're not
netbooting )
 2015-10-08 17:55:58 +00:00
macallan
56acaa063f add a driver for the chip's EFUSE interface, use it to find the MAC address 
for the onboard ethernet controller
 2015-10-08 17:54:30 +00:00
skrll
c7ae7fb6cf Update for latest dwc2 2015-08-30 13:02:42 +00:00
macallan
05830377d3 add attribution, no functional change. 
from Michael McConville
 2015-08-30 05:09:16 +00:00
macallan
569fb3a720 add driver for jz4780 random number generator 
From Michael McConville
 2015-08-07 17:39:58 +00:00
macallan
7de0cc0eb5 - sprinkle volatile 
- add RNG registers
- fix some comments
 2015-08-07 17:37:54 +00:00
macallan
ede3c3ba87 - get rid of private bus space in ingenic_com.c 
- move com to apbus
- attach the other UARTs
 2015-07-11 19:00:04 +00:00
macallan
1e82b93929 fix tpyos 2015-07-11 18:54:03 +00:00
macallan
ed22b0ef0b fix pasto 2015-05-29 18:47:13 +00:00
macallan
1e554361c1 explicitly un-suspend the OTG port after PHY reset 2015-05-18 15:11:47 +00:00
macallan
b5397a7efc pass the appropriate clock register to devices so different instances of the 
same driver don't have to guess
also wire the ddc2 part to iic4 for now so we can see the monitor
 2015-05-18 15:07:52 +00:00
macallan
1f087e4105 add some clock divider registers 2015-05-18 15:03:16 +00:00
macallan
abaafac606 - fix pclk calculation 
- report CPU clock
- pass mclk to child devices
- wire up pins for MSC / sdmmc
 2015-05-04 12:23:15 +00:00
macallan
d74120f14c moar registers 
( clock and gpio related )
 2015-05-04 12:16:24 +00:00
macallan
0d580d9e18 add entries for sdmmc hosts, no driver yet 2015-04-28 15:08:07 +00:00
macallan
b476f8d357 'USB' -> 'USB OTG' to distinguish this one from the other USB hosts 2015-04-28 15:07:07 +00:00
macallan
dfeb853a61 add sdmmc ('MSC') registers 2015-04-28 15:05:45 +00:00
macallan
f1ea20a105 more bits & registers 2015-04-23 01:20:20 +00:00
macallan
d3361f56e7 enable clocks as needed 2015-04-21 19:57:41 +00:00
macallan
de18a25b0d #define some bits in the clock gating registers 2015-04-21 19:56:01 +00:00
macallan
3aefd491bf fix comments, add LCDC*_BASEs 2015-04-21 19:19:31 +00:00
macallan
66d1b808ee support interrupt-driven transfers 2015-04-21 06:12:41 +00:00
macallan
fb06cc11ce preliminary driver for JZ4780's on-chip SMBus controllers 
needs more work but it's good enough for talking to an RTC
 2015-04-04 12:28:52 +00:00
macallan
ada74a1dcd - determine bus clock, pass it to devices 
- more clock enabling / gpio setup
 2015-03-25 11:25:10 +00:00
macallan
53a48da639 more clock and gpio stuff 2015-03-25 11:23:26 +00:00
macallan
ac1f438869 add SMBus registers 2015-03-19 12:22:36 +00:00
macallan
1b64e3ebad spin up SMBus clocks before attaching drivers 
TODO: only enable clocks for drivers that actually attach
 2015-03-19 12:22:00 +00:00
macallan
4f8ab635ea set root hub vendor IDs 2015-03-17 09:27:09 +00:00
macallan
73612c0da3 always print the child devices' address, print irq if not -1 and a driver 
is actually attaching
 2015-03-17 09:26:31 +00:00
macallan
613f592364 - keep a list of devices, addresses and interrupts in apbus.c 
- pass irq numbers to devices
- reduce magic numbers in device drivers
- allow multiple instances of device drivers
 2015-03-17 07:25:07 +00:00
macallan
9f61ee1762 add SMBus base addresses 2015-03-17 07:22:40 +00:00
macallan
68b2e2bad9 support CI20's onboard Ethernet controller 2015-03-10 18:15:47 +00:00
macallan
4dd5ab1bbe flash the LED to show we're doing something 
( and as a side effect make sure the USB PHY is powered up )
 2015-03-10 18:03:17 +00:00
macallan
f9cd814175 add gpio registers 2015-03-10 18:02:16 +00:00
macallan
2b384ef413 moar devices 2015-03-09 13:24:21 +00:00
macallan
7cae5ebb28 magic number reduction 2015-03-09 13:23:57 +00:00
macallan
c614c4022d moar registers 2015-03-09 13:22:37 +00:00
macallan
e3ba4f1c4e drivers for on-chip ohci and ehci 
ohci works fine, ehci doesn't like high speed devices
 2015-03-08 17:14:27 +00:00
macallan
97f2a49be5 add memory controller registers 2015-03-07 15:36:16 +00:00
macallan
cc7c5632da fix uart parameters, now speed setting actually works 2015-03-07 15:35:33 +00:00
macallan
735afce6b0 restrict DMA buffers to the lower 256MB -> now dwc2 DMA works 2014-12-27 17:22:15 +00:00
macallan
5a85739cac - use the same parameter block as the linux driver, only with DMA disabled 
- reset the chip before handing it to dwc2/
now it actually detects some devices
 2014-12-25 05:13:49 +00:00