simonb
|
c5d34b4371
|
Remove the number of TLB entries for different rx39 CPUs - this info
is in the table in mips_machdep.c now.
|
2002-03-05 16:02:48 +00:00 |
|
uch
|
2c8098281b
|
TX39, R5900 cache configuration.
|
2001-12-02 10:37:25 +00:00 |
|
uch
|
2111496e74
|
Rewrote TX39 series cache routines.
|
2000-08-24 05:31:59 +00:00 |
|
uch
|
e8ebb2a377
|
use mips3 cache op.
invalidate -> write-back invalidate
(although NetBSD/hpcmips run on write-through mode.)
suggested by cgd.
|
2000-07-10 16:23:18 +00:00 |
|
soren
|
a255740671
|
MachForceCacheUpdate and cacheflush_bug have never been used in NetBSD,
so remove references them, and do a little other cleanup.
|
2000-05-23 04:21:39 +00:00 |
|
uch
|
8b01b15437
|
TX3912/22 specific register defines.
|
1999-11-29 11:13:11 +00:00 |