e36e7f175a
Add transmeta crusoe cpu support from toshi.
2001-11-17 08:21:43 +00:00
662f877587
MAXSLP is defined to be a machine-independent scheduling parameter,
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so move it into sys/param.h.
2001-11-15 18:06:11 +00:00
9f8afd5252
Make the type of ports in the in*()/out*() routines u_long instead of
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int. Massively reduced kernel lint, causes no harm. Discussed
extensively with christos and thorpej.
2001-11-13 03:27:50 +00:00
2cff38a9ba
trivially rename some macro parameters to avoid lint warnings.
2001-11-10 22:21:00 +00:00
4475186a1d
correct comment.
2001-11-07 10:52:08 +00:00
3343f31154
explicitly pull in sys/types.h
2001-11-03 06:22:54 +00:00
153d16f7b1
replace __byte_swap_long_variable and __byte_swap_word_variable
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#define ({ }) with static __inline { }
2001-11-02 05:17:59 +00:00
6cb3157ebe
Add defines for the rest of fasttraps as defined on Solaris8/i386. For
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documentation purposes only (though CLOCK_SETTIME a.k.a T_GETHRESTIME
shouldn't be too hard to implement).
2001-10-31 18:20:13 +00:00
e727e3f180
Split elf32 vs. elf64 handling in loadfile(), including support for
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each separately and explicitly. BOOT_ELF is now BOOT_ELF32 and
BOOT_ELF64, and ELFSIZE should no longer be defined in loadfile_machdep.h.
2001-10-31 17:20:45 +00:00
5d461f21ee
Update freebsd_sigcontext to what FreeBSD currently uses, and save/restore
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%fs/%gs as appropriate.
XXX Note that the new sigcontext uses the new sigset_t instead of old
int sc_mask. The new FreeBSD sigcontext doesn't contain any backward
compatibility sc_mask, so basically old FreeBSD application making
use of sigcontext are hosed. This can't be fixed in NetBSD compat code.
2001-10-27 12:26:29 +00:00
cbc00e701a
Until early last year, the i386 port had 256M of kvm, and the max.
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amount of kvm used for buffers was set at 70%, some 188M. Then
the total amount of kvm became 1G, and the amount for buffers
thus became some 716M. This is really too much, and some
device drivers want to map quite a bit of kvm these days.
So, cap it at 384M, which gives each buffer a little over 8k (the
default FFS blocksize) physical in an 1G physram configuration.
2001-10-20 00:17:47 +00:00
3d5c31f282
Bah, fix typo that crept in (tank you vi(1)).
2001-09-28 01:50:04 +00:00
abd2c67167
Machine-dependent ACPI CA Osd routines for i386.
2001-09-28 01:46:56 +00:00
f5599abc0a
fix typo
2001-09-23 19:59:19 +00:00
808d23f484
{,u}intptr_t are longs; adjust printf/scanf formats.
2001-09-19 05:23:43 +00:00
3792a5d8c5
Add code to frob the MTRR-like registers on the AMD K6-2
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and AMD K6-III.
2001-09-19 01:26:18 +00:00
d941f3b164
Define UWCCR bits for the AMD K6 (these are its MTRR-like registers).
2001-09-19 00:31:21 +00:00
f0d792297e
Define the AMD K6 cache/write-combinding control register MSR.
2001-09-19 00:30:11 +00:00
9185cf1b34
Add mtrr.h to INCS list to get installed on a make includes
2001-09-12 04:44:21 +00:00
0e7661f023
Update pmap_update to now take the updated pmap as an argument.
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This will allow improvements to the pmaps so that they can more easily defer expensive operations, eg tlb/cache flush, til the last possible moment.
Currently this is a no-op on most platforms, so they should see no difference.
Reviewed by Jason.
2001-09-10 21:19:08 +00:00
78742dd0e0
Add flag to indicate that a process set some mtrrs that need to be
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cleaned up automatically on exit.
2001-09-10 10:11:21 +00:00
c823d05ca0
Add definitions for mtrr syscalls.
2001-09-10 10:10:57 +00:00
e0a68652a8
MTRR include file, based on the one by Bill Sommerfeld from the i386 mp
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branch.
2001-09-10 10:10:33 +00:00
edea1a2c17
Make it possible to query each battery individually by making the
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APM_IOC_GETPOWER ioctl read/write. Setting the batteryid in the passed
structure returns the data for just that battery. The old ioctl
remains for binary compatibility but has been renamed.
Itojun already did the hard work -- I just added a couple of lines.
reviewed by: thorpej
2001-09-10 05:23:30 +00:00
47920741b0
Implement bus_space_mmap().
2001-09-04 02:37:08 +00:00
9fa41ab3b9
use cli/sti instead of splhigh/splx for MCOUNT_ENTER/MCOUNT_EXIT.
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this makes clearer how much time mcount() is really taking.
2001-08-23 06:17:00 +00:00
7c661278ee
update some comments.
2001-08-12 00:20:32 +00:00
518ad20222
Upon further reading of the manual, don't save the MXCSR-at-last-exception.
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Its status bits are sticky, and unaffacted by FNINIT.
2001-08-03 01:46:08 +00:00
099e93139b
In setregs(), initialize the process's MXCSR to the reset-default
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value as documented in the IA-32 Instruction Set Reference (in the
description of the LDMXCSR insn).
2001-08-03 01:24:39 +00:00
f72ee0a9c6
Remember the MXCSR at last-exception the way we do the FPU SW/TW.
2001-08-03 01:11:49 +00:00
3f5acd41c2
Remove trailing "U" on KERNBASE introduced in last commit.
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Breaks assembly of locore.
2001-08-03 01:03:10 +00:00
6e331fdd9f
Define KERNTEXTOFF in terms of KERNBASE.
2001-08-03 00:47:59 +00:00
f0449fd933
- Rename cpu_use_fxsave to i386_use_fxsave.
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- If we detect SSE/SSE2 support in the CPU, enable SSE exceptions
and set i386_has_{sse,sse2} as appropriate.
- Expose i386_use_fxsave and i386_has_{sse,sse2} through sysctl
as machdep.{osfsxr,sse,sse2}.
2001-08-02 22:04:28 +00:00
99a7f640fe
Add support for saving/restoring SSE/SSE2 state using FXSAVE/FXRSTOR.
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Reviewed by Frank.
2001-08-02 21:04:43 +00:00
4b584bf5bb
Add several more Intel cache info entries, and fetch the CFLUSH
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line size if we have the CFLUSH insn.
2001-08-01 19:50:48 +00:00
ebbd9cd428
Add some more CPUID feature bits.
2001-08-01 18:47:38 +00:00
c43f8649d2
Set up function pointers for copyin/copyout in preparation for
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adding optimized versions for various CPU classes/models.
Split the 386 version of copyout into a separate routine, and
add a 486 version that doesn't have the class/page-writeability
check.
2001-07-31 18:28:58 +00:00
71aa31a75a
support multiple batteries (currently only # of batteris is visible -
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need to tweak ioctl API more). PR 10545.
2001-07-22 16:05:17 +00:00
a9356936b4
seperate -> separate
2001-07-22 13:33:58 +00:00
babefc5331
Add BUS_DMA_READ and BUS_DMA_WRITE flags, that hint the back-end
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at dmamap load time that the mapping will be used for a unidirectional
transfer of the specified direction.
2001-07-19 15:32:10 +00:00
d68e2c3f12
Redefine evil tXXX register offset defines into the trapframe structure
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to use offsetof. These should be completely nuked.
Fixes math_emulate lossage.
2001-07-17 08:13:06 +00:00
091e29f94f
In i386_softintr_lock(), use splserial() rather than splhigh(),
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because of splhigh() braindamage on the i386 port.
Fixes port-i386/13038 and port-i386/12985.
2001-07-16 16:53:00 +00:00
825843808a
add MACHO_MACHDEP_CASES
2001-07-14 03:05:51 +00:00
747d93e317
new i386 files for macho and mach.
2001-07-14 02:04:25 +00:00
75dabe22c7
Use global descriptor 7 for mach traps. Unfortunately this is already
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used by apm 16 bit code segments so we cannot have both at the same time.
2001-07-14 02:02:45 +00:00
e26fe5cc01
Compute the VM_* constants directly, rather than hard-coding
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them (with the formulas in comments).
2001-06-25 16:28:48 +00:00
f3f6c5b675
`accessible' only has one `a'.
2001-06-19 12:52:20 +00:00
b4b5dc533d
Add fxsr CR4 bits.
2001-06-19 09:12:49 +00:00
7e7d262c34
Add %fs/%gs to trap frame and save/restore them on
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trap/interrupt/syscall entry from userspace.
Remove special-case "by hand" validation of fs/gs register values as
well as special handling of them in various signal handling paths.
Now, like %ds and %es, they are validated by the hardware on return to
userland.
This paves the way for the use of %fs for per-cpu data on
multiprocessor systems, and fixes an otherwise difficult-to-fix
interaction between threads/clone(2) and USER_LDT.
Discussed in advance with Frank van der Linden.
2001-06-17 21:01:32 +00:00
8eb3b954f1
Don't need to prototype child_return() here, it's in <sys/proc.h>.
2001-06-14 22:56:55 +00:00
christos