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2729bcfb69
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33279 Commits

Author SHA1 Message Date
scw
2729bcfb69 - Use intrnames[] instead of rolling our own. 
- Update intrcnt[level] in sh5_intr_dispatch().
 2002-10-08 15:55:07 +00:00
scw
e0248b775a intrnames has moved to board-specific code. 2002-10-08 15:53:04 +00:00
scw
f07358cb66 - Make sure not to sign-extend the PA of KSEG0, particulary in 64-bit mode, 
- Moved intrnames/eintrnames here, since they're pretty much board-specific.
 2002-10-08 15:52:02 +00:00
scw
a5719508fe Get DB_ELFSIZE for 64-bit kernels. 2002-10-08 15:49:26 +00:00
augustss
b45db92e85 Add ubsa attachment. 2002-10-08 13:09:05 +00:00
jdolecek
e72c35e47e tag the cdevsw as tty with D_TTY 2002-10-08 08:57:52 +00:00
bjh21
8bd749851d Special locking primitives for use in Hydra kernels. These include a cache 
invalidation after every lock to ensure that changes made by other CPUs are
visible.  This has nasty performance implications, but it does allow my
Hydrated Risc PC to run printf() on all its CPUs at once without corrupting
the message buffer.
 2002-10-07 23:23:53 +00:00
bjh21
5a9767e3de Minor tidy-up, mostly to improve readability. The SWP instruction is now 
in its own little inline function, and this allows us to get rid of all the
automatic variables elsewhere.  This subtly changes the semantics of
__cpu_simple_lock() such that the loop ends up one instruction longer, but
I'm not sure that's a particularly bad thing.
 2002-10-07 23:19:49 +00:00
jdolecek
4140408d7e g/c empty apmpoll(), use nopoll() instead 2002-10-07 21:32:10 +00:00
martin
e91fcc8060 Remove obsolete and unused file (there still is ../include/asm.h, which is 
shared with sparc)
 2002-10-07 20:01:46 +00:00
scw
2657f0ac37 Ensure the temporary mapping for /dev/mem is flagged as unmanaged. 2002-10-07 15:05:58 +00:00
scw
88e1242876 Lots of small changes, some functional, some cosmetic. 
The main bug fixes are:
 - pmap_pvo_remove() must calculate the kipt index if the idx param is -1.

 - Don't assume that if a pmap's ASID generation is out of date that we
   can skip purging/invalidating the cache for any of its constituent
   mappings. At this time, the ASID generation just indicates that none
   of its mappings are in the TLB. However, there may still be some valid
   cache entries for them.

Finally, the subtle NFS and buffer cache corruption problems disappear.
 2002-10-07 15:02:07 +00:00
martin
bbdf4c9e6d Remove unused file, superseeded by syssrc/dev/sun/fb.c. 2002-10-07 14:57:53 +00:00
scw
199e165526 Add a cacheop for purging/invalidating the whole operand/insn caches. 
This is currently not used (actually, it was used locally for a short time
while tracking down a pmap bug), but is here in case it's needed later.
 2002-10-07 14:48:14 +00:00
scw
9bbc15e3a1 Add a SH5_PTEL_CACHEABLE() macro which evaulates TRUE if the specified 
PTEL describes a cacheable mapping.
 2002-10-07 14:42:31 +00:00
martin
44a2c6cb31 All sparc64 CPUs do __HAVE_CPU_COUNTER (aka %tick). 2002-10-07 13:26:56 +00:00
scw
c3ed42912c Simplify the scsibus attatchment as pointed out by Simon Burge. 2002-10-07 08:20:07 +00:00
fvdl
570d69db6e Remove ifdef LOCKDEBUG, this file is only compiled when it is defined. 2002-10-07 07:58:26 +00:00
fvdl
288a0ddc5d lock_machdep.c only depends on LOCKDEBUG, in which case it's also 
needed in the non-MP case (since pmap.c now calls __cpu_simple_lock
directly)
 2002-10-07 07:54:31 +00:00
fvdl
fb2f78f8b5 Put DDB stubs inside ifdef DDB, PR 18563. 2002-10-07 07:11:59 +00:00
thorpej
7bbf61fd89 Add support for restartable atomic sequences on 26-bit ARM. Compile 
tested only.

Now that all ARM systems have RAS, move __HAVE_RAS from arm/arm32/types.h
to arm/types.h.
 2002-10-07 02:48:38 +00:00
fvdl
d1cbc91464 Remove ci_lapic_ints from struct cpu_info again, it isn't needed anymore. 2002-10-06 20:40:27 +00:00
fvdl
3319c2f2dc Add cpu_id field to mp_intr_map structure. Declare mp_nintr. 2002-10-06 20:39:33 +00:00
fvdl
f493e906e6 Handle per-CPU local apic redir entries a little better. My previous 
solution relied on CPU entries coming first in the table, which
isn't guaranteed. Instead, export mp_intrs to lapic.c, and scan
it for entries that match the current CPU in lapic_set_lvt().

Also, do not try to up intr_cnt by the number of IO APICs or CPUs in
the case of MPS_ALL_APICS; it isn't needed, and it also relies on
CPU and IO APIC entries being earlier in the table.
 2002-10-06 20:38:37 +00:00
fvdl
be146319cd Keep size of struct cpu_info independent of DIAGNOSTIC/LOCKDEBUG 
(was done in rev. 1.81, got lost in the MP merge).
 2002-10-06 18:31:21 +00:00
bjh21
c62984115f Turn curcpu() into a macro. 
Rename cpu_info_array to cpu_info and make it public.
Add CPU_FOREACH() and friends.
 2002-10-06 18:28:48 +00:00
thorpej
70cc64f942 Make this compile with strict prototypes. 2002-10-06 17:13:58 +00:00
fvdl
f8a5d4e00c Handle per-CPU local APIC redir tables in the MP BIOS. 2002-10-06 14:28:55 +00:00
fvdl
85eaacd06e Add per-CPU local apic redir table (2 pointers). 2002-10-06 14:28:17 +00:00
bjh21
1f17ac8831 Remove footbridge and isadma glue -- these no longer seem to be necessary. 2002-10-06 13:05:39 +00:00
bjh21
682415134d Call cpu_setup() and cpu_attach() from cpu_hydra_hatch(). 
Also simplify cpu_hydra_attach() somewhat.
 2002-10-06 12:37:59 +00:00
fvdl
a2e301721c cpu_swapin now exists, so remove the empty define. 2002-10-06 12:37:35 +00:00
fvdl
2560973204 If NOREDZONE is defined, keep UPAGES at 2 as before. 2002-10-06 12:37:12 +00:00
fvdl
5e33ec48d8 Define NOREDZONE and use it in the *_TINY config files to save a page 
per process.
 2002-10-06 12:36:16 +00:00
fvdl
14c70e4627 Put an unmapped page below the kernel stack (and above struct user) to 
catch kernel stack overflows. This bumps UPAGES from 2 to 4 (one unmapped),
because struct user take 1 page then there's the unmapped page, and
then the 2 pages for the kernel stack. If the NOREDZONE option is
set, UPAGES is 2 as before, and no unmapped page is used.
 2002-10-06 12:35:16 +00:00
bjh21
c775c3e73c Give each CPU a struct cpu_info, and have curcpu() return the right one. 
Also have cpu_boot_secondary_processors() un-halt all the slave CPUs, and
have them do something visible when that happens.
 2002-10-06 11:34:12 +00:00
bjh21
8e25492f64 Make cpu_number() work. 2002-10-06 10:21:50 +00:00
bjh21
f68de9a752 Use HYDRA_ID_SLAVE_MASK rather than 3. 
No need for an infinite loop after we jump out of hydra_hatchcode.
 2002-10-06 10:21:10 +00:00
provos
d1c3210192 regen from GENERIC.in 2002-10-06 03:00:02 +00:00
provos
fbc128def8 add SYSTRACE here; pointed out by lukem 2002-10-06 02:58:21 +00:00
tsutsui
a7933969a6 Sync with GENERIC. (systrace and other misc options) 2002-10-06 02:50:28 +00:00
tsutsui
a9ca52263a Sync with GENERIC: 
- Add options SYSTRACE
- Add (commented out) options for semaphores
 2002-10-06 02:31:38 +00:00
provos
2f7a0aaac8 add SYSTRACE; approved perry. 2002-10-06 02:11:54 +00:00
bjh21
bb6b27b143 Second phase of Hydra attachment: All CPUs are now set up sufficiently that 
they can call printf(), which they do before halting.
 2002-10-05 23:30:03 +00:00
bjh21
389f612a10 Remove spurious comment. 2002-10-05 23:26:48 +00:00
chs
993948e989 count executable image pages as executable for vm-usage purposes. 
also, always do the VTEXT vs. v_writecount mutual exclusion
(which we previously skipped if the text or data segment was empty).
 2002-10-05 22:34:02 +00:00
fvdl
9110a093d8 Do rendezvous for TLB shootdown IPI. The sender sets a bitmask 
of all CPUs it wants entries shot down on, and waits until it
clears. pmap_tlb_doshootdown clears the bit of the current CPU
in this mask.

Also, change simple_lock -> __cpu_simple_lock in IPI path.
 2002-10-05 21:30:42 +00:00
fvdl
c55b2f6fa9 Define XINTR_TSS 2002-10-05 21:29:01 +00:00
fvdl
2153e9d81a Adjust callers to setgate() to match new extra parameter. 2002-10-05 21:28:34 +00:00
fvdl
1176155ea2 Protect against multiple inclusion. 2002-10-05 21:27:52 +00:00