address shift (stride). This is necessary because many podules have standard
chips with odd address-bus wiring to allow for using LDM for
bus_space_*_multi_*().
<dev/podulebus/podulebus.h> is the canonical file to include, and includes
<machine/podulebus_machdep.h>.
<arch/${MACHINE}/poudulebus/podulebus.h> remains for backward compatibility.
always points to the undefined instruction in question. It's up to the
handler to advance it to the next instruction if it wants execution to
continue there. This is how things have always worked on arm26.
co-processor. This is necessary so we can have several handlers for
CP0 (used as a catch-all for non-CP instructions).
Handlers are now removed using remove_coproc_handler(), rather than by calling
install_coproc_handler() with a NULL handler.
Because install_coproc_handler() can now allocate memory, there's a version
for use at boot time that doesn't.
is derived mostly from the arm32 version, but with a check for an obscure ARM2
bug thrown in.
arm26 fpu and cpu drivers use the new interface for catching undefined
instructions.
Excise unnecessary instructions from kernel launch code.
Increase HIMEM on >8Mb machines, since the last two changes didn't free
enough memory to boot with 16Mb.
arm32/arm32/machdep.c into arm/arm/sig_machdep.c, merging and ANSIfying in
the process.
The code is based on the arm32 version, so I don't think anything should break
there.
Also, most device functions related to IRQ handling no longer take a device
pointer. We make so many assumptions about the machine's layout in irq.c that
this just seemed silly.
The architecture here follows that of the vax port -- each device has its
evcnt in its softc, but defers actually incrementing it to the IRQ
dispatcher. This way, devices can attach sub-counts (e.g. Rx and Tx counts
for Ethernet interfaces), but don't all have to have code to increment the
counters.
Drivers deliberately call evcnt_attach_dynamic() before establishing their
interrupt handler so that the establish routine can attach a parent event if
that's appropriate. At present, it isn't.
The architecture here follows that of the vax port -- each device has its
evcnt in its softc, but defers actually incrementing it to the IRQ
dispatcher. This way, devices can attach sub-counts (e.g. Rx and Tx counts
for Ethernet interfaces), but don't all have to have code to increment the
counters.
Drivers deliberately call evcnt_attach_dynamic() before establishing their
interrupt handler so that the establish routine can attach a parent event if
that's appropriate. At present, it isn't.
NULL "name" argument to irq_establish indicates that the device will maintain
an evcnt structure for this interrupt. In this case, irq_establish will still
maintain its own count (for DDB machine irqstat), but won't attach it to the
global list.
Change use of ev_group and ev_name to follow guidelines in evcnt(9).
Switch arckbd(4) over to the new arrangements.
This adds support for EtherExpress/16 cards with 16k of RAM, and in the
process adds general support for PIO mode on these cards. This entails
changing the way the i82586 driver handles bus barriers, since it doesn't
allow for strange cases like this.
This has been tested on the i386 port with the 'ix' driver in both
16KB (which was the source of the problem) and 32KB modes, as well
as with the 'ef' driver. I've tested it (briefly) with 'ei' on arm26
as well. In theory, drivers other than 'ix' should follow precisely the
same code paths as before.
and link it directly to db_command_table[] so that it's not necessary
to do this at runtime. Make db_machine_command_table[] const on all ports.
g/c now unneded stuff, like db_machine_commands_install(), db_machine_init()
Patch written by enami.
shape as the old arm32 one, but there are a few #defines to keep arm26 code
happy. Anything that depends on the precise shape of the trapframe,
and especially on being able to treat it as an array of registers, has been
updated.
Yes, this causes binary incompatibility. Yes, it's Evil, Bad and Wrong.
Nonetheless, I think it's probably the least unpleasant way to get close to
binary compatibility with NetBSD/arm32, and a very much doubt there are any
arm26 binaries out there that depend on the old shape of struct sigcontext.
and place the definition in <machine/types.h>. This can now be used
as a flag to indicate whether or not <machine/intr.h> can be included
to get the generic soft interrupt API.
arm32/arm32/in_cksum_arm32.c -> arm/arm/in_cksum_arm.c
Also move specification of other checksum stuff to files.arm, even though we
use the MI code for that.
bjh21