requires that the CPU control vector be properly readable. I believe that
all CPUs that have high vector support have a readable CPU control register,
but if we ever encounter one that does not, then we'll have to adjust this
code.
Some features of the new pmap are:
- It allows L1 descriptor tables to be shared efficiently between
multiple processes. A typical "maxusers 32" kernel, where NPROC is set
to 532, requires 35 L1s. A "maxusers 2" kernel runs quite happily
with just 4 L1s. This completely solves the problem of running out
of contiguous physical memory for allocating new L1s at runtime on a
busy system.
- Much improved cache/TLB management "smarts". This change ripples
out to encompass the low-level context switch code, which is also
much smarter about when to flush the cache/TLB, and when not to.
- Faster allocation of L2 page tables and associated metadata thanks,
in part, to the pool_cache enhancements recently contributed to
NetBSD by Wasabi Systems.
- Faster VM space teardown due to accurate referenced tracking of L2
page tables.
- Better/faster cache-alias tracking.
The new pmap is enabled by adding options ARM32_PMAP_NEW to the kernel
config file, and making the necessary changes to the port-specific
initarm() function. Several ports have already been converted and will
be committed shortly.
Right now, only power switch state change events are supported. This
is a work-in-progress.
* Add support to sysmon for delivering power mangement events to userland.
Add poll, kqueue, and read entry points to sysmon.
* Adapt ACPI to use the new generic <sys/power.h> event types.
This provides the kernel support for a forthcoming powerd(8) which can
do nice things like gracefully shut the system down when an ACPI power
button is pressed.
ILP32 platform.
What happens is that the compiler inserts padding in struct mbuf between the
MH_pkthdr and MH_dat members, due to the paddr_t in struct _m_ext.
Unfortunately, the old MLEN/MHLEN macroes fail to take into account this
padding and, thus, wind up making sizeof(struct mbuf) > MSIZE. This causes
mbuf corruption, which eventually leads to all sorts of bogosity on ILP32
platforms with a 64-bit paddr_t.
Thanks to simonb@ and fvdl@ for helping to track down this bug.
thorpej