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19 Commits

Author SHA1 Message Date
mark 4285910912 Implement faster method of blocking all lower priority interrupts. 
Modify current_spl_level to reflect the temporary change in interrupt
priority level which dispatching.
Don't increment the interrupt stats for every handler in the interrupt chain.
Cleaned up a number of comments.
Define soft interrupt names.
A few miscellaneous tidy ups.
 1998-09-05 04:05:31 +00:00
mark 4a463e49fe defopt CPU_* options in opt_cputypes.h 1998-07-07 03:05:15 +00:00
mark c73c7674d7 defopt IRQSTATS. 1998-07-06 00:53:07 +00:00
mark bdfeab3714 Merge in UVM support from Neil Carson <neil@causality.com>. 1998-06-02 20:41:46 +00:00
mark b2286e384a Include machine/asm.h and use the macros from there for declaring 
the function entry points.
Removed some redundant .req statements.
 1998-04-01 23:09:06 +00:00
mark 06d8713b3d arm32 kernel source restructure. 
- IOMD specific interrupt handling. These files are mainly the old
    arch/arm32/irq* files moved here and updated for new iomd device etc.
    (revision history maintained).
 1997-10-14 11:05:58 +00:00
mark 187f8c7c3d Remove local definitions of macros to push and pull trapframes and instead 
include machine/frame.h to get these definitions.
 1997-02-10 03:50:53 +00:00
mark e626201c12 Adopt as standard, the instruction sequence for storing the trapframe that 
includes the workaround from the SA110 STM^ bug. This allows one piece of
code to be used to store the trapframe on all CPU types.
 1997-02-04 06:49:08 +00:00
mark bc3f67bb21 Use the irqblock array to provide the information about which interrupts 
should be blocked for each irq currently asserted.
 1997-01-06 02:35:46 +00:00
mark 9c855e4d1b Provide alternative trapframe push and pull macros from the StrongARM. 
These alternative macros have a workaround for the STM^ bug in revision < 3
StrongARM CPU's that causes incorrect register saving if a cache line fill
is in progress during the STM.
 1996-11-23 04:02:40 +00:00
mark 81f6df323e *Major* rewrite, long overdue. 
The irq delivery code has been rewritten. On entry to the irq vector the
processor is switched to SVC32 mode so all interrupt routines now run
in SVC32 mode rather than IRQ32 mode. This fixes lots of irq re-enabling
problems.
Interrupt latency times are now vastly improved for high priority interrupts.
Cleaned up calling ast() before returning to USR32 mode (don't need to
mess about with trapframe copying.
Cleaned up all the comments and sorted out their indentation.
Rewritten the soft interrupt delivery code.
Added generic ARM7500 support rather than just RC7500 support.
 1996-10-15 23:20:40 +00:00
christos ad67e04154 backout previous kprintf change 1996-10-13 16:50:51 +00:00
christos 60dd5ceebe printf -> kprintf, sprintf -> ksprintf 1996-10-11 00:06:28 +00:00
mark 459cefbe67 Added support for the RC7500 interrupt registers 
Added interrupt chaining.
Removed some dead debugging code.
Guarded several sanity checks with #ifdef DIAGNOSTIC
Make sure interrupts are disable while updating the IOMD interrupt
masks.
 1996-06-12 20:19:35 +00:00
mark 181c7ad5cd Added a new function fiq_getregs() to transfer the FIQ mode register 
into a fiqhandler structure.
Updated fiq_setregs to use symbols in assym.h for offsets into
fiqhandler structures.
 1996-05-06 00:25:43 +00:00
mark 47804c6e17 Table of interrupts names has been padded out to 14 characters so that 
it can be filled in when interrupt handlers are attached. Table moved
from the text area to the data area.
 1996-03-27 20:42:53 +00:00
mark e03778a035 Updated irq names, replaced reserved irq 1 with irq softclock. 1996-03-08 20:44:13 +00:00
mycroft fc9d84fb46 assym.s -> assym.h 
(Some ports did this already.)
 1996-02-02 02:34:09 +00:00
mark 386ad2ff0f Initial commit of the NetBSD/arm32 port. 1996-01-31 23:14:53 +00:00