-optionally, use Martin's direct hardware access to serial lines
-optionally, new console autoselection method: select serial console
if a character is seen within 1 second
-move awaitkey() here, it can be shared by different bootloaders and
it is used by console autoselection
-collect information about console selection in a "bootinfo" defined
structure, for passing to the kernel
separated "nfswrapper.c"/"nfs.c".
This nfs.c differs from the stand/lib/libsa one in that it does not
have a separate mount() function - the mount is done in open().
on EV56 and later processors that have the "amask BWX" bit clear. These
instructions will be used to implement non-swizzle bus access functions
on newer systems, such as the new AlphaStation 500s with EV56 and 21172
PCI chipsets.
See "Alpha Architecture Handbook, Version 3", DEC order number EC-QD2KB-TE.
* support chip clocks != COM_FREQ, by introducing sc_frequency (for the
mainline code) and adding a frequency parameter right after the rate
parameter to comcnattach() and com_kgdb_attach().
- Make com_isa and com_multi initialize sc_frequency to COM_FREQ.
- Make i386/machdep.c and alpha/dec_xxx.c call com*attach() with the freq.
parameter.
* supio_attach_args get two more fields: a sc_ipl and a sc_arg, both ints.
- com_supio uses the first for interupt establishment (all childs will, as
soon as they exist) and the 2nd for sc_frequency.
- drsupio passes sc_ipl alway as 5, and for the "com"s, sc_arg as 16*115200
- hyper will pass sc_ipl as 6, and sc_arg as 16 * 460800
- Fix a few bugs in the software single-stepping support code, where
VMS PALcode ops were being checked, rather than OSF/1 PALcode ops,
causing erroneous results in the "exception return" and "unconditional
branch" predicates.
- Add the BWX instructions ("ldbu", "ldwu", "stb", "stw") to the
"load" and "store" predicates.
easier to add instructions that the disassembler doesn't know about
(the opcode subfunction number is now printed).
- Add the "amask" and "implver" operate subfunctions.
- Add the "ldbu", "ldwu", "stb", and "stw" major opcodes (BWX instructions).
An IMB intruction must be executed after software or I/O devices
write into the instruction stream or modify the instruction
stream virtual address mapping, and before the new value is
fetched as an instruction.
We were missing calls to IMB after mappings were changed, which caused
systems with large I-caches (e.g. my AlphaStation 500) to fail miserably
when mapping in new pages of program text, or when context switching
(I couldn't even get the shell from init!).
reads. This is necessary because of newer AlphaStation firmware doing
the Wrong Thing with target aborts behind PCI-PCI bridges, much like they
do the Wrong Thing with master aborts. Reported by Matthias Drochner.
use the `a_entry' field from the kernel's header as a base.
Pass on a new DDB magic number to the kernel, so kernels linked for a
different KERNBASE value can apply a correction when booted from old
bootblocks.
drochner