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1536 Commits

Author SHA1 Message Date
simonb
4ebec9cd61 Add a define for the size of the UART register block. 2003-11-08 05:49:08 +00:00
simonb
edaec67118 Use the COM_AU1x00 option for Au1x00 feature support. 2003-11-08 05:12:51 +00:00
simonb
52f438d9a8 Sync with com.c, rev 1.222. 2003-11-08 05:10:11 +00:00
simonb
8899101173 Add a "COM_AU1x00" option, similar to COM_PXA2X0, for enabling Au1x00 
features in the "com" driver.
 2003-11-08 05:05:14 +00:00
simonb
4116da8027 Sync with dev/ic/com.c rev 1.221. 2003-11-07 02:08:35 +00:00
simonb
f3bced434d Try using matching numbers of open and close parentheses to make this 
compile again.
 2003-11-06 04:17:11 +00:00
dsl
2ffbd2ab99 Remove p_nras from struct proc - use LIST_EMPTY(&p->p_raslist) instead. 
Remove p_raslock and rename p_lwplock p_lock (one lock is enough).
Simplify window test when adding a ras and correct test on VM_MAXUSER_ADDRESS.
Avoid unpredictable branch in i386 locore.S
(pad fields left in struct proc to avoid kernel bump)
 2003-11-04 10:33:15 +00:00
simonb
20db9285ba Kill trailing blank lines. 2003-11-02 08:29:06 +00:00
christos
38dd4ae2dc Initialize another fp instance 2003-11-02 08:27:41 +00:00
christos
6dba5c3bc3 only assign to fp when we have a valid lwp. Thanks simon 2003-11-02 08:20:48 +00:00
christos
df7d5f4716 Use siginfo_t not ksiginfo_t in the frame. Doh! 2003-11-02 08:20:09 +00:00
tsutsui
fe1d71458c - Flush cache only if mips_sdcache_line_size == 0 in pmap_copy_page() when 
options MIPS3_L2CACHE_ABSENT is defined.
- Fix comments following #endif for MIPS3_L2CACHE_ABSENT.
 2003-11-01 14:48:16 +00:00
shin
70f5a0a5b2 cache_r10k.c rev. 1.1 is broken. Because, 
1) R10k uses VA0 to select cache ways, but in rev. 1.1, VA14
	   is used instead.
	2) R10k does not support HitWriteBack and should map HitWriteBack
	   to HitWriteBackInvalidate, but in rev. 1.1, HitWriteBack is not
	   handled properly.

So, cache_r10k.c rev. 1.1 was replaced by new implementation.
 2003-11-01 04:42:56 +00:00
cl
ef56cc40ab Reduce code duplication by adding mi_userret() in sys/userret.h 
containing signal posting, kernel-exit handling and sa_upcall processing.

XXX the pc532, sparc, sparc64 and vax ports should have their
XXX userret() code rearranged to use this.
 2003-10-31 16:44:34 +00:00
drochner
0622a85590 don't need ELF_INTER_NON_RELOCATABLE anymore if no COMPAT_16, from simonb 2003-10-31 14:06:29 +00:00
simonb
183066a619 Remove some assigned-to but otherwise unused variables. 2003-10-31 03:32:19 +00:00
simonb
6d85c5e0d5 Don't pass the (unused) return value args to the 
trace_enter()/systrace_enter() functions.
 2003-10-31 03:28:12 +00:00
christos
2c8096f763 set the onstack flag if requested. 2003-10-30 00:26:54 +00:00
simonb
0c6a00f6c6 KNF. 2003-10-30 00:01:47 +00:00
simonb
31d051445b Make this 64-bit paddr_t friendly. 2003-10-29 23:52:22 +00:00
christos
dc307db22e add compat_16_machdep.c 2003-10-29 23:41:49 +00:00
simonb
0bf7a721e9 Add some more MTI CPU ids. 2003-10-29 23:41:10 +00:00
christos
61e4914300 first pass siginfo for mips 2003-10-29 23:40:42 +00:00
christos
8ca558e8ed first pass siginfo glue for mips 2003-10-29 23:39:45 +00:00
simonb
a5ace5a563 Add some more MIPS vendor IDs. 2003-10-29 23:39:16 +00:00
simonb
6836656005 Remove assigned-to but otherwise unused variables. 2003-10-27 02:58:31 +00:00
simonb
8338dcf797 More bogus uninitialised warnings. 2003-10-27 02:16:15 +00:00
simonb
eeb03b3e1b "Fix" bogus gcc3 uninitialised warning. 2003-10-27 01:17:59 +00:00
kleink
a3fabb9e7f Use <sys/ieee754.h> where applicable. 2003-10-26 20:55:30 +00:00
mycroft
b1915c81d6 Oops, in the fpe_trap case, actually leave it storing $a2 in the $a3 stack 
slot.  This is a hack.
 2003-10-25 22:10:34 +00:00
mycroft
cde8e7d93d Store $a1 (and $a2 in another case) in the correct stack slot. 2003-10-25 22:06:59 +00:00
mycroft
fd8bb946a3 Update for GCC3 (basically, use the __builtin_va_* implementation). 2003-10-25 18:14:48 +00:00
simonb
49a8cd4e3a Rename the "strtc" device to "m41t81rtc" so that it doesn't conflict with 
the MI i2c "strtc" device.
XXX: This should use the MI "strtc" device - the M41T81 should be
     compatible enough with the M41ST84 currently supported by that
     driver.
 2003-10-25 15:05:00 +00:00
simonb
e93422fa5f Remove "struct aubus_ohci_softc". As well as ohci_softc_t, it only had 
a copy of the interrupt cookie which isn't used outside the attach.  We
has also bogusly only told the autoconfiguration machinery that our softc
was as big as a ohci_softc_t, not a struct aubus_ohci_softc.
Also, disestablish the interrupt if OHCI initialisation fails.
 2003-10-23 04:58:32 +00:00
tsutsui
bf4d10546f vaddr_t is not pointer, so don't compare it against NULL. 
(BTW, should we also fix "NULL" in following printf messages?)
 2003-10-21 15:05:56 +00:00
simonb
513b330566 Tell the Alchemy Au1x00 on-chip ohci that we're in big-endian mode if 
necessary.
 2003-10-18 04:34:30 +00:00
simonb
136dd90b25 Remove unused ohci stub. 2003-10-18 04:31:37 +00:00
simonb
07c9a24e6a One defintion of OP_SYNC should be enough. 2003-10-15 06:46:46 +00:00
tsutsui
c74700fe65 It seems r4k_sdcache_wb_range_NN() function can't handle 
R10000 L2 cache (which is 2-way set-associative write-back),
so use r4k_sdcache_wbinv_range_NN() for workaround until someone
implement proper r10k_sdcache_*() ops.

Problem reported by Christopher SEKIYA.
 2003-10-11 09:09:15 +00:00
thorpej
901da40cf9 Add some accessor macros for the ucontext: 
* _UC_MACHINE_PC() - access the program counter
* _UC_MACHINE_INTRV() - access the integer return value register
* _UC_MACHINE_SET_PC() - set the program counter (this requires
  special handling on some platforms).
 2003-10-08 22:43:01 +00:00
tsutsui
61b40c3946 Update comment to follow the previous R4000 ID addtion. 2003-10-05 17:31:09 +00:00
tsutsui
779268c4cf Define ELF2ECOFF here for native build. 
(BTW, objcopy with OMAGIC kernel won't work on old pmax and sgimips machines?)
 2003-10-05 16:53:15 +00:00
tsutsui
d1a36ee086 Include opt_mips_cache.h for options MIPS3_L2CACHE_ABSENT and 
MIPS3_NO_PV_UNCACHED.
 2003-10-05 16:38:03 +00:00
tsutsui
800933ed42 No need to include opt_mips_cache.h here. 2003-10-05 16:34:51 +00:00
tsutsui
14658b124b Add R10000 cache ops, written by KIYOHARA Takashi and posted on port-sgimips. 
Enabled by options ENABLE_MIPS4_CACHE_R10K for now.
 2003-10-05 11:10:25 +00:00
simonb
457cdc6624 Quieten down lint a little with a /* LONGLONG */ comment. 2003-10-01 15:47:27 +00:00
tsutsui
e67b04670b Remove '#' from if/endif, otherwise it fails on elf64 environment. 
From Christopher SEKIYA.
 2003-09-29 14:34:44 +00:00
junyoung
4c47dc9339 Fix typo in comments. 2003-09-29 04:03:55 +00:00
tsutsui
6ca112843e - Add MIPS_KSEG2_TO_PHYS() and MIPS_PHYS_TO_KSEG2() macro. 
- Add definitions of the MIPS4 config register.

From Christopher SEKIYA.
 2003-09-28 08:43:29 +00:00
tsutsui
e7500ac4b0 Add another R4000 CPU revision ID. From Christopher SEKIYA. 2003-09-28 08:16:51 +00:00