- Add MIPS_KSEG2_TO_PHYS() and MIPS_PHYS_TO_KSEG2() macro.
- Add definitions of the MIPS4 config register. From Christopher SEKIYA.
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/* $NetBSD: cpuregs.h,v 1.63 2003/09/28 08:16:51 tsutsui Exp $ */
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/* $NetBSD: cpuregs.h,v 1.64 2003/09/28 08:43:29 tsutsui Exp $ */
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/*
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* Copyright (c) 1992, 1993
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#define MIPS_PHYS_TO_KSEG0(x) ((unsigned)(x) | MIPS_KSEG0_START)
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#define MIPS_KSEG1_TO_PHYS(x) ((unsigned)(x) & MIPS_PHYS_MASK)
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#define MIPS_PHYS_TO_KSEG1(x) ((unsigned)(x) | MIPS_KSEG1_START)
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#define MIPS_KSEG2_TO_PHYS(x) ((unsigned)(x) & MIPS_PHYS_MASK)
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#define MIPS_PHYS_TO_KSEG2(x) ((unsigned)(x) | MIPS_KSEG2_START)
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/* Map virtual address to index in mips3 r4k virtually-indexed cache */
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#define MIPS3_VA_TO_CINDEX(x) \
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/* Master-Checker Mode - 1: enabled */
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#define MIPS3_CONFIG_CM 0x80000000
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/*
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* The bits in the MIPS4 config register.
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*/
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/* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */
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#define MIPS4_CONFIG_K0_MASK MIPS3_CONFIG_K0_MASK
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#define MIPS4_CONFIG_DN_MASK 0x00000018 /* Device number */
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#define MIPS4_CONFIG_CT 0x00000020 /* CohPrcReqTar */
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#define MIPS4_CONFIG_PE 0x00000040 /* PreElmReq */
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#define MIPS4_CONFIG_PM_MASK 0x00000180 /* PreReqMax */
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#define MIPS4_CONFIG_EC_MASK 0x00001e00 /* SysClkDiv */
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#define MIPS4_CONFIG_SB 0x00002000 /* SCBlkSize */
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#define MIPS4_CONFIG_SK 0x00004000 /* SCColEn */
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#define MIPS4_CONFIG_BE 0x00008000 /* MemEnd */
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#define MIPS4_CONFIG_SS_MASK 0x00070000 /* SCSize */
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#define MIPS4_CONFIG_SC_MASK 0x00380000 /* SCClkDiv */
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#define MIPS4_CONFIG_RESERVED 0x03c00000 /* Reserved wired 0 */
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#define MIPS4_CONFIG_DC_MASK 0x1c000000 /* Primary D-Cache size */
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#define MIPS4_CONFIG_IC_MASK 0xe0000000 /* Primary I-Cache size */
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#define MIPS4_CONFIG_DC_SHIFT 26
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#define MIPS4_CONFIG_IC_SHIFT 29
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#define MIPS4_CONFIG_CACHE_SIZE(config, mask, base, shift) \
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((base) << (((config) & (mask)) >> (shift)))
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#define MIPS4_CONFIG_CACHE_L2_LSIZE(config) \
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(((config) & MIPS4_CONFIG_SB) ? 128 : 64)
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/*
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* Location of exception vectors.
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*
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