chips. Add the i82541 and i82547 product IDs to the table, #if 0'd
out, for now (there are still more changes to come for these new chips
to work properly).
max memory read byte count in the command register is <= the max designed
memory read byte count in the status register. If not, reset it to the
status register's value. This is necessary because some BIOSes configure
the wrong value, and the wrong value confused some versions of the PCI-X
capable chips.
normal operation, it is required to implement a bug work-around on
some chips.
- When issuing a reset on the i82544, i82540, i82545, i82546,
and i82541, use I/O space, if available, to work around a problem
with the memory write cycle (problem only occurs when issuing
a reset).
descriptor sizes if larger mbuf clusters are in use -- currently
commented out because, for some reason, transmit doesn't work at
all with large mbuf cluster sizes.
Note that using actual 9K frames is a _lot_ less efficient than
using frames that are a little smaller than 8K so that they fit
in one or two pages (instead of two or three) and avoid the extra
chained descriptor with only 1K of data in it, too. TCP will
segment things just fine for an 8K total packet size, just as it
does for 1500-byte packets.
On my system, using "mtu 8000" with ifconfig, I get an almost 50%
performance boost for TCP (930Mbit/sec instead of 660Mbit/sec) over
1500-byte frames. "mtu 9000" yields only 770Mbit/sec.
sync that descriptor with PREREAD to make sure that it is evicted
from the data cache. From Allen Briggs.
* With the above bug fixed, stop using BUS_DMA_COHERENT, resulting in
a fairly decent performance improvement on systems where BUS_DMA_COHERENT
causes descriptors to be accessed uncached (most painful in wm_start()).
i82546 chip has 2 Gig-E interfaces in a single chip.
The main difference is these chips have a special handshaking protocol
for accessing the EEPROM (due to the shared nature on the i82546).
When initializing a TCP/IP context descriptor, even if a checksum
offload feature is not going to be used, the IPCSS and TUCSS fields
must be initialized.
* Fix outbound IPv4 header checksums (missing add of an offset).
* When enabling Rx TCP/UDP checksum offload, make sure that IPv4
header checksum Rx offload is enabled on the chip, as well.
* Bump the number of Rx descriptors from 128 to 256.
* Don't use a sliding Tx interrupt window. Instead, just do reap-behind
when we have <= 1/8 of our available descriptors in wm_start().
* Don't use Tx Queue Empty interrupts, and always set the Tx Interrupt
Delay bit in the Tx descriptor.
* In wm_intr(), always call wm_rxintr() and wm_txintr(), regardless of
their respective ISR bits being set. We're here, might as well do some
work.
* Adjust the Tx and Rx interrupt delay timer values. New values from
Intel's driver for FreeBSD via Allen Briggs.
With these changes, NetBSD can sustain > 900Mb/s userland to userland
*without* using TCP checksum offload using Intel PRO/1000 XT cards.
