(with several cosmetic changes by me) which fixes O2 (IP32) support.
Now my R5000 O2 works fine in multiuser with on-board AIC7880 SCSIs
and several PCI network cards (but only on serial console yet).
L2 cache on R5000/Rm5200 is still disabled for now, but it will be
fixed later, hopefully.
See recent discussion on port-sgimips for details.
which is automatically included during kernel config, and add comments
to individual machine-dependant majors.* files to assign new MI majors
in MI file.
Range 0-191 is reserved for machine-specific assignments, range
192+ are MI assignments.
Follows recent discussion on tech-kern@
- Use NULL where appropriate.
- No need to pull in stdint.h.
- Get rid of "register" keywords in the hope that the compiler will
do a better job for us. :-)
- Every message ends with a period.
- MMAP() macro is supposed to return MAP_FAILED rather than -1 if it
fails.
- De-__P.
* Implement read for ulpt.
* If the device is not opened for reading, occasionally drain any
data the printer might have (but don't hammer the printer with reads).
* Lower the buffer size to one page.
The driver seems to work with more printers now.
its platform code is R530A. As such, the external video patches for
the R530 work for the '780. This gives a 640x480 video out (but only
the middle 240 pixels are used, to match the lcd resolution) on the
console and in X11.
>- Move PMAGB-BA and PMAG-JA (which I have) out of "may be incorrect" entries.
>- Put driver name "tfb" for PMAG-JA (which will appear in future pmax-wscons).
1. ABLE sets the l1pt to use domain 3 for it's entries (no idea why) so to
cover all bases when setting the domain before the change to the new L1pt
become a client of all domains.
2. It seems that we setup the kernel entries without any access permission.
(note not sure that this isn't a bug) And rely on the control bits
containing either ROM or SYST enable. which allows access to pages without
access permissions set. We actually enable SYST when we do the full detect
of the CPU, but we don't detect the CPU till after the L1pt switch, which
we never make it past. Fix this by explicitly enabling the SYST bit in the
control register. rather than relying on the firmware to have dont the right
thing.
pk