/dev/power.
XXX - due to the way interrupt handling is structured we have no easy
way to defer clearing the button interrupt until the sysmon callback
has happened and the event is dispatched. We clear it imediately on
return from the interrupt handler. This means we get an interrupt storm
until the button is released, and then start to handle it.
This needs to be fixed! (But with the default application for the power
button does not make a user visible difference.)
- handle devices which has no OBP node.
- move PCI latency-timer initialization from pci_intr_map to
pci_enumerate_bus.
- make PCI bus free space extents for cardbus devices.
- fix PCI config space map size.
- some code integrations.
sysio streaming buffer flushes write a single 8-byte aligned 8-byte
value.
psycho streaming buffer flushes write a 64-byte aligned 64-byte block.
So separate out the streaming buffers into their own structure and pass those
in to all iommu operations. This also means we only flush the correct
streaming buffer for psycho rather than needing to flush both just in case.
bus_space_handle_t now holds an address and two ASIs, one for normal accesses
and one for streaming accesses. This allows to map individual handles
different ways, so some can use MMU bypass accesses and others use virtual
addresses. bus_space_map() will now create handles that use bypass accesses
unles BUS_SPACE_MAP_LINEAR is passed in. So only pass in BUS_SPACE_MAP_LINEAR
if you absolutely *need* to use bus_space_vaddr(). This removes at least one
extra level of indirection and should reduce TLB misses.
32-bit kernels have problems accessing 64-bit addresses, so they always use
virtual addresses.
interrupt number. properly find interrupts for the E250. modify
pci_intr_map() accordingly. retire psycho_intr_map(). deal with
INO values upto 0x3f, not upto 0x32. restructure sabre_init() and
psycho_init() to be more similar, and display each psycho's IGN.
psycho_intr_establish() deals with INO upto 0x3f, values from 0x32
and higher get 0 for IPL.
tested on E250 & U5.
diag regsiter to work out why the (non-existant) strbufs don't work.
- check for malloc failure in _all_ places.
- setup the PCI control register as recommended in the IIi users manual.
(`SUNW,sabre') for now, and it doesn't really quite work there yet anyway.
the bus space/dma code is cloned from the sbus driver. the IOMMU code also
is cloned from the sbus code, but separated out into iommu.c so that we can
share it with the sbus driver. hopefully, much of the bus space/dma code
can also be re-shared with the sbus driver and the ebus driver but for now
these copies will do.
support for the real UltraSPARC PCI (`SUNW,psycho') is unwritten, though
most of this code is shared with it.
we can probe PCI config space and try to configue devices, but interrupts
don't work yet...
