Commit Graph

41 Commits

Author SHA1 Message Date
thorpej 81afcb3940 And more ANSI'ification! 2000-06-08 03:10:06 +00:00
thorpej 966b3da402 ANSI'ify. 2000-06-08 02:53:47 +00:00
thorpej dbcb4cee48 Fix a typo in a previous revision, and add bit names for amask bits for
use with bitmask_snprintf().
2000-04-03 01:10:17 +00:00
thorpej 3c8d09cc56 Update the amask bits. 2000-03-20 02:19:44 +00:00
thorpej 23c5667cfe Use ANSI-style function declarations for the various inline functions
here.  Addresses port-alpha/9056.
2000-03-05 18:46:14 +00:00
thorpej 9f7d189f05 Inline most of the remaining PALcode calls. 1999-12-02 22:08:04 +00:00
thorpej 0a2ea99c42 Inline the BWX instructions. 1999-12-02 19:41:39 +00:00
thorpej 4106b60175 Move atomic operations into <machine/atomic.h>, and make them in-line
assembly, rather than function calls.

...except alpha_atomic_testset_l(), which will go away completely once
I commit the new <machine/lock.h>.
1999-12-02 01:09:11 +00:00
thorpej c258dfae2f After reading the GCC `documentation' a little more, improve the inline
__asm() statements added previously for PALcode operations.
1999-12-01 18:23:11 +00:00
thorpej 89ae0bf93c Inline several things from pal.s:
- alpha_rpcc(), alpha_mb(), alpha_wmb() -- these are instructions, and
  we win by inlining them: rpcc is generally used for profiling, and
  the memory barriers really should execute as quickly as possible with
  minimal side-effects (like additional loads/stores required to call the
  functions!)
- alpha_pal_imb(), alpha_pal_rdps(), alpha_pal_swpipl(), alpha_pal_tbi(),
  alpha_pal_whami() -- these are PALcode ops.  We must specify some register
  clobbers for these.

We have a very decent size savings as a result.  My test system:
text    data    bss     dec     hex     filename
2671724 235848  377016  3284588 321e6c  /netbsd.bak
2617708 235736  377016  3230460 314afc  /netbsd

Most of this comes from fewer register saves/restores around spl*() calls
(now that alpha_pal_rdps() and alpha_pal_swpipl() are inlined).

Note that alpha_pal_rdps() and alpha_pal_swpipl() remain in pal.s to
maintain binary compatibility with LKMs that may use spl*() functions.
1999-11-30 00:42:46 +00:00
thorpej 1710fad449 Implement atomic addition and subtraction on quadwords. 1999-11-28 19:47:13 +00:00
thorpej e2aa38459c Implement atomic quadword load-and-latch. 1998-09-25 23:59:42 +00:00
thorpej 57e656b2ec The processor unique value in the PCB is used as a backup kernel stack
pointer when booting secondary CPUs.  Add an alias for it.
1998-09-25 03:21:31 +00:00
thorpej 91a031471d Implement atomic test-and-set for longwords (32-bit). 1998-09-24 22:22:07 +00:00
thorpej 7df5ebc392 "Gee, there was already a function to do that." 1998-09-23 22:02:21 +00:00
thorpej 53d42701b5 Implement a function to recompute the HWRPB checksum. 1998-09-23 21:51:04 +00:00
thorpej 402a9210a2 Implement quadword atomic test-and-set. 1998-09-22 05:56:52 +00:00
thorpej 3eaeeb5357 Add definitions for the maximum allowable `whami' procssor ID and the
maximum number of processors we'll allow (64, assuming procssor IDs start
at 0).
1998-09-20 18:28:50 +00:00
thorpej d5df55112a vm_offset_t -> {paddr_t,vaddr_t}, vm_size_t -> vsize_t 1998-08-14 16:50:00 +00:00
mjacob 6b092524ea stale beer- place structure in right file 1998-07-08 17:20:42 +00:00
thorpej 0792d7f3db Define a shorthand macro that represents the mask of PTE bits that the
PALcode cares about.
1998-07-08 16:48:49 +00:00
thorpej 3f776dfbe2 Cosmetic change. 1998-07-08 16:46:51 +00:00
mjacob 35ffe8edb3 Add machine check type definitions. Structure the expected/received
machine check items.
1998-07-08 00:39:02 +00:00
thorpej fcfe2f1539 Implement a set of `atomic' (using load-locked and store-conditional)
operations.  Initial set includes:

alpha_atomic_setbits_q()	set bits in a quad
alpha_atomic_clearbits_q()	clear bits in a quad
1998-03-22 07:26:32 +00:00
thorpej cb6972d4d3 Implement alpha_pal_swpctx(). 1998-02-27 03:44:53 +00:00
thorpej bd60d9c62d Rewrite the way the platform model string is determined:
- Attempt to find the model string in the HWRPB's DSR area.  Failing that
  (if the HWRPB version is too old)...
- Look up the system variation in a variation/string table.  Failing that
  (unknown variation)...
- Create a default model string using the variation number.

Also, factor out a bunch of common code.
1998-02-13 00:12:45 +00:00
mjacob 03a798a3fd Add some defines for alpha interrupt types. 1997-09-20 19:02:34 +00:00
thorpej cd69e27594 Prototype alpha_implver(), and fix a think-o in a previous commit. 1997-09-17 23:33:28 +00:00
thorpej 87c1a08481 Add stubs for the Alpha Byte/Word Extension (BWX) instructions, present
on EV56 and later processors that have the "amask BWX" bit clear.  These
instructions will be used to implement non-swizzle bus access functions
on newer systems, such as the new AlphaStation 500s with EV56 and 21172
PCI chipsets.

See "Alpha Architecture Handbook, Version 3", DEC order number EC-QD2KB-TE.
1997-09-16 23:09:10 +00:00
thorpej 0599db7897 - Define bits used in the "amask" instruction.
- Define processor family IDs returned by the "implver" instruction.
- Prototype alpha_amask().
1997-09-16 06:57:12 +00:00
thorpej 6f4f08b8b2 Add a few more PALcode operations, as documented in pages (II-B) 2-1 through
(II-B) 2-33 of the Alpha AXP Architecture Reference Manual, Second Edition:

* rdps - Read Processor Status, needed by spl* functions.
* cflush - Cache Flush
* rdval - Read System Value
* wripir - Write Interprocessor Interrupt Request
* wrval - Write System Value

cflush, rdval, wripir, and wrval are used in multi-processor environments.
1997-09-03 23:09:04 +00:00
thorpej b7b3955ce0 Fix a typo: ALPHA_PTE_WRITE needs to include the "user write" bit. 1997-09-02 14:29:37 +00:00
cgd f5bfcda4fe comment out text after #endif. "Pasto!" pointed out by Kevin Sullivan
in PR 3529.
1997-04-24 23:58:24 +00:00
cgd 562fa9b97d clean up NetBSD RCS ID strings 1997-04-06 08:39:37 +00:00
cgd 12fc617201 make ALPHA_K0SEG_TO_PHYS and ~0xfffffc00000000000 with the address,
rather than and-ing 16G-1.  That just strips the k0seg bits, rather
than making the false assumption that the physical address is going
to be in the lower 16G.  That doesn't apply for CIA device-space
addresses, for instance.
1996-11-23 06:25:31 +00:00
cgd 8bc62db31e K0SEG_END is inclusive 1996-08-20 23:02:17 +00:00
cgd ce626bee48 rename translation buffer invalidation macros to start with ALPHA_,
like all other macros defined in alpha_cpu.h.
1996-07-14 20:00:15 +00:00
cgd deb9f8f4b6 (1) Remove old trap definitions, define trap and interrupt handling
more naturally in terms of way the OSF/1 PALcode delivers traps and
interrupts.  Clean up fault/exception handling code and system entry
points.  Seperate ASTs into a seperate C function.
(2)     Restructure and improve machine check and correctable error
handling based on information in the 2nd Ed. of the Alpha Architecture
Reference Manual.
(3)     Removed unused (and not likely useful) PALcode assembly stubs.
1996-07-14 04:12:46 +00:00
cgd 105697388d Instead of treating the trap/syscall/exception frame like a struct
containing a substruct (the hardware frame) and an array of registers,
treat it like one big array of registers, for easier and prettier
access.  Update everything to deal with that.
1996-07-11 05:31:16 +00:00
cgd 436a892738 Add definitions for:
Process Control Block
	Interrupt/Exception/Syscall Stack Frame
	Machine Check Error Summary Register
	Machine Check Logout Area
clean up some, and add prototypes for all of the CPU instruction and
PALcode function stubs.
1996-07-11 03:44:50 +00:00
cgd 8c87bcbe93 definitions and constants which are part of the Alpha AXP
Architecture, and which relate to the OSF/1 PALcode.
1996-07-09 00:40:58 +00:00