drisavar.h pretends to provide a few bus.h macros, hardwired to
that chip.
This should eventually be replaced by attachment code for the normal
com.c driver, once that one is split up into chip core driver and
attachment code, and once we have busxxx macros in NetBSD/Amiga.
along with toolchain enhancements.
aout2bb transforms a.out files with reloc information into bootblock format
files with a compressed relocation info.
bbstart.s relocates the bootblock using this compressed info, before jumping
to C code.
txlt changes some more of the absolute references to pc-relative ones (we know
we have a single code + data address space).
If you ever try to change this: don't even dare to change the compiler options;
they were found in weeks of trial and error as the ones producing the smallest
(not necessarily fastests) code.
installboot is just a script around dd, for now.
Some ideas by Michael Hitch, Leo Weppelman and Jason Thorpe; bugs added
by myself.
along with toolchain enhancements.
aout2bb transforms a.out files with reloc information into bootblock format
files with a compressed relocation info.
bbstart.s relocates the bootblock using this compressed info, before jumping
to C code.
txlt changes some more of the absolute references to pc-relative ones (we know
we have a single code + data address space).
If you ever try to change this: don't even dare to change the compiler options;
they were found in weeks of trial and error as the ones producing the smallest
(not necessarily fastests) code.
installboot is just a script around dd, for now.
Some ideas by Michael Hitch, Leo Weppelman and Jason Thorpe; bugs added
by myself.
Also, the munging is extended by inserting an instruction that branches
past the header, so the same boot image can be used on all supported
sun platforms.
primarily to nicely print version information about your PCI chipset
(try with "options PCIVERBOSE"). Eventually, it may be used to
enable/disable features/bugs of a given PCI chipset. In addition, this
driver uses the PCI-ISA bridge callback mechanism to logically attach the
ISA bus to the PCI-ISA bridge.
driver is a place-holder, which will nicely print version information
about your PCI chipset (try with "options PCIVERBOSE"). Eventually,
this can be used to enable/disable features/bugs of individual PCI
chipsets.
been attached to the system. If, by the time mainbus wants to attach
an ISA an ISA has not yet been attached to the system, attempt to attach
an ISA to mainbus.
>Pay attention to DMA errors as reported by DMAINTR() returning -1. If this
>happens reset everything.
>
>Re-schedule a timeout when first attempting to abort an operation.
>Cancel any queued timer events before re-scheduling a timeout, so esp_abort()
>can be called from other places besides the timeout handler.
as a "timeout", yet there's no specific delay in each iteration. Add
a small delay (10 usec... pretty arbitrary) in each iteration. This
fixes the "fdcresult: timeout" problems I've been having on my 200MHz P6.
after returning from hardclock(), rather than before. For some reason,
this fixes the 0xffffffff i used to see in the tv_secs of the used cpu
time of some processes.
XXX I don't fully understand the issue.
the chipset space init functions multiple times, since that would clobber
extent allocations made between the two calls. Also, deal with the
fact that the APECS and LCA no longer shared common chipset functions.
the same things, but the extent maps have to be managed differently,
since the two chipsets provide different memory and I/O region mapping
possibilities.
and PC-ish keyboard controller. (Actually, on alphas, the built-in PPI
(in the SIO) appears to be a lobotomized version of the original, but
i'd not call that a bad thing.) This driver should eventually handle all
speaker tone requests and keyboard commands, but for now it just maps
the relevant ports and passes them on to the keyboard and mouse drivers,
which are now its children (rather than children of ISA).
* Support for the new softint mechanism. Softints are now requested by
triggering an unused ICU hardware interrupt. The idea for this was
contributed by Phil Budne.
* Real probe code added.
* Duart info is now allocated only for devices that are present.
* Added IO-Recovery delays for 30mhz systems.
* Removed a few potential NULL-pointer references.
>One control block per target is insufficient if you have a full complement
>of targets attached and access those simultaneously (like in a ccd(4) array).
>We (now) allocate (somewhat arbitrarily) three per target.
>Noticed by Marshall Midden.
don't machine check when a PCI Master Abort is signalled. This can
happen, for instance, when configuration space for a device that isn't
present is examined. When this is detected, act like we normally would
when machine checks are posted while examining nonexistant devices.
enabled (from the attach routine), and add comments as to why.
Some PALcode apparently 'saves' a clock interrupt for the kernel,
and if the clock interrupt handler is enabled at attach time, it
will be run when that interrupt hits, i.e. right after the spl0()
at the end of autoconfiguration. That would cause hardclock to be
run, but proc0's p_stats isn't set up by then, which would cause
hardclock to crash.
rather than and-ing 16G-1. That just strips the k0seg bits, rather
than making the false assumption that the physical address is going
to be in the lower 16G. That doesn't apply for CIA device-space
addresses, for instance.
even if PCI and the IDs are right), just for sanity, before declaring
success. Split the single 0x3b0 -> 0x3df allocation into three seperate
ones: 0x3b0 -> 0x3bc (leaving the 4 ports available for lpt),
0x3c0 -> 0x3cf, and 0x3d0 -> 0x3df. The former chunk has to be split
off if the lpt can exist there, and it's sort-of pretty to have each
group (based on second hex digit) have its own handle.
These alternative macros have a workaround for the STM^ bug in revision < 3
StrongARM CPU's that causes incorrect register saving if a cache line fill
is in progress during the STM.
a podulebus.
Make sure the podulebus driver conforms to the Acorn expansion card
specification:
- Probe the podule bus using sync access cycles rather than slow access
cycles.
- Read the podulebus header/ROM using sync access cycles rather than slow
access cycles
of targets attached and access those simultaneously (like in a ccd(4) array).
We (now) allocate (somewhat arbitrarily) three per target.
Noticed by Marshall Midden.
