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228 Commits

Author SHA1 Message Date
gutteridge eac9df6f33 cpuctl.8: fix grammar in a sentence 2024-03-19 01:19:11 +00:00
rillig 88b554245c cpuctl: fix i386 bit descriptions for CPUID_SEF_FLAGS1 
warning: non-printing character '\31' in description
    'BUS_LOCK_DETECT""b\31' [363]
 2024-03-08 20:29:17 +00:00
andvar 1cd43426d5 Fix various typos in comments, log messages and documentation. 2024-02-10 18:43:51 +00:00
msaitoh 90313c06e6 Remove ryo@'s mail addresses. 2024-02-07 04:20:25 +00:00
msaitoh 4dfb580c4d Add Meteor Lake and Emerald Rapids. 2024-01-18 03:19:26 +00:00
wiz 4b9e46d064 tabify 2023-09-13 06:53:23 +00:00
wiz 61d5ba744a cpuctl(8): note that AMD updates need to be applied on all CPUs at once 
Note that checking dmesg(8) after problems might be helpful.
Sort commands.
Bump date.
 2023-09-12 20:45:17 +00:00
wiz 49d9c90b11 cpuctl: be more verbose about problems and diagnosing them 2023-09-12 20:43:38 +00:00
msaitoh e47efcfbf6 Sort by number. No functional change. 2023-07-21 10:26:36 +00:00
msaitoh 7c95744288 Add Alder Lake-N. 2023-07-06 02:43:44 +00:00
msaitoh 1f3afd7cc6 CPU model 0x5a is not Atom E3500 but Atom Z3500. 2023-07-05 02:54:37 +00:00
kre 1950105167 Unless -v is given, ignore EEXIST errors from the IOC_CPU_UCODE_APPLY ioctl() 
used to implement "cpuctl ucode N",  which indicates that the microcode
to be loaded already exists in the CPU, and as such, isn't really a
very interesting "error".
 2023-03-06 01:28:54 +00:00
msaitoh c57da92632 Add some CPUID bits from PPR for AMD Family 19h Model 61h Revision B1. 2023-02-14 15:46:06 +00:00
skrll 33f800a4a9 MPIDR is 64bits. Without this AFF3 would always be zero. 
Spotted by Cyprien.
 2023-02-03 08:08:33 +00:00
msaitoh e95c6bd4b4 Add Raptor Lake and Sapphire Rapids. 2022-12-30 13:32:46 +00:00
msaitoh 7809cc8cad Print cpuid 7 sub-leaf 1 %ebx, %edx and sub-leaf 2 %edx. 2022-12-30 12:21:07 +00:00
msaitoh ce50970520 s/features 2/features2/ 2022-11-17 15:21:31 +00:00
msaitoh 733f1aef14 s/Instruction-Based Sampling/IBS/ 2022-11-16 15:02:00 +00:00
msaitoh 0eb57810eb Add CPUID Fn8000_0022 AMD Extended Performance Monitoring and Debug. 2022-11-16 14:55:50 +00:00
msaitoh 8c5c0f4087 Add CPUID Fn8000_0021 AMD Extended Features Identification 2. 2022-11-16 14:01:41 +00:00
msaitoh f4bc0dd676 Print AMD RAS features and Instruction-Based Sampling features. 2022-11-16 13:15:26 +00:00
andvar 6478b40555 s/blity/bility/ in various words, mainly in comments. 2022-08-06 18:26:41 +00:00
msaitoh 9a8e306805 Modify output of CPUID Fn0000000a. 
old:
cpu0: Perfmon-eax 0x8300805<VERSION=0x5,GPCounter=0x8,GPBitwidth=0x30>
cpu0: Perfmon-eax 0x8300805<Vectorlen=0x8>
cpu0: Perfmon-edx 0x8604<FixedFunc=0x4,FFBitwidth=0x30,ANYTHREADDEPR>

new:
cpu0: Perfmon: Ver. 5
cpu0: Perfmon: General: bitwidth 48, 8 counters
cpu0: Perfmon: General: avail 0xff<CORECYCL,INST,REFCYCL,LLCREF,LLCMISS,BRINST>
cpu0: Perfmon: General: avail 0xff<BRMISPR,TOPDOWNSLOT>
cpu0: Perfmon: Fixed: bitwidth 48, 4 counters
cpu0: Perfmon: Fixed: avail 0xf<INST,CLK_CORETHREAD,CLK_REF_TSC,TOPDOWNSLOT>
 2022-06-15 16:28:01 +00:00
ryo 5e3407a716 add CPU_ID_APPLE_M1_ICESTORM and CPU_ID_APPLE_M1_FIRESTORM. 
sync cpuids[] to sys/arch/aarch64/aarch64/cpu.c r1.69
 2022-04-30 14:06:10 +00:00
mrg 9eba1842f2 allow "cpuN" as well as "N" to specific a CPU. 
update usage to include a change i made from 2015 to allow multiple
CPUs to be operated on at the same time for most commands.
 2022-02-01 10:45:02 +00:00
msaitoh 6f3942e76a Decode Intel Hybrid Information Enumeration (CPUID Fn0000_001a). 2022-01-29 08:20:45 +00:00
msaitoh 4e642f75a7 Remove debug code and simplify. No functional change. 2022-01-27 09:53:43 +00:00
msaitoh a80eb31137 Add Alder Lake, Rocket Lake and Sapphire Rapids. From the latest Intel SDM. 2022-01-13 16:02:44 +00:00
ryo 0d457a2cc0 display the raw value of each field when -v specified 2022-01-06 18:00:58 +00:00
ryo 1a9455cf02 fix typo 2022-01-06 17:59:15 +00:00
ryo 57817f981a Added more field definitions for ARMv8.x system registers 2022-01-06 09:01:16 +00:00
ryo bf1b93949b macroify. NFC. 2022-01-06 08:46:43 +00:00
ryo 63bdacd840 fix ID_AA64ISAR0_EL1.ATOMIC field definition 2022-01-05 19:53:32 +00:00
mrg d914a3c1b9 remove clause 3 from all my licenses that aren't conflicting with 
another copyright claim line.  again.  (i did this in 2008 and then
did not update all of my personal templates.)
 2021-12-11 19:24:18 +00:00
msaitoh 9833ff7c7e Print 1GB TLB entry at the same leve's line. 
Example:
  before:
    cpu0: ITLB: 128 4KB entries 8-way, 2M/4M: 8 entries
    cpu0: DTLB: 64 4KB entries 4-way
    cpu0: L2 STLB: 4K/2M: 1024 entries
    cpu0: L1 1GB page DTLB: 4 1GB entries 4-way

  after:
    cpu0: ITLB: 128 4KB entries 8-way, 2M/4M: 8 entries
    cpu0: DTLB: 64 4KB entries 4-way, 4 1GB entries 4-way
    cpu0: L2 STLB: 4K/2M: 1024 entries
 2021-12-09 14:23:06 +00:00
msaitoh 5e4e622281 auxilary -> auxiliary 2021-12-05 04:25:33 +00:00
mrg d626ccb00f decode SMT parts for AMD family >= 0x17, not just 0x17. 
now zen3 systems are properly identified by cpu topology for the
scheduler and cpuctl identify.
 2021-10-27 04:15:41 +00:00
msaitoh fae021bceb Move some common functions into x86/identcpu_subr.c. No functional change. 2021-10-07 13:04:18 +00:00
msaitoh a79b797b99 Improve variable sized TLB's output. 
- Fix a bug that STLB is printed as DTLB.
 - If a TLB is variable sized, print the max size instead of error message.
   XXX This is temporary solution.
 2021-09-27 17:05:58 +00:00
msaitoh 5bad7a59b6 Add Load Only TLB and Store Only TLB. 2021-09-27 16:52:15 +00:00
msaitoh ec1888b4e2 Fix a bug that some TLB related lines were not printed. 2021-09-27 16:47:15 +00:00
msaitoh bdd55414af Add ':' for readability. 2021-09-27 16:22:58 +00:00
msaitoh 1fdbc7c04d Add 0x96(Elkhart Lake) and 0x9c(Jasper Lake). 
Not listed in SDM but listed in those spec update documents.
 2021-07-12 12:56:52 +00:00
msaitoh 1f5dbb6eb2 0x6a and 0x6c are 3rd gen Xeon Scalable (Ice Lake). 2021-07-10 17:18:05 +00:00
riastradh a8fb54449d Teach cpuctl(8) about some additional aarch64 feature bits. 
(Descriptions for CSV3 and CSV2 are not very good, but the blurbs in
the arm arm are an entire paragraph long each.  Please fix if you have
a conciser summary!)
 2021-05-17 18:43:18 +00:00
jmcneill 89f30dcf4f trailing whitespace 2021-01-16 15:35:28 +00:00
jmcneill f13c261fb1 ID_AA64PFR0_EL1.GIC=0 means that the CPU interface system registers are 
not implemented. This does not necessarily mean that there is no GIC in the
system, as GICv2 uses MMIO instead of system registers for the CPU
interface.

While here, add description for GIC=3, which means that the v4.1 system
register interface is supported.
 2021-01-16 15:34:37 +00:00
ryo ea9fe086ae sync cpuids[] of sys/arch/aarch64/aarch64/cpu.c r1.43 2021-01-04 05:35:14 +00:00
msaitoh 1e34099b98 - Print CPUID 0x8000008 %ebx on Intel, too. Intel now supports WBNOINVD. 
- Print CPUID leaf 7 subleaf 1.
 2020-11-24 00:48:39 +00:00
jmcneill 29517913b7 Report half-precision FP and SIMD support 2020-10-10 08:27:41 +00:00