Aren/NetBSD
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

The maximum FIFO depth on old WD33C93 parts is only 5, not 12 as on 93A and

Browse Source 
93B. However, there appear to be issues using the maximum of 5 on old
parts, so 4 is it.
This commit is contained in:
rumble 2007-05-08 00:29:30 +00:00
parent 11dc14c9fe
commit f337484a4a
2 changed files with 14 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
sys/dev/ic/wd33c93.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: wd33c93.c,v 1.12 2007/05/08 00:20:15 rumble Exp $ */
/* $NetBSD: wd33c93.c,v 1.13 2007/05/08 00:29:30 rumble Exp $ */
/*
* Copyright (c) 1990 The Regents of the University of California.
@ -79,7 +79,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: wd33c93.c,v 1.12 2007/05/08 00:20:15 rumble Exp $");
__KERNEL_RCSID(0, "$NetBSD: wd33c93.c,v 1.13 2007/05/08 00:29:30 rumble Exp $");
#include "opt_ddb.h"
@ -207,8 +207,6 @@ wd33c93_attach(struct wd33c93_softc *dev)
callout_init(&dev->sc_watchdog);
dev->sc_maxoffset = SBIC_SYN_MAX_OFFSET; /* Max Sync Offset */
/*
* Add reference to adapter so that we drop the reference after
* config_found() to make sure the adatper is disabled.
@ -373,6 +371,13 @@ wd33c93_reset(struct wd33c93_softc *dev)
dev->sc_minsyncperiod = dev->sc_fsyncperiods[0];
}
/* Max Sync Offset */
if (dev->sc_chip == SBIC_CHIP_WD33C93A ||
dev->sc_chip == SBIC_CHIP_WD33C93B)
dev->sc_maxoffset = SBIC_SYN_93AB_MAX_OFFSET;
else
dev->sc_maxoffset = SBIC_SYN_93_MAX_OFFSET;
/*
* don't allow Selection (SBIC_RID_ES)
* until we can handle target mode!!

8
sys/dev/ic/wd33c93reg.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: wd33c93reg.h,v 1.2 2007/05/08 00:20:15 rumble Exp $ */
/* $NetBSD: wd33c93reg.h,v 1.3 2007/05/08 00:29:30 rumble Exp $ */
/*
* Copyright (c) 1990 The Regents of the University of California.
@ -199,7 +199,8 @@
* FIFO register
*/
#define SBIC_FIFO_DEEP 12
#define SBIC_FIFO_93_DEPTH 5
#define SBIC_FIFO_93AB_DEPTH 12
/*
* maximum possible size in TC registers. Since this is 24 bit, it's easy
@ -213,7 +214,8 @@
*/
#define SBIC_SYN_OFF_MASK 0x0f
#define SBIC_SYN_MAX_OFFSET SBIC_FIFO_DEEP
#define SBIC_SYN_93_MAX_OFFSET (SBIC_FIFO_93_DEPTH - 1) /* 4 is recommended */
#define SBIC_SYN_93AB_MAX_OFFSET SBIC_FIFO_93AB_DEPTH
#define SBIC_SYN_PER_MASK 0x70
#define SBIC_SYN_MIN_PERIOD 2 /* upto 8, encoded as 0 */
#define SBIC_SYN_FSS 0x80 /* Enable Fast SCSI Transfers (10MB/s)*/