Enable Fast SCSI transfers for WD33C93B parts with appropriate input
clocks. My Seagate ST32430N now sees about 50% greater throughput (about 97% as fast as IRIX can push it). However, there appear to be other performance issues with the driver as other disks perform significantly worse than they should, with or without this change. Reviewed by bjh21. Tested on my Indy and Challenge S.
This commit is contained in:
rumble
parent
10c3d35ca0
commit
11dc14c9fe
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@ -1,4 +1,4 @@
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/* $NetBSD: wd33c93.c,v 1.11 2007/03/12 18:18:30 ad Exp $ */
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/* $NetBSD: wd33c93.c,v 1.12 2007/05/08 00:20:15 rumble Exp $ */
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/*
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* Copyright (c) 1990 The Regents of the University of California.
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@ -79,7 +79,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: wd33c93.c,v 1.11 2007/03/12 18:18:30 ad Exp $");
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__KERNEL_RCSID(0, "$NetBSD: wd33c93.c,v 1.12 2007/05/08 00:20:15 rumble Exp $");
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#include "opt_ddb.h"
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@ -144,8 +144,7 @@ void wd33c93_sched_msgout (struct wd33c93_softc *, u_short);
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void wd33c93_msgout (struct wd33c93_softc *);
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void wd33c93_timeout (void *arg);
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void wd33c93_watchdog (void *arg);
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int wd33c93_div2stp (struct wd33c93_softc *, int);
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int wd33c93_stp2div (struct wd33c93_softc *, int);
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u_char wd33c93_stp2syn (struct wd33c93_softc *, struct wd33c93_tinfo *);
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void wd33c93_setsync (struct wd33c93_softc *, struct wd33c93_tinfo *);
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void wd33c93_update_xfer_mode (struct wd33c93_softc *, int);
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@ -222,11 +221,18 @@ wd33c93_attach(struct wd33c93_softc *dev)
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dev->sc_cfflags = device_cfdata(&dev->sc_dev)->cf_flags;
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wd33c93_init(dev);
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printf(": %s revision %d, %d.%d MHz, SCSI ID %d\n",
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wd33c93_chip_names[dev->sc_chip], dev->sc_rev,
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printf(": %s (%d.%d MHz clock, SCSI ID %d)\n",
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wd33c93_chip_names[dev->sc_chip],
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dev->sc_clkfreq / 10, dev->sc_clkfreq % 10,
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dev->sc_channel.chan_id);
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if (dev->sc_chip == SBIC_CHIP_WD33C93B) {
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printf("%s: microcode revision 0x%02x",
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dev->sc_dev.dv_xname, dev->sc_rev);
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if (dev->sc_minsyncperiod < 50)
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printf(", Fast SCSI");
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printf("\n");
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}
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dev->sc_child = config_found(&dev->sc_dev, &dev->sc_channel,
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scsiprint);
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@ -277,7 +283,7 @@ wd33c93_init(struct wd33c93_softc *dev)
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ti->flags |= T_NOSYNC;
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if (dev->sc_cfflags & (1<<i) || wd33c93_nodisc)
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ti->flags |= T_NODISC;
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ti->period = dev->sc_syncperiods[0];
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ti->period = dev->sc_minsyncperiod;
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ti->offset = 0;
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}
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}
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@ -297,6 +303,40 @@ wd33c93_reset(struct wd33c93_softc *dev)
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(*dev->sc_reset)(dev);
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my_id = dev->sc_channel.chan_id & SBIC_ID_MASK;
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/* Enable advanced features and really(!) advanced features */
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#if 1
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my_id |= (SBIC_ID_EAF | SBIC_ID_RAF); /* XXX - MD Layer */
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#endif
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SET_SBIC_myid(dev, my_id);
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/* Reset the chip */
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SET_SBIC_cmd(dev, SBIC_CMD_RESET);
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DELAY(25);
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SBIC_WAIT(dev, SBIC_ASR_INT, 0);
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/* Set up various chip parameters */
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SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI);
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GET_SBIC_csr(dev, csr); /* clears interrupt also */
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GET_SBIC_cdb1(dev, dev->sc_rev); /* valid with RAF on wd33c93b */
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switch (csr) {
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case SBIC_CSR_RESET:
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dev->sc_chip = SBIC_CHIP_WD33C93;
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break;
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case SBIC_CSR_RESET_AM:
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SET_SBIC_queue_tag(dev, 0x55);
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GET_SBIC_queue_tag(dev, reg);
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dev->sc_chip = (reg == 0x55) ?
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SBIC_CHIP_WD33C93B : SBIC_CHIP_WD33C93A;
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SET_SBIC_queue_tag(dev, 0x0);
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break;
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default:
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dev->sc_chip = SBIC_CHIP_UNKNOWN;
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}
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/*
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* Choose a suitable clock divisor and work out the resulting
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* sync transfer periods in 4ns units.
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@ -312,46 +352,25 @@ wd33c93_reset(struct wd33c93_softc *dev)
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div = 4;
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} else
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panic("wd33c93: invalid clock speed %d", dev->sc_clkfreq);
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for (i = 0; i < 7; i++)
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dev->sc_syncperiods[i] =
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(i + 2) * div * 1250 / dev->sc_clkfreq;
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dev->sc_minsyncperiod = dev->sc_syncperiods[0];
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SBIC_DEBUG(SYNC, ("available sync periods: %d %d %d %d %d %d %d\n",
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dev->sc_syncperiods[0], dev->sc_syncperiods[1],
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dev->sc_syncperiods[2], dev->sc_syncperiods[3],
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dev->sc_syncperiods[4], dev->sc_syncperiods[5],
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dev->sc_syncperiods[6]));
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/* Enable advanced features */
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#if 1
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my_id |= SBIC_ID_EAF; /* XXX - MD Layer */
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#endif
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SET_SBIC_myid(dev, my_id);
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/* Reset the chip */
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SET_SBIC_cmd(dev, SBIC_CMD_RESET);
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DELAY(25);
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SBIC_WAIT(dev, SBIC_ASR_INT, 0);
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/* Set up various chip parameters */
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SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI);
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GET_SBIC_csr(dev, csr); /* clears interrupt also */
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GET_SBIC_cdb1(dev, dev->sc_rev);
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switch (csr) {
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case SBIC_CSR_RESET:
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dev->sc_chip = SBIC_CHIP_WD33C93;
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break;
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case SBIC_CSR_RESET_AM:
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SET_SBIC_queue_tag(dev, 0x55);
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GET_SBIC_queue_tag(dev, reg);
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dev->sc_chip = (reg == 0x55) ?
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SBIC_CHIP_WD33C93B : SBIC_CHIP_WD33C93A;
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SET_SBIC_queue_tag(dev, 0x0);
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break;
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default:
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dev->sc_chip = SBIC_CHIP_UNKNOWN;
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if (dev->sc_clkfreq >= 160 && dev->sc_chip == SBIC_CHIP_WD33C93B) {
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for (i = 0; i < 3; i++)
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dev->sc_fsyncperiods[i] =
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(i + 2) * 2 * 1250 / dev->sc_clkfreq;
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SBIC_DEBUG(SYNC, ("available fast sync periods: %d %d %d\n",
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dev->sc_fsyncperiods[0], dev->sc_fsyncperiods[1],
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dev->sc_fsyncperiods[2]));
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dev->sc_minsyncperiod = dev->sc_fsyncperiods[0];
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}
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/*
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@ -383,25 +402,50 @@ wd33c93_error(struct wd33c93_softc *dev, struct wd33c93_acb *acb)
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printf("SCSI Error\n");
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}
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/*
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* Determine an appropriate value for the synchronous transfer register
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* given the period and offset values in *ti.
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*/
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u_char
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wd33c93_stp2syn(struct wd33c93_softc *dev, struct wd33c93_tinfo *ti)
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{
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unsigned i;
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/* see if we can handle fast scsi (100-200ns) first */
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if (ti->period < 50 && dev->sc_minsyncperiod < 50) {
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for (i = 0; i < 3; i++)
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if (dev->sc_fsyncperiods[i] >= ti->period)
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return (SBIC_SYN(ti->offset, i + 2, 1));
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}
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for (i = 0; i < 7; i++) {
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if (dev->sc_syncperiods[i] >= ti->period) {
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if (i == 6)
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return (SBIC_SYN(0, 0, 0));
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else
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return (SBIC_SYN(ti->offset, i + 2, 0));
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}
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}
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/* XXX - can't handle it; do async */
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return (SBIC_SYN(0, 0, 0));
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}
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/*
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* Setup sync mode for given target
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*/
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void
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wd33c93_setsync(struct wd33c93_softc *dev, struct wd33c93_tinfo *ti)
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{
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u_char offset, period;
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u_char syncreg;
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if (ti->flags & T_SYNCMODE) {
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offset = ti->offset;
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period = wd33c93_stp2div(dev, ti->period);
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} else {
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offset = 0;
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period = 0;
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}
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if (ti->flags & T_SYNCMODE)
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syncreg = wd33c93_stp2syn(dev, ti);
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else
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syncreg = SBIC_SYN(0, 0, 0);
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SBIC_DEBUG(SYNC, ("wd33c93_setsync: sync reg = 0x%02x\n",
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SBIC_SYN(offset, period)));
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SET_SBIC_syn(dev, SBIC_SYN(offset, period));
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SBIC_DEBUG(SYNC, ("wd33c93_setsync: sync reg = 0x%02x\n", syncreg));
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SET_SBIC_syn(dev, syncreg);
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}
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/*
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@ -1039,7 +1083,7 @@ wd33c93_selectbus(struct wd33c93_softc *dev, struct wd33c93_acb *acb)
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/* Inititae a SDTR message */
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SBIC_DEBUG(SYNC, ("Sending SDTR to target %d\n", id));
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if (ti->flags & T_WANTSYNC) {
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ti->period = dev->sc_syncperiods[0];
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ti->period = dev->sc_minsyncperiod;
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ti->offset = dev->sc_maxoffset;
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} else {
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ti->period = 0;
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@ -1051,7 +1095,7 @@ wd33c93_selectbus(struct wd33c93_softc *dev, struct wd33c93_acb *acb)
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dev->sc_omsg[2] = MSG_EXT_SDTR_LEN;
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dev->sc_omsg[3] = MSG_EXT_SDTR;
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if (ti->flags & T_WANTSYNC) {
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dev->sc_omsg[4] = dev->sc_syncperiods[0];
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dev->sc_omsg[4] = dev->sc_minsyncperiod;
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dev->sc_omsg[5] = dev->sc_maxoffset;
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} else {
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dev->sc_omsg[4] = 0;
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@ -1611,7 +1655,7 @@ void wd33c93_msgin(struct wd33c93_softc *dev, u_char *msgaddr, int msglen)
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goto reject;
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ti->period =
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MAX(msgaddr[3], dev->sc_syncperiods[0]);
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MAX(msgaddr[3], dev->sc_minsyncperiod);
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ti->offset = MIN(msgaddr[4], dev->sc_maxoffset);
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if (!(ti->flags & T_WANTSYNC))
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ti->period = ti->offset = 0;
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@ -2208,39 +2252,6 @@ wd33c93_update_xfer_mode(struct wd33c93_softc *sc, int target)
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scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm);
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}
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/*
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* Calculate SCSI Tranfser Period Factor (4ns units each) from the
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* WD33c93 divisor value
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*
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* cycle = DIV / (2 * CLK)
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* DIV = FS + 2
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* best we can do is 200ns at 20 MHz, 2 cycles
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*/
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int
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wd33c93_div2stp(struct wd33c93_softc *dev, int div)
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{
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if (div < 2)
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div = 8; /* map to Cycles */
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return dev->sc_syncperiods[div - 2];
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}
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/*
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* Convert SCSI Transfer Period Factor (in 4ns units) to the divisor
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* value used by the WD33c93 controller.
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*/
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int
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wd33c93_stp2div(struct wd33c93_softc *dev, int stp)
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{
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unsigned i;
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for (i = 0; i < 7; i++)
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if (dev->sc_syncperiods[i] >= stp)
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return (i == 6 ? 0 : i + 2);
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return 0; /* XXX we can't slow down far enough */
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}
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void
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wd33c93_timeout(void *arg)
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{
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@ -1,4 +1,4 @@
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/* $NetBSD: wd33c93reg.h,v 1.1 2006/08/26 22:06:37 bjh21 Exp $ */
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/* $NetBSD: wd33c93reg.h,v 1.2 2007/05/08 00:20:15 rumble Exp $ */
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/*
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* Copyright (c) 1990 The Regents of the University of California.
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@ -145,7 +145,7 @@
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/* 11 MHz is invalid */
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#define SBIC_ID_FS_12_15 0x40 /* Input clock is 12-15 MHz */
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#define SBIC_ID_FS_16_20 0x80 /* Input clock is 16-20 MHz */
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#define SBIC_ID_RAF 0x20 /* */
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#define SBIC_ID_RAF 0x20 /* Enable Really Advanced Features */
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#define SBIC_ID_EHP 0x10 /* Enable host parity */
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#define SBIC_ID_EAF 0x08 /* Enable Advanced Features */
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#define SBIC_ID_MASK 0x07
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@ -208,15 +208,19 @@
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/*
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* Synchronous xfer register
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*
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* NB: SBIC_SYN_FSS only valid on WD33C93B with 16-20MHz clock.
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*/
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#define SBIC_SYN_OFF_MASK 0x0f
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#define SBIC_SYN_MAX_OFFSET SBIC_FIFO_DEEP
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#define SBIC_SYN_PER_MASK 0x70
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#define SBIC_SYN_MIN_PERIOD 2 /* upto 8, encoded as 0 */
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#define SBIC_SYN_FSS 0x80 /* Enable Fast SCSI Transfers (10MB/s)*/
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#define SBIC_SYN(o,p) \
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(((o) & SBIC_SYN_OFF_MASK) | (((p) << 4) & SBIC_SYN_PER_MASK))
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#define SBIC_SYN(o,p,f) \
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(((o) & SBIC_SYN_OFF_MASK) | (((p) << 4) & SBIC_SYN_PER_MASK) | \
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((f) ? SBIC_SYN_FSS : 0))
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/*
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* Transfer count register
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@ -1,4 +1,4 @@
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/* $NetBSD: wd33c93var.h,v 1.5 2007/03/04 06:02:03 christos Exp $ */
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/* $NetBSD: wd33c93var.h,v 1.6 2007/05/08 00:20:15 rumble Exp $ */
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/*
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* Copyright (c) 1990 The Regents of the University of California.
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@ -171,8 +171,10 @@ struct wd33c93_softc {
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int sc_rev; /* Chip revision */
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int sc_cfflags; /* Copy of config flags */
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int sc_maxxfer; /* Maximum transfer size */
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uint8_t sc_maxoffset; /* Maximum sync ofset (bytes) */
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uint8_t sc_maxoffset; /* Maximum sync offset (bytes) */
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uint8_t sc_minsyncperiod; /* Minimum supported sync xfer period */
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uint8_t sc_syncperiods[7]; /* Sync transfer periods (4ns units) */
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uint8_t sc_fsyncperiods[3]; /* Sync transfer periods for Fast SCSI*/
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int (*sc_dmasetup) (struct wd33c93_softc *, void **,
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size_t *, int, size_t *);
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