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This commit is contained in:
skrll 2017-03-30 08:43:40 +00:00
parent a0123401b6
commit e7e2876573
1 changed files with 6 additions and 5 deletions
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11
sys/arch/mips/cavium/octeon_intr.c
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@ -1,4 +1,4 @@
/* $NetBSD: octeon_intr.c,v 1.9 2016/11/28 04:18:08 mrg Exp $ */ /* $NetBSD: octeon_intr.c,v 1.10 2017/03/30 08:43:40 skrll Exp $ */
/* /*
* Copyright 2001, 2002 Wasabi Systems, Inc. * Copyright 2001, 2002 Wasabi Systems, Inc.
* All rights reserved. * All rights reserved.
@ -45,7 +45,7 @@
#define __INTR_PRIVATE #define __INTR_PRIVATE
#include <sys/cdefs.h> #include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: octeon_intr.c,v 1.9 2016/11/28 04:18:08 mrg Exp $"); __KERNEL_RCSID(0, "$NetBSD: octeon_intr.c,v 1.10 2017/03/30 08:43:40 skrll Exp $");
#include <sys/param.h> #include <sys/param.h>
#include <sys/cpu.h> #include <sys/cpu.h>
@ -333,9 +333,10 @@ octeon_intr_init(struct cpu_info *ci)
#endif #endif
if (ci->ci_dev) if (ci->ci_dev)
aprint_verbose_dev(ci->ci_dev, aprint_verbose_dev(ci->ci_dev,
"enabling intr masks %#"PRIx64"/%#"PRIx64"/%#"PRIx64"\n", "enabling intr masks %#"PRIx64"/%#"PRIx64"/%#"PRIx64"\n",
cpu->cpu_int0_enable0, cpu->cpu_int1_enable0, cpu->cpu_int2_enable0); cpu->cpu_int0_enable0, cpu->cpu_int1_enable0,
cpu->cpu_int2_enable0);
mips3_sd(cpu->cpu_int0_en0, cpu->cpu_int0_enable0); mips3_sd(cpu->cpu_int0_en0, cpu->cpu_int0_enable0);
mips3_sd(cpu->cpu_int1_en0, cpu->cpu_int1_enable0); mips3_sd(cpu->cpu_int1_en0, cpu->cpu_int1_enable0);