Support external DMA mode and provide an interface for DMA address configuration
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parent
38c1b17ca1
commit
e427b2e5a6
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@ -1,4 +1,4 @@
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/* $NetBSD: dwc2_core.c,v 1.6 2014/04/03 06:34:58 skrll Exp $ */
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/* $NetBSD: dwc2_core.c,v 1.7 2015/05/01 06:58:40 hikaru Exp $ */
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/*
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* core.c - DesignWare HS OTG Controller common routines
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@ -43,7 +43,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: dwc2_core.c,v 1.6 2014/04/03 06:34:58 skrll Exp $");
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__KERNEL_RCSID(0, "$NetBSD: dwc2_core.c,v 1.7 2015/05/01 06:58:40 hikaru Exp $");
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#include <sys/types.h>
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#include <sys/bus.h>
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@ -312,8 +312,13 @@ static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
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switch (hsotg->hw_params.arch) {
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case GHWCFG2_EXT_DMA_ARCH:
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dev_err(hsotg->dev, "External DMA Mode not supported\n");
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return -EINVAL;
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dev_dbg(hsotg->dev, "External DMA Mode\n");
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if (hsotg->core_params->ahbcfg != -1) {
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ahbcfg &= GAHBCFG_CTRL_MASK;
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ahbcfg |= hsotg->core_params->ahbcfg &
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~GAHBCFG_CTRL_MASK;
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}
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break;
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case GHWCFG2_INT_DMA_ARCH:
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dev_dbg(hsotg->dev, "Internal DMA Mode\n");
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@ -1396,10 +1401,18 @@ void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
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} else {
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dma_addr = chan->xfer_dma;
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}
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DWC2_WRITE_4(hsotg, HCDMA(chan->hc_num), (u32)dma_addr);
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if (hsotg->hsotg_sc->sc_set_dma_addr == NULL) {
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DWC2_WRITE_4(hsotg, HCDMA(chan->hc_num),
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(u32)dma_addr);
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if (dbg_hc(chan))
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dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n",
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(unsigned long)dma_addr, chan->hc_num);
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dev_vdbg(hsotg->dev,
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"Wrote %08lx to HCDMA(%d)\n",
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(unsigned long)dma_addr,
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chan->hc_num);
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} else {
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(void)(*hsotg->hsotg_sc->sc_set_dma_addr)(
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hsotg->dev, dma_addr, chan->hc_num);
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}
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}
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/* Start the split */
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@ -1,4 +1,4 @@
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/* $NetBSD: dwc2var.h,v 1.3 2013/10/22 12:57:40 skrll Exp $ */
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/* $NetBSD: dwc2var.h,v 1.4 2015/05/01 06:58:40 hikaru Exp $ */
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/*-
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* Copyright (c) 2013 The NetBSD Foundation, Inc.
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@ -77,6 +77,7 @@ typedef struct dwc2_softc {
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bus_space_handle_t sc_ioh;
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bus_dma_tag_t sc_dmat;
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struct dwc2_core_params *sc_params;
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int (*sc_set_dma_addr)(device_t, bus_addr_t, int);
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/*
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* Private
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