Nuke homegrown PCI configuration routines. #ifdef'd out by tsutsui@ a long
time ago; this is just garbage collection.
This commit is contained in:
sekiya
parent
1eb315b681
commit
e2a64ba528
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@ -1,4 +1,4 @@
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/* $NetBSD: pci_mace.c,v 1.8 2006/08/30 23:35:10 rumble Exp $ */
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/* $NetBSD: pci_mace.c,v 1.9 2007/04/17 12:41:57 sekiya Exp $ */
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/*
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* Copyright (c) 2001,2003 Christopher Sekiya
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@ -34,7 +34,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pci_mace.c,v 1.8 2006/08/30 23:35:10 rumble Exp $");
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__KERNEL_RCSID(0, "$NetBSD: pci_mace.c,v 1.9 2007/04/17 12:41:57 sekiya Exp $");
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#include "opt_pci.h"
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#include "pci.h"
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@ -56,32 +56,14 @@ __KERNEL_RCSID(0, "$NetBSD: pci_mace.c,v 1.8 2006/08/30 23:35:10 rumble Exp $");
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcidevs.h>
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#ifdef PCI_NETBSD_CONFIGURE
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#include <sys/extent.h>
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#include <sys/malloc.h>
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#include <dev/pci/pciconf.h>
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#endif
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#include <sgimips/mace/macereg.h>
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#include <sgimips/mace/macevar.h>
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#include <sgimips/mace/pcireg_mace.h>
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#ifndef PCI_NETBSD_CONFIGURE
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#include <sgimips/pci/pci_addr_fixup.h>
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#define PCIBIOS_PRINTV(arg) \
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do { \
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printf arg; \
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} while (0)
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#define PCIBIOS_PRINTVN(n, arg) \
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do { \
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printf arg; \
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} while (0)
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#define PAGE_ALIGN(x) (((x) + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1))
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#define MEG_ALIGN(x) (((x) + 0x100000 - 1) & ~(0x100000 - 1))
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#endif
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struct macepci_softc {
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struct device sc_dev;
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@ -99,15 +81,6 @@ static const char *
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macepci_intr_string(pci_chipset_tag_t, pci_intr_handle_t);
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static int macepci_intr(void *);
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#ifndef PCI_NETBSD_CONFIGURE
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struct pciaddr pciaddr;
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int pciaddr_do_resource_allocate(pci_chipset_tag_t pc, pcitag_t tag, int mapreg, void *ctx, int type, bus_addr_t *addr, bus_size_t size);
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unsigned int ioaddr_base = 0x1000;
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unsigned int memaddr_base = 0x80100000;
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#endif
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CFATTACH_DECL(macepci, sizeof(struct macepci_softc),
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macepci_match, macepci_attach, NULL, NULL);
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@ -127,10 +100,6 @@ macepci_attach(struct device *parent, struct device *self, void *aux)
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struct pcibus_attach_args pba;
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u_int32_t control;
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int rev;
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#ifndef PCI_NETBSD_CONFIGURE
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pcitag_t devtag;
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int device;
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#endif
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if (bus_space_subregion(maa->maa_st, maa->maa_sh,
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maa->maa_offset, 0, &pc->ioh) )
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@ -166,49 +135,6 @@ macepci_attach(struct device *parent, struct device *self, void *aux)
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MACE_PCI_CONTROL_TAR_INT |
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MACE_PCI_CONTROL_MAR_INT);
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#ifndef PCI_NETBSD_CONFIGURE
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/* Must fix up all PCI devices, ahc_pci expects proper i/o mapping */
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for (device = 1; device < 4; device++) {
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const struct pci_quirkdata *qd;
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int function, nfuncs;
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pcireg_t bhlcr, id;
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devtag = pci_make_tag(pc, 0, device, 0);
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id = pci_conf_read(pc, devtag, PCI_ID_REG);
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/* Invalid vendor ID value? */
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if (PCI_VENDOR(id) == PCI_VENDOR_INVALID)
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continue;
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/* XXX Not invalid, but we've done this ~forever. */
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if (PCI_VENDOR(id) == 0)
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continue;
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qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id));
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bhlcr = pci_conf_read(pc, devtag, PCI_BHLC_REG);
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if (PCI_HDRTYPE_MULTIFN(bhlcr) ||
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(qd != NULL &&
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(qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0))
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nfuncs = 8;
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else
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nfuncs = 1;
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for (function = 0; function < nfuncs; function++) {
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devtag = pci_make_tag(pc, 0, device, function);
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id = pci_conf_read(pc, devtag, PCI_ID_REG);
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/* Invalid vendor ID value? */
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if (PCI_VENDOR(id) == PCI_VENDOR_INVALID)
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continue;
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/* Not invalid, but we've done this ~forever */
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if (PCI_VENDOR(id) == 0)
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continue;
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pciaddr_resource_manage(pc, devtag, NULL, NULL);
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}
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}
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#endif
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/*
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* Enable all MACE PCI interrupts. They will be masked by
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* the CRIME code.
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@ -218,14 +144,12 @@ macepci_attach(struct device *parent, struct device *self, void *aux)
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bus_space_write_4(pc->iot, pc->ioh, MACEPCI_CONTROL, control);
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#if NPCI > 0
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#ifdef PCI_NETBSD_CONFIGURE
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pc->pc_ioext = extent_create("macepciio", 0x00001000, 0x01ffffff,
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M_DEVBUF, NULL, 0, EX_NOWAIT);
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pc->pc_memext = extent_create("macepcimem", 0x80100000, 0x81ffffff,
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M_DEVBUF, NULL, 0, EX_NOWAIT);
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pci_configure_bus(pc, pc->pc_ioext, pc->pc_memext, NULL, 0,
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mips_dcache_align);
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#endif
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memset(&pba, 0, sizeof pba);
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/*XXX*/ pba.pba_iot = SGIMIPS_BUS_SPACE_IO;
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/*XXX*/ pba.pba_memt = SGIMIPS_BUS_SPACE_MEM;
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@ -424,204 +348,3 @@ macepci_intr(void *arg)
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}
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return 0;
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}
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#ifndef PCI_NETBSD_CONFIGURE
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/* PCI Address fixup routines */
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void
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pciaddr_resource_manage(pci_chipset_tag_t pc, pcitag_t tag,
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pciaddr_resource_manage_func_t func, void *ctx)
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{
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pcireg_t val, mask;
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bus_addr_t addr;
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bus_size_t size;
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int error, mapreg, type, reg_start, reg_end, width;
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val = macepci_conf_read(pc, tag, PCI_BHLC_REG);
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switch (PCI_HDRTYPE_TYPE(val)) {
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default:
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printf("WARNING: unknown PCI device header.");
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pciaddr.nbogus++;
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return;
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case 0:
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reg_start = PCI_MAPREG_START;
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reg_end = PCI_MAPREG_END;
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break;
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case 1: /* PCI-PCI bridge */
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reg_start = PCI_MAPREG_START;
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reg_end = PCI_MAPREG_PPB_END;
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break;
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case 2: /* PCI-CardBus bridge */
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reg_start = PCI_MAPREG_START;
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reg_end = PCI_MAPREG_PCB_END;
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break;
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}
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error = 0;
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for (mapreg = reg_start; mapreg < reg_end; mapreg += width) {
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/* inquire PCI device bus space requirement */
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val = macepci_conf_read(pc, tag, mapreg);
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macepci_conf_write(pc, tag, mapreg, ~0);
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mask = macepci_conf_read(pc, tag, mapreg);
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macepci_conf_write(pc, tag, mapreg, val);
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type = PCI_MAPREG_TYPE(val);
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width = 4;
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if (type == PCI_MAPREG_TYPE_MEM) {
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size = PCI_MAPREG_MEM_SIZE(mask);
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/*
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* XXXrkb: for MEM64 BARs, to be totally kosher
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* about the requested size, need to read mask
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* from top 32bits of BAR and stir that into the
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* size calculation, like so:
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*
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* case PCI_MAPREG_MEM_TYPE_64BIT:
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* bar64 = pci_conf_read(pb->pc, tag, br + 4);
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* pci_conf_write(pb->pc, tag, br + 4, 0xffffffff);
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* mask64 = pci_conf_read(pb->pc, tag, br + 4);
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* pci_conf_write(pb->pc, tag, br + 4, bar64);
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* size = (u_int64_t) PCI_MAPREG_MEM64_SIZE(
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* (((u_int64_t) mask64) << 32) | mask);
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* width = 8;
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*
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* Fortunately, anything with all-zeros mask in the
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* lower 32-bits will have size no less than 1 << 32,
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* which we're not prepared to deal with, so I don't
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* feel bad punting on it...
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*/
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if (PCI_MAPREG_MEM_TYPE(val) ==
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PCI_MAPREG_MEM_TYPE_64BIT) {
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/*
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* XXX We could examine the upper 32 bits
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* XXX of the BAR here, but we are totally
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* XXX unprepared to handle a non-zero value,
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* XXX either here or anywhere else in the
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* XXX sgimips code (not sure about MI code).
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* XXX
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* XXX So just arrange to skip the top 32
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* XXX bits of the BAR and zero then out
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* XXX if the BAR is in use.
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*/
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width = 8;
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if (size != 0)
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macepci_conf_write(pc, tag,
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mapreg + 4, 0);
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}
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} else {
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/*
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* Upper 16 bits must be one. Devices may hardwire
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* them to zero, though, per PCI 2.2, 6.2.5.1, p 203.
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*/
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mask |= 0xffff0000;
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size = PCI_MAPREG_IO_SIZE(mask);
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}
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if (size == 0) /* unused register */
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continue;
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addr = pciaddr_ioaddr(val);
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/* reservation/allocation phase */
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error += pciaddr_do_resource_allocate(pc, tag, mapreg,
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ctx, type, &addr, size);
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#if 0
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PCIBIOS_PRINTV(("\n\t%02xh %s 0x%08x 0x%08x",
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mapreg, type ? "port" : "mem ",
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(unsigned int)addr, (unsigned int)size));
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#endif
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}
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/* enable/disable PCI device */
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val = macepci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
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if (error == 0)
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val |= (PCI_COMMAND_IO_ENABLE |
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PCI_COMMAND_MEM_ENABLE |
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PCI_COMMAND_MASTER_ENABLE |
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PCI_COMMAND_SPECIAL_ENABLE |
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PCI_COMMAND_INVALIDATE_ENABLE |
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PCI_COMMAND_PARITY_ENABLE);
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else
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val &= ~(PCI_COMMAND_IO_ENABLE |
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PCI_COMMAND_MEM_ENABLE |
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PCI_COMMAND_MASTER_ENABLE);
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macepci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, val);
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if (error)
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pciaddr.nbogus++;
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}
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bus_addr_t
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pciaddr_ioaddr(u_int32_t val)
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{
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return ((PCI_MAPREG_TYPE(val) == PCI_MAPREG_TYPE_MEM) ?
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PCI_MAPREG_MEM_ADDR(val) : PCI_MAPREG_IO_ADDR(val));
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}
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int
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pciaddr_do_resource_allocate(pci_chipset_tag_t pc, pcitag_t tag, int mapreg,
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void *ctx, int type, bus_addr_t *addr, bus_size_t size)
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{
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switch (type) {
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case PCI_MAPREG_TYPE_IO:
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*addr = ioaddr_base;
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ioaddr_base += PAGE_ALIGN(size);
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break;
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case PCI_MAPREG_TYPE_MEM:
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*addr = memaddr_base;
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memaddr_base += MEG_ALIGN(size);
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break;
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default:
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PCIBIOS_PRINTV(("attempt to remap unknown region (addr 0x%lx, "
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"size 0x%lx, type %d)\n", *addr, size, type));
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return 0;
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}
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/* write new address to PCI device configuration header */
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macepci_conf_write(pc, tag, mapreg, *addr);
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/* check */
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#ifdef PCIBIOSVERBOSE
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if (!pcibiosverbose)
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#endif
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{
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printf("pci_addr_fixup: ");
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pciaddr_print_devid(pc, tag);
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}
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if (pciaddr_ioaddr(macepci_conf_read(pc, tag, mapreg)) != *addr) {
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macepci_conf_write(pc, tag, mapreg, 0); /* clear */
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printf("fixup failed. (new address=%#x)\n", (unsigned)*addr);
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return (1);
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}
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#ifdef PCIBIOSVERBOSE
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if (!pcibiosverbose)
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#endif
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printf("new address 0x%08x (size 0x%x)\n", (unsigned)*addr,
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(unsigned)size);
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return (0);
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}
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void
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pciaddr_print_devid(pci_chipset_tag_t pc, pcitag_t tag)
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{
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int bus, device, function;
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pcireg_t id;
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id = macepci_conf_read(pc, tag, PCI_ID_REG);
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pci_decompose_tag(pc, tag, &bus, &device, &function);
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printf("%03d:%02d:%d 0x%04x 0x%04x ", bus, device, function,
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PCI_VENDOR(id), PCI_PRODUCT(id));
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}
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#endif
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