From e2a64ba528ad8e427c5ee1f18ca7863901801eb8 Mon Sep 17 00:00:00 2001 From: sekiya Date: Tue, 17 Apr 2007 12:41:57 +0000 Subject: [PATCH] Nuke homegrown PCI configuration routines. #ifdef'd out by tsutsui@ a long time ago; this is just garbage collection. --- sys/arch/sgimips/mace/pci_mace.c | 281 +------------------------------ 1 file changed, 2 insertions(+), 279 deletions(-) diff --git a/sys/arch/sgimips/mace/pci_mace.c b/sys/arch/sgimips/mace/pci_mace.c index 469825325fb7..077da85a77c4 100644 --- a/sys/arch/sgimips/mace/pci_mace.c +++ b/sys/arch/sgimips/mace/pci_mace.c @@ -1,4 +1,4 @@ -/* $NetBSD: pci_mace.c,v 1.8 2006/08/30 23:35:10 rumble Exp $ */ +/* $NetBSD: pci_mace.c,v 1.9 2007/04/17 12:41:57 sekiya Exp $ */ /* * Copyright (c) 2001,2003 Christopher Sekiya @@ -34,7 +34,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: pci_mace.c,v 1.8 2006/08/30 23:35:10 rumble Exp $"); +__KERNEL_RCSID(0, "$NetBSD: pci_mace.c,v 1.9 2007/04/17 12:41:57 sekiya Exp $"); #include "opt_pci.h" #include "pci.h" @@ -56,32 +56,14 @@ __KERNEL_RCSID(0, "$NetBSD: pci_mace.c,v 1.8 2006/08/30 23:35:10 rumble Exp $"); #include #include -#ifdef PCI_NETBSD_CONFIGURE #include #include #include -#endif #include #include #include -#ifndef PCI_NETBSD_CONFIGURE -#include - -#define PCIBIOS_PRINTV(arg) \ - do { \ - printf arg; \ - } while (0) -#define PCIBIOS_PRINTVN(n, arg) \ - do { \ - printf arg; \ - } while (0) - - -#define PAGE_ALIGN(x) (((x) + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1)) -#define MEG_ALIGN(x) (((x) + 0x100000 - 1) & ~(0x100000 - 1)) -#endif struct macepci_softc { struct device sc_dev; @@ -99,15 +81,6 @@ static const char * macepci_intr_string(pci_chipset_tag_t, pci_intr_handle_t); static int macepci_intr(void *); -#ifndef PCI_NETBSD_CONFIGURE -struct pciaddr pciaddr; - -int pciaddr_do_resource_allocate(pci_chipset_tag_t pc, pcitag_t tag, int mapreg, void *ctx, int type, bus_addr_t *addr, bus_size_t size); - -unsigned int ioaddr_base = 0x1000; -unsigned int memaddr_base = 0x80100000; -#endif - CFATTACH_DECL(macepci, sizeof(struct macepci_softc), macepci_match, macepci_attach, NULL, NULL); @@ -127,10 +100,6 @@ macepci_attach(struct device *parent, struct device *self, void *aux) struct pcibus_attach_args pba; u_int32_t control; int rev; -#ifndef PCI_NETBSD_CONFIGURE - pcitag_t devtag; - int device; -#endif if (bus_space_subregion(maa->maa_st, maa->maa_sh, maa->maa_offset, 0, &pc->ioh) ) @@ -166,49 +135,6 @@ macepci_attach(struct device *parent, struct device *self, void *aux) MACE_PCI_CONTROL_TAR_INT | MACE_PCI_CONTROL_MAR_INT); -#ifndef PCI_NETBSD_CONFIGURE - /* Must fix up all PCI devices, ahc_pci expects proper i/o mapping */ - for (device = 1; device < 4; device++) { - const struct pci_quirkdata *qd; - int function, nfuncs; - pcireg_t bhlcr, id; - - devtag = pci_make_tag(pc, 0, device, 0); - id = pci_conf_read(pc, devtag, PCI_ID_REG); - - /* Invalid vendor ID value? */ - if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) - continue; - /* XXX Not invalid, but we've done this ~forever. */ - if (PCI_VENDOR(id) == 0) - continue; - - qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id)); - bhlcr = pci_conf_read(pc, devtag, PCI_BHLC_REG); - - if (PCI_HDRTYPE_MULTIFN(bhlcr) || - (qd != NULL && - (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0)) - nfuncs = 8; - else - nfuncs = 1; - - for (function = 0; function < nfuncs; function++) { - devtag = pci_make_tag(pc, 0, device, function); - id = pci_conf_read(pc, devtag, PCI_ID_REG); - - /* Invalid vendor ID value? */ - if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) - continue; - /* Not invalid, but we've done this ~forever */ - if (PCI_VENDOR(id) == 0) - continue; - - pciaddr_resource_manage(pc, devtag, NULL, NULL); - } - } -#endif - /* * Enable all MACE PCI interrupts. They will be masked by * the CRIME code. @@ -218,14 +144,12 @@ macepci_attach(struct device *parent, struct device *self, void *aux) bus_space_write_4(pc->iot, pc->ioh, MACEPCI_CONTROL, control); #if NPCI > 0 -#ifdef PCI_NETBSD_CONFIGURE pc->pc_ioext = extent_create("macepciio", 0x00001000, 0x01ffffff, M_DEVBUF, NULL, 0, EX_NOWAIT); pc->pc_memext = extent_create("macepcimem", 0x80100000, 0x81ffffff, M_DEVBUF, NULL, 0, EX_NOWAIT); pci_configure_bus(pc, pc->pc_ioext, pc->pc_memext, NULL, 0, mips_dcache_align); -#endif memset(&pba, 0, sizeof pba); /*XXX*/ pba.pba_iot = SGIMIPS_BUS_SPACE_IO; /*XXX*/ pba.pba_memt = SGIMIPS_BUS_SPACE_MEM; @@ -424,204 +348,3 @@ macepci_intr(void *arg) } return 0; } - -#ifndef PCI_NETBSD_CONFIGURE -/* PCI Address fixup routines */ - -void -pciaddr_resource_manage(pci_chipset_tag_t pc, pcitag_t tag, - pciaddr_resource_manage_func_t func, void *ctx) -{ - pcireg_t val, mask; - bus_addr_t addr; - bus_size_t size; - int error, mapreg, type, reg_start, reg_end, width; - - val = macepci_conf_read(pc, tag, PCI_BHLC_REG); - switch (PCI_HDRTYPE_TYPE(val)) { - default: - printf("WARNING: unknown PCI device header."); - pciaddr.nbogus++; - return; - case 0: - reg_start = PCI_MAPREG_START; - reg_end = PCI_MAPREG_END; - break; - case 1: /* PCI-PCI bridge */ - reg_start = PCI_MAPREG_START; - reg_end = PCI_MAPREG_PPB_END; - break; - case 2: /* PCI-CardBus bridge */ - reg_start = PCI_MAPREG_START; - reg_end = PCI_MAPREG_PCB_END; - break; - } - error = 0; - - for (mapreg = reg_start; mapreg < reg_end; mapreg += width) { - /* inquire PCI device bus space requirement */ - val = macepci_conf_read(pc, tag, mapreg); - macepci_conf_write(pc, tag, mapreg, ~0); - - mask = macepci_conf_read(pc, tag, mapreg); - macepci_conf_write(pc, tag, mapreg, val); - - type = PCI_MAPREG_TYPE(val); - width = 4; - - if (type == PCI_MAPREG_TYPE_MEM) { - size = PCI_MAPREG_MEM_SIZE(mask); - - /* - * XXXrkb: for MEM64 BARs, to be totally kosher - * about the requested size, need to read mask - * from top 32bits of BAR and stir that into the - * size calculation, like so: - * - * case PCI_MAPREG_MEM_TYPE_64BIT: - * bar64 = pci_conf_read(pb->pc, tag, br + 4); - * pci_conf_write(pb->pc, tag, br + 4, 0xffffffff); - * mask64 = pci_conf_read(pb->pc, tag, br + 4); - * pci_conf_write(pb->pc, tag, br + 4, bar64); - * size = (u_int64_t) PCI_MAPREG_MEM64_SIZE( - * (((u_int64_t) mask64) << 32) | mask); - * width = 8; - * - * Fortunately, anything with all-zeros mask in the - * lower 32-bits will have size no less than 1 << 32, - * which we're not prepared to deal with, so I don't - * feel bad punting on it... - */ - if (PCI_MAPREG_MEM_TYPE(val) == - PCI_MAPREG_MEM_TYPE_64BIT) { - /* - * XXX We could examine the upper 32 bits - * XXX of the BAR here, but we are totally - * XXX unprepared to handle a non-zero value, - * XXX either here or anywhere else in the - * XXX sgimips code (not sure about MI code). - * XXX - * XXX So just arrange to skip the top 32 - * XXX bits of the BAR and zero then out - * XXX if the BAR is in use. - */ - width = 8; - - if (size != 0) - macepci_conf_write(pc, tag, - mapreg + 4, 0); - } - } else { - /* - * Upper 16 bits must be one. Devices may hardwire - * them to zero, though, per PCI 2.2, 6.2.5.1, p 203. - */ - mask |= 0xffff0000; - size = PCI_MAPREG_IO_SIZE(mask); - } - - if (size == 0) /* unused register */ - continue; - - addr = pciaddr_ioaddr(val); - - /* reservation/allocation phase */ - error += pciaddr_do_resource_allocate(pc, tag, mapreg, - ctx, type, &addr, size); - -#if 0 - PCIBIOS_PRINTV(("\n\t%02xh %s 0x%08x 0x%08x", - mapreg, type ? "port" : "mem ", - (unsigned int)addr, (unsigned int)size)); -#endif - } - - /* enable/disable PCI device */ - val = macepci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); - - if (error == 0) - val |= (PCI_COMMAND_IO_ENABLE | - PCI_COMMAND_MEM_ENABLE | - PCI_COMMAND_MASTER_ENABLE | - PCI_COMMAND_SPECIAL_ENABLE | - PCI_COMMAND_INVALIDATE_ENABLE | - PCI_COMMAND_PARITY_ENABLE); - else - val &= ~(PCI_COMMAND_IO_ENABLE | - PCI_COMMAND_MEM_ENABLE | - PCI_COMMAND_MASTER_ENABLE); - - macepci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, val); - - if (error) - pciaddr.nbogus++; -} - -bus_addr_t -pciaddr_ioaddr(u_int32_t val) -{ - - return ((PCI_MAPREG_TYPE(val) == PCI_MAPREG_TYPE_MEM) ? - PCI_MAPREG_MEM_ADDR(val) : PCI_MAPREG_IO_ADDR(val)); -} - -int -pciaddr_do_resource_allocate(pci_chipset_tag_t pc, pcitag_t tag, int mapreg, - void *ctx, int type, bus_addr_t *addr, bus_size_t size) -{ - - switch (type) { - case PCI_MAPREG_TYPE_IO: - *addr = ioaddr_base; - ioaddr_base += PAGE_ALIGN(size); - break; - - case PCI_MAPREG_TYPE_MEM: - *addr = memaddr_base; - memaddr_base += MEG_ALIGN(size); - break; - - default: - PCIBIOS_PRINTV(("attempt to remap unknown region (addr 0x%lx, " - "size 0x%lx, type %d)\n", *addr, size, type)); - return 0; - } - - - /* write new address to PCI device configuration header */ - macepci_conf_write(pc, tag, mapreg, *addr); - - /* check */ -#ifdef PCIBIOSVERBOSE - if (!pcibiosverbose) -#endif - { - printf("pci_addr_fixup: "); - pciaddr_print_devid(pc, tag); - } - if (pciaddr_ioaddr(macepci_conf_read(pc, tag, mapreg)) != *addr) { - macepci_conf_write(pc, tag, mapreg, 0); /* clear */ - printf("fixup failed. (new address=%#x)\n", (unsigned)*addr); - return (1); - } -#ifdef PCIBIOSVERBOSE - if (!pcibiosverbose) -#endif - printf("new address 0x%08x (size 0x%x)\n", (unsigned)*addr, - (unsigned)size); - - return (0); -} - -void -pciaddr_print_devid(pci_chipset_tag_t pc, pcitag_t tag) -{ - int bus, device, function; - pcireg_t id; - - id = macepci_conf_read(pc, tag, PCI_ID_REG); - pci_decompose_tag(pc, tag, &bus, &device, &function); - printf("%03d:%02d:%d 0x%04x 0x%04x ", bus, device, function, - PCI_VENDOR(id), PCI_PRODUCT(id)); -} -#endif