Machinery to configure multiple CPUs. All CPUs found are spun up from the
auto-configuration cpu_attach() function using the firmware. Currently, all CPUs except the one used to boot end up in an idle loop in locore.
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pk
parent
1b077ae1cd
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e120fa4e14
@ -1,4 +1,4 @@
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/* $NetBSD: cpu.c,v 1.65 1998/09/07 23:02:40 pk Exp $ */
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/* $NetBSD: cpu.c,v 1.66 1998/09/12 15:33:40 pk Exp $ */
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/*
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* Copyright (c) 1996
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@ -54,6 +54,7 @@
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/malloc.h>
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#include <vm/vm.h>
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#include <vm/vm_kern.h>
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@ -90,6 +91,7 @@ struct cpu_softc {
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char machine[] = MACHINE; /* from <machine/param.h> */
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char machine_arch[] = MACHINE_ARCH; /* from <machine/param.h> */
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char cpu_model[100];
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int ncpu;
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struct proc *fpproc;
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@ -103,7 +105,7 @@ struct cfattach cpu_ca = {
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static char *fsrtoname __P((int, int, int, char *));
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void cache_print __P((struct cpu_softc *));
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void cpu_spinup __P((struct cpu_info *));
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void cpu_spinup __P((struct cpu_softc *));
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void fpu_init __P((struct cpu_info *));
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#define IU_IMPL(psr) ((u_int)(psr) >> 28)
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@ -130,9 +132,9 @@ alloc_cpuinfo()
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* Allocate aligned KVA.
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*/
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align = NBPG;
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if (cpuinfo.cacheinfo.c_totalsize > align)
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if (CACHEINFO.c_totalsize > align)
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/* Assumes `c_totalsize' is power of two */
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align = cpuinfo.cacheinfo.c_totalsize;
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align = CACHEINFO.c_totalsize;
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sz = (sizeof(struct cpu_info) + NBPG - 1) & -NBPG;
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esz = sz + align - NBPG;
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@ -238,6 +240,8 @@ static struct cpu_softc *bootcpu;
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char *fpuname;
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char fpbuf[40];
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ncpu++; /* Another one */
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node = ma->ma_node;
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/*
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@ -249,24 +253,26 @@ static struct cpu_softc *bootcpu;
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cip = sc->sc_cpuinfo = (struct cpu_info *)CPUINFO_VA;
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cip->master = 1;
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} else {
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cip = alloc_cpuinfo();
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cip = sc->sc_cpuinfo = alloc_cpuinfo();
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}
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if (mid != 0)
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printf(": mid %d", mid);
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cip->mid = mid;
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cip->node = node;
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getcpuinfo(cip, node);
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fpuname = "no";
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if (cip->master) {
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if (cip->hotfix)
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cip->hotfix(cip);
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fpu_init(cip);
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if (cip->fpupresent)
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fpuname = fsrtoname(cip->cpu_impl, cip->cpu_vers,
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cip->fpuvers, fpbuf);
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fpuname = (cip->fpupresent)
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? fsrtoname(cip->cpu_impl, cip->cpu_vers,
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cip->fpuvers, fpbuf)
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: "no";
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sprintf(cpu_model, "%s @ %s MHz, %s FPU",
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cip->cpu_name,
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@ -282,31 +288,102 @@ static struct cpu_softc *bootcpu;
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}
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/* Now start this CPU */
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cpu_spinup(sc);
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#ifdef DEBUG
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printf("***\n");
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if (ncpu >= 4)
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callrom();
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#endif
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}
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#if 0
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void cpu_setup __P((struct cpu_softc *));
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/* */
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void *cpu_hatchstack = 0;
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void *cpu_hatch_sc = 0;
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volatile int cpu_hatched = 0;
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void
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cpu_hatch(sc)
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cpu_setup(sc)
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struct cpu_softc *sc;
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{
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if (sc->hotfix)
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sc->hotfix(sc);
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struct cpu_info *cip = sc->sc_cpuinfo;
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char *fpuname;
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char fpbuf[40];
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#ifdef DEBUG
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printf("[cpu_setup: cip @ %p; mid %d] ", cip, cip->mid);
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#endif
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if (cip->hotfix)
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cip->hotfix(cip);
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/* Initialize FPU */
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fpu_init(sc);
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fpu_init(cip);
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fpuname = (cip->fpupresent)
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? fsrtoname(cip->cpu_impl, cip->cpu_vers, cip->fpuvers, fpbuf)
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: "no";
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printf("%s @ %s MHz, %s FPU\n", cip->cpu_name,
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clockfreq(cip->hz), fpuname);
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if (cip->cacheinfo.c_totalsize != 0)
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cache_print(sc);
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/* Enable the cache */
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sc->cache_enable();
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cip->cache_enable();
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cpu_hatched = 1;
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/* Flush cache line */
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cpuinfo.cache_flush((caddr_t)&cpu_hatched, sizeof(cpu_hatched));
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}
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#endif
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#include <machine/bsd_openprom.h> /*XXX*/
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extern struct promvec *promvec; /*XXX-make library functions */
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void
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cpu_spinup(sc)
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struct cpu_info *sc;
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struct cpu_softc *sc;
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{
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#if 0
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pmap_cpusetup();
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struct cpu_info *cip = sc->sc_cpuinfo;
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int n;
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extern void cpu_hatch __P((void));
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caddr_t pc = (caddr_t)cpu_hatch;
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struct rom_reg rr;
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/* Setup CPU-specific MMU tables */
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pmap_alloc_cpu(cip);
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cpu_hatched = 0;
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cpu_hatchstack = malloc(USPACE,M_TEMP, M_NOWAIT);
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cpu_hatch_sc = sc;
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/*
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* The physical address of the context table is passed to
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* the PROM in a "physical address descriptor".
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*/
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rr.rr_iospace = 0;
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rr.rr_paddr = (u_int32_t)cip->ctx_tbl_pa;
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rr.rr_len = cip->mmu_ncontext * sizeof(cip->ctx_tbl[0]); /*???*/
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/*
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* Flush entire cache here, since the CPU may start with
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* caches off, hence no cache-coherency may be assumed.
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*/
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/*XXX*/cpuinfo.cache_flush((caddr_t)KERNBASE, 0xff000000U - KERNBASE);
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(*promvec->pv_v3cpustart)(cip->node, (u_int)&rr, 0, pc);
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/*
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* Wait for this CPU to spin up.
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*/
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for (n = 10000; n != 0; n--) {
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cpuinfo.cache_flush((caddr_t)&cpu_hatched, sizeof(cpu_hatched));
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if (cpu_hatched != 0) {
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#ifdef DEBUG
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printf("[CPU hatched]\n");
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#endif
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break;
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}
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delay(100);
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}
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}
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/*
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@ -917,7 +994,7 @@ viking_mmu_enable()
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/* ROSS Hypersparc */
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struct module_info module_hypersparc = { /* UNTESTED */
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CPUTYP_UNKNOWN,
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VAC_NONE,
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VAC_WRITETHROUGH, /* should be:VAC_NONE/VAC_WRITEBACK*/
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cpumatch_hypersparc,
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getcacheinfo_obp,
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0,
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