Fix iocorrect defines.
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uch
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7dd8599060
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dd4be4cdba
@ -1,4 +1,4 @@
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/* $NetBSD: plumicu.c,v 1.1 1999/11/21 06:50:26 uch Exp $ */
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/* $NetBSD: plumicu.c,v 1.2 1999/12/07 17:53:04 uch Exp $ */
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/*
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* Copyright (c) 1999, by UCHIYAMA Yasushi
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@ -58,13 +58,10 @@ int plumicu_intr __P((void*));
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struct plum_intr_ctrl {
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plumreg_t ic_ackpat1;
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plumreg_t ic_ackpat2;
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int ic_ackreg2;
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plumreg_t ic_ienpat;
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int ic_ienreg;
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plumreg_t ic_senpat;
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int ic_senreg;
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} pi_ctrl[] = {
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plumreg_t ic_ackpat2; int ic_ackreg2;
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plumreg_t ic_ienpat; int ic_ienreg;
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plumreg_t ic_senpat; int ic_senreg;
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} pi_ctrl[PLUM_INTR_MAX] = {
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[PLUM_INT_C1IO] = {PLUM_INT_INTSTA_PCCINT,
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PLUM_INT_PCCINTS_C1IO, PLUM_INT_PCCINTS_REG,
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PLUM_INT_PCCIEN_IENC1IO, PLUM_INT_PCCIEN_REG,
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@ -260,21 +257,25 @@ plum_intr_establish(pc, line, mode, level, ih_fun, ih_arg)
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TAILQ_INSERT_TAIL(&sc->sc_pi_head[line], pi, pi_link);
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/* Enable interrupt */
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if (pi->pi_ctrl->ic_ienreg) {
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reg = plum_conf_read(regt, regh, pi->pi_ctrl->ic_ienreg);
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reg |= pi->pi_ctrl->ic_ienpat;
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plum_conf_write(regt, regh, pi->pi_ctrl->ic_ienreg, reg);
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}
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/* status enable */
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if (pi->pi_ctrl->ic_senreg) {
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reg = plum_conf_read(regt, regh, pi->pi_ctrl->ic_senreg);
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reg |= pi->pi_ctrl->ic_senpat;
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plum_conf_write(regt, regh, pi->pi_ctrl->ic_senreg, reg);
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}
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/* interrupt enable */
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if (pi->pi_ctrl->ic_ienreg) {
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reg = plum_conf_read(regt, regh, pi->pi_ctrl->ic_ienreg);
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reg |= pi->pi_ctrl->ic_ienpat;
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plum_conf_write(regt, regh, pi->pi_ctrl->ic_ienreg, reg);
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}
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/* Enable redirect to TX39 core */
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DPRINTF(("plum_intr_establish: %d (count=%d)\n", line, sc->sc_enable_count));
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sc->sc_enable_count++;
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plum_conf_write(regt, regh, PLUM_INT_INTIEN_REG, 1);
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if (!sc->sc_enable_count++) {
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plum_conf_write(regt, regh, PLUM_INT_INTIEN_REG, PLUM_INT_INTIEN);
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}
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return ih_fun;
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}
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@ -298,7 +299,6 @@ plum_intr_disestablish(pc, arg)
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TAILQ_REMOVE(&sc->sc_pi_head[i], pi, pi_link);
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DPRINTF(("plum_intr_disestablish: %d (count=%d)\n",
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pi->pi_line, sc->sc_enable_count - 1));
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free(pi, M_DEVBUF);
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goto found;
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}
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}
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@ -316,10 +316,11 @@ plum_intr_disestablish(pc, arg)
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reg &= ~(pi->pi_ctrl->ic_senpat);
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plum_conf_write(regt, regh, pi->pi_ctrl->ic_senreg, reg);
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}
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free(pi, M_DEVBUF);
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/* Disable redirect to TX39 core */
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if (--sc->sc_enable_count == 0) {
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/* Disable redirect to TX39 core to avoid lost interrupt */
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/* Disable redirect to TX39 core */
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plum_conf_write(regt, regh, PLUM_INT_INTIEN_REG, 0);
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}
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}
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@ -336,19 +337,21 @@ plumicu_intr(arg)
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int i;
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reg1 = plum_conf_read(regt, regh, PLUM_INT_INTSTA_REG);
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for (i = 0; i < PLUM_INTR_MAX; i++) {
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struct plum_intr_ctrl *pic = &pi_ctrl[i];
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if (pic->ic_ackpat1 & reg1) {
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if (pic->ic_ackpat2) {
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reg2 = plum_conf_read(regt, regh,
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pic->ic_ackreg2);
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TAILQ_FOREACH(pi, &sc->sc_pi_head[i],
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pi_link) {
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if (pi->pi_ctrl->ic_ackpat2 & reg2) {
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plum_conf_write(
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regt, regh,
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pic->ic_ackreg2,
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pi->pi_ctrl->ic_ackpat2);
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if (pic->ic_ackpat2 & reg2) {
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plum_conf_write(
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regt, regh,
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pic->ic_ackreg2,
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pic->ic_ackpat2);
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TAILQ_FOREACH(pi,
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&sc->sc_pi_head[i],
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pi_link) {
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(*pi->pi_fun)(pi->pi_arg);
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}
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: plumicureg.h,v 1.1 1999/11/21 06:50:26 uch Exp $ */
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/* $NetBSD: plumicureg.h,v 1.2 1999/12/07 17:53:04 uch Exp $ */
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/*
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* Copyright (c) 1999, by UCHIYAMA Yasushi
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@ -27,12 +27,14 @@
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*/
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/*
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* INTERRUPT CONTROLLER
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* PLUM2 INTERRUPT CONTROLLER UNIT
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*/
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#define PLUM_INT_REGBASE 0x8000
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#define PLUM_INT_REGSIZE 0x1000
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/* interrupt status register */
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/*
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* Interrupt status register
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*/
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#define PLUM_INT_INTSTA_REG 0x000
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#define PLUM_INT_INTSTA_EXTINT 0x00000080
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#define PLUM_INT_INTSTA_SMINT 0x00000040
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@ -43,38 +45,51 @@
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#define PLUM_INT_INTSTA_C1SCINT 0x00000002
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#define PLUM_INT_INTSTA_PCCINT 0x00000001
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/* interrupt enable register */
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/*
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* Interrupt enable register
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*/
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#define PLUM_INT_INTIEN_REG 0x010
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#define PLUM_INT_INTIEN 0x00000001
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/*
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* External interrupts
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*/
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/* outside input interrupt status register */
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#define PLUM_INT_EXTINTS_REG 0x100
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#define PLUM_INT_EXTINTS_IO5INT0 0x00000020
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#define PLUM_INT_EXTINTS_IO5INT1 0x00000010
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#define PLUM_INT_EXTINTS_IO5INT2 0x00000008
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#define PLUM_INT_EXTINTS_IO5INT3 0x00000004
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#define PLUM_INT_EXTINTS_IO3INT0 0x00000002
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#define PLUM_INT_EXTINTS_IO3INT1 0x00000001
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#define PLUM_INT_EXTINTS_IO3INT1 0x00000020
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#define PLUM_INT_EXTINTS_IO3INT0 0x00000010
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#define PLUM_INT_EXTINTS_IO5INT3 0x00000008
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#define PLUM_INT_EXTINTS_IO5INT2 0x00000004
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#define PLUM_INT_EXTINTS_IO5INT1 0x00000002
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#define PLUM_INT_EXTINTS_IO5INT0 0x00000001
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/* outside input interrupt status register (after the mask) */
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#define PLUM_INT_EXTINTM_REG 0x104
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/* interrupt enable register from the outside input */
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#define PLUM_INT_EXTIEN_REG 0x110
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#define PLUM_INT_EXTIEN_IENIO5INT0 0x00000020
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#define PLUM_INT_EXTIEN_IENIO5INT1 0x00000010
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#define PLUM_INT_EXTIEN_IENIO5INT2 0x00000008
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#define PLUM_INT_EXTIEN_IENIO5INT3 0x00000004
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#define PLUM_INT_EXTIEN_IENIO3INT0 0x00000002
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#define PLUM_INT_EXTIEN_IENIO3INT1 0x00000001
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#define PLUM_INT_EXTIEN_SENIO5INT0 0x00002000
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#define PLUM_INT_EXTIEN_SENIO5INT1 0x00001000
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#define PLUM_INT_EXTIEN_SENIO5INT2 0x00000800
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#define PLUM_INT_EXTIEN_SENIO5INT3 0x00000400
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#define PLUM_INT_EXTIEN_SENIO3INT0 0x00000200
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#define PLUM_INT_EXTIEN_SENIO3INT1 0x00000100
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#define PLUM_INT_EXTIEN_IENIO3INT1 0x00000020
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#define PLUM_INT_EXTIEN_IENIO3INT0 0x00000010
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#define PLUM_INT_EXTIEN_IENIO5INT3 0x00000008
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#define PLUM_INT_EXTIEN_IENIO5INT2 0x00000004
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#define PLUM_INT_EXTIEN_IENIO5INT1 0x00000002
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#define PLUM_INT_EXTIEN_IENIO5INT0 0x00000001
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#define PLUM_INT_EXTIEN_SENIO3INT1 0x00002000
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#define PLUM_INT_EXTIEN_SENIO3INT0 0x00001000
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#define PLUM_INT_EXTIEN_SENIO5INT3 0x00000800
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#define PLUM_INT_EXTIEN_SENIO5INT2 0x00000400
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#define PLUM_INT_EXTIEN_SENIO5INT1 0x00000200
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#define PLUM_INT_EXTIEN_SENIO5INT0 0x00000100
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/*
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* PC-card interrupts
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*/
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/* PC-card interrupt status register */
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#define PLUM_INT_PCCINTS_REG 0x200
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#define PLUM_INT_PCCINTS_C2RI 0x00000008
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#define PLUM_INT_PCCINTS_C2IO 0x00000004
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#define PLUM_INT_PCCINTS_C1RI 0x00000002
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@ -85,25 +100,33 @@
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/* PC-card interrupt enable register */
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#define PLUM_INT_PCCIEN_REG 0x210
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#define PLUM_INT_PCCIEN_IENC2RI 0x00000008
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#define PLUM_INT_PCCIEN_IENC2IO 0x00000004
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#define PLUM_INT_PCCIEN_IENC1RI 0x00000002
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#define PLUM_INT_PCCIEN_IENC1IO 0x00000001
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#define PLUM_INT_PCCIEN_SENC2RI 0x00000800
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#define PLUM_INT_PCCIEN_SENC2IO 0x00000400
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#define PLUM_INT_PCCIEN_SENC1RI 0x00000200
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#define PLUM_INT_PCCIEN_SENC1IO 0x00000100
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#define PLUM_INT_PCCIEN_IENC2RI 0x00000008
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#define PLUM_INT_PCCIEN_IENC2IO 0x00000004
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#define PLUM_INT_PCCIEN_IENC1RI 0x00000002
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#define PLUM_INT_PCCIEN_IENC1IO 0x00000001
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/* PC-card interrupt detection register */
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#define PLUM_INT_PCCLKSL_REG 0x220
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#define PLUM_INT_PCCLKSL_RTC 0x00000001 /*(for suspend mode)*/
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/*
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* USB interrupts
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*/
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/* USB interrupt enable register */
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#define PLUM_INT_USBINTEN_REG 0x310
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#define PLUM_INT_USBINTEN_WIEN 0x00000002
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#define PLUM_INT_USBINTEN_IEN 0x00000001
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/* master-enables the USB interrupts */
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#define PLUM_INT_USBINTEN_IEN 0x00000002
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/* enbales the clock restart request interrupts */
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#define PLUM_INT_USBINTEN_WIEN 0x00000001
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/*
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* SmartMedia interrupts
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*/
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/* SmartMedia interrupt enable register */
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#define PLUM_INT_SMIEN_REG 0x410
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