diff --git a/sys/arch/hpcmips/dev/plumicu.c b/sys/arch/hpcmips/dev/plumicu.c
index e3d8697da40e..d581c816e0a7 100644
--- a/sys/arch/hpcmips/dev/plumicu.c
+++ b/sys/arch/hpcmips/dev/plumicu.c
@@ -1,4 +1,4 @@
-/*	$NetBSD: plumicu.c,v 1.1 1999/11/21 06:50:26 uch Exp $ */
+/*	$NetBSD: plumicu.c,v 1.2 1999/12/07 17:53:04 uch Exp $ */
 
 /*
  * Copyright (c) 1999, by UCHIYAMA Yasushi
@@ -58,13 +58,10 @@ int	plumicu_intr __P((void*));
 
 struct plum_intr_ctrl {
 	plumreg_t	ic_ackpat1;
-	plumreg_t	ic_ackpat2;
-	int		ic_ackreg2;
-	plumreg_t	ic_ienpat;
-	int		ic_ienreg;
-	plumreg_t	ic_senpat;
-	int		ic_senreg;
-} pi_ctrl[] = {
+	plumreg_t	ic_ackpat2;	int	ic_ackreg2;
+	plumreg_t	ic_ienpat;	int	ic_ienreg;
+	plumreg_t	ic_senpat;	int	ic_senreg;
+} pi_ctrl[PLUM_INTR_MAX] = {
 	[PLUM_INT_C1IO]	= {PLUM_INT_INTSTA_PCCINT,	
 			   PLUM_INT_PCCINTS_C1IO,	PLUM_INT_PCCINTS_REG,
 			   PLUM_INT_PCCIEN_IENC1IO,	PLUM_INT_PCCIEN_REG,		
@@ -260,21 +257,25 @@ plum_intr_establish(pc, line, mode, level, ih_fun, ih_arg)
 	TAILQ_INSERT_TAIL(&sc->sc_pi_head[line], pi, pi_link);
 	
 	/* Enable interrupt */
-	if (pi->pi_ctrl->ic_ienreg) {
-		reg = plum_conf_read(regt, regh, pi->pi_ctrl->ic_ienreg);
-		reg |= pi->pi_ctrl->ic_ienpat;
-		plum_conf_write(regt, regh, pi->pi_ctrl->ic_ienreg, reg);
-	}
+	/* status enable */
 	if (pi->pi_ctrl->ic_senreg) {
 		reg = plum_conf_read(regt, regh, pi->pi_ctrl->ic_senreg);
 		reg |= pi->pi_ctrl->ic_senpat;
 		plum_conf_write(regt, regh, pi->pi_ctrl->ic_senreg, reg);
 	}
+	/* interrupt enable */
+	if (pi->pi_ctrl->ic_ienreg) {
+		reg = plum_conf_read(regt, regh, pi->pi_ctrl->ic_ienreg);
+		reg |= pi->pi_ctrl->ic_ienpat;
+		plum_conf_write(regt, regh, pi->pi_ctrl->ic_ienreg, reg);
+	}
 
 	/* Enable redirect to TX39 core */
 	DPRINTF(("plum_intr_establish: %d (count=%d)\n", line, sc->sc_enable_count));
-	sc->sc_enable_count++;
-	plum_conf_write(regt, regh, PLUM_INT_INTIEN_REG, 1);
+
+	if (!sc->sc_enable_count++) {
+		plum_conf_write(regt, regh, PLUM_INT_INTIEN_REG, PLUM_INT_INTIEN);
+	}
 
 	return ih_fun;
 }
@@ -298,7 +299,6 @@ plum_intr_disestablish(pc, arg)
 				TAILQ_REMOVE(&sc->sc_pi_head[i], pi, pi_link);
 				DPRINTF(("plum_intr_disestablish: %d (count=%d)\n",  
 					 pi->pi_line, sc->sc_enable_count - 1));
-				free(pi, M_DEVBUF);
 				goto found;
 			}
 		}
@@ -316,10 +316,11 @@ plum_intr_disestablish(pc, arg)
 		reg &= ~(pi->pi_ctrl->ic_senpat);
 		plum_conf_write(regt, regh, pi->pi_ctrl->ic_senreg, reg);
 	}
+	free(pi, M_DEVBUF);
 	
 	/* Disable redirect to TX39 core */
 	if (--sc->sc_enable_count == 0) {
-		/* Disable redirect to TX39 core to avoid lost interrupt */
+		/* Disable redirect to TX39 core */
 		plum_conf_write(regt, regh, PLUM_INT_INTIEN_REG, 0);
 	}
 }
@@ -336,19 +337,21 @@ plumicu_intr(arg)
 	int i;
 	
 	reg1 = plum_conf_read(regt, regh, PLUM_INT_INTSTA_REG);
+
 	for (i = 0; i < PLUM_INTR_MAX; i++) {
 		struct plum_intr_ctrl *pic = &pi_ctrl[i];
 		if (pic->ic_ackpat1 & reg1) {
 			if (pic->ic_ackpat2) {
 				reg2 = plum_conf_read(regt, regh, 
 						      pic->ic_ackreg2);
-				TAILQ_FOREACH(pi, &sc->sc_pi_head[i], 
-					      pi_link) {
-					if (pi->pi_ctrl->ic_ackpat2 & reg2) {
-						plum_conf_write(
-							regt, regh, 
-							pic->ic_ackreg2, 
-							pi->pi_ctrl->ic_ackpat2);
+				if (pic->ic_ackpat2 & reg2) {
+					plum_conf_write(
+						regt, regh,
+						pic->ic_ackreg2,
+						pic->ic_ackpat2);
+					TAILQ_FOREACH(pi, 
+						      &sc->sc_pi_head[i], 
+						      pi_link) {
 						(*pi->pi_fun)(pi->pi_arg);
 					}
 				} 
diff --git a/sys/arch/hpcmips/dev/plumicureg.h b/sys/arch/hpcmips/dev/plumicureg.h
index e209e03c7c5a..93799cd435ae 100644
--- a/sys/arch/hpcmips/dev/plumicureg.h
+++ b/sys/arch/hpcmips/dev/plumicureg.h
@@ -1,4 +1,4 @@
-/*	$NetBSD: plumicureg.h,v 1.1 1999/11/21 06:50:26 uch Exp $ */
+/*	$NetBSD: plumicureg.h,v 1.2 1999/12/07 17:53:04 uch Exp $ */
 
 /*
  * Copyright (c) 1999, by UCHIYAMA Yasushi
@@ -27,12 +27,14 @@
  */
 
 /*
- * INTERRUPT CONTROLLER
+ * PLUM2 INTERRUPT CONTROLLER UNIT
  */
 #define	PLUM_INT_REGBASE		0x8000
 #define	PLUM_INT_REGSIZE		0x1000
 
-/* interrupt status register */
+/* 
+ *  Interrupt status register 
+ */
 #define	PLUM_INT_INTSTA_REG		0x000
 #define PLUM_INT_INTSTA_EXTINT		0x00000080
 #define PLUM_INT_INTSTA_SMINT		0x00000040
@@ -43,38 +45,51 @@
 #define PLUM_INT_INTSTA_C1SCINT		0x00000002
 #define PLUM_INT_INTSTA_PCCINT		0x00000001
 
-/* interrupt enable register */
+/* 
+ *  Interrupt enable register 
+ */
 #define	PLUM_INT_INTIEN_REG		0x010
 #define PLUM_INT_INTIEN			0x00000001
 
+/*
+ *  External interrupts 
+ */
 /* outside input interrupt status register */
 #define	PLUM_INT_EXTINTS_REG		0x100
-#define	PLUM_INT_EXTINTS_IO5INT0	0x00000020
-#define	PLUM_INT_EXTINTS_IO5INT1	0x00000010
-#define	PLUM_INT_EXTINTS_IO5INT2	0x00000008
-#define	PLUM_INT_EXTINTS_IO5INT3	0x00000004
-#define	PLUM_INT_EXTINTS_IO3INT0	0x00000002
-#define	PLUM_INT_EXTINTS_IO3INT1	0x00000001
 
+#define	PLUM_INT_EXTINTS_IO3INT1	0x00000020
+#define	PLUM_INT_EXTINTS_IO3INT0	0x00000010
+#define	PLUM_INT_EXTINTS_IO5INT3	0x00000008
+#define	PLUM_INT_EXTINTS_IO5INT2	0x00000004
+#define	PLUM_INT_EXTINTS_IO5INT1	0x00000002
+#define	PLUM_INT_EXTINTS_IO5INT0	0x00000001
+
+/* outside input interrupt status register (after the mask) */
 #define	PLUM_INT_EXTINTM_REG		0x104
+
+/* interrupt enable register from the outside input */
 #define	PLUM_INT_EXTIEN_REG		0x110
 
-#define	PLUM_INT_EXTIEN_IENIO5INT0	0x00000020
-#define	PLUM_INT_EXTIEN_IENIO5INT1	0x00000010
-#define	PLUM_INT_EXTIEN_IENIO5INT2	0x00000008
-#define	PLUM_INT_EXTIEN_IENIO5INT3	0x00000004
-#define	PLUM_INT_EXTIEN_IENIO3INT0	0x00000002
-#define	PLUM_INT_EXTIEN_IENIO3INT1	0x00000001
-#define	PLUM_INT_EXTIEN_SENIO5INT0	0x00002000
-#define	PLUM_INT_EXTIEN_SENIO5INT1	0x00001000
-#define	PLUM_INT_EXTIEN_SENIO5INT2	0x00000800
-#define	PLUM_INT_EXTIEN_SENIO5INT3	0x00000400
-#define	PLUM_INT_EXTIEN_SENIO3INT0	0x00000200
-#define	PLUM_INT_EXTIEN_SENIO3INT1	0x00000100
+#define	PLUM_INT_EXTIEN_IENIO3INT1	0x00000020
+#define	PLUM_INT_EXTIEN_IENIO3INT0	0x00000010
+#define	PLUM_INT_EXTIEN_IENIO5INT3	0x00000008
+#define	PLUM_INT_EXTIEN_IENIO5INT2	0x00000004
+#define	PLUM_INT_EXTIEN_IENIO5INT1	0x00000002
+#define	PLUM_INT_EXTIEN_IENIO5INT0	0x00000001
 
+#define	PLUM_INT_EXTIEN_SENIO3INT1	0x00002000
+#define	PLUM_INT_EXTIEN_SENIO3INT0	0x00001000
+#define	PLUM_INT_EXTIEN_SENIO5INT3	0x00000800
+#define	PLUM_INT_EXTIEN_SENIO5INT2	0x00000400
+#define	PLUM_INT_EXTIEN_SENIO5INT1	0x00000200
+#define	PLUM_INT_EXTIEN_SENIO5INT0	0x00000100
 
+/*
+ *  PC-card interrupts
+ */
 /* PC-card interrupt status register */
 #define	PLUM_INT_PCCINTS_REG		0x200
+
 #define PLUM_INT_PCCINTS_C2RI		0x00000008
 #define PLUM_INT_PCCINTS_C2IO		0x00000004
 #define PLUM_INT_PCCINTS_C1RI		0x00000002
@@ -85,25 +100,33 @@
 /* PC-card interrupt enable register */
 #define	PLUM_INT_PCCIEN_REG		0x210
 
-#define PLUM_INT_PCCIEN_IENC2RI		0x00000008
-#define PLUM_INT_PCCIEN_IENC2IO		0x00000004
-#define PLUM_INT_PCCIEN_IENC1RI		0x00000002
-#define PLUM_INT_PCCIEN_IENC1IO		0x00000001
 #define PLUM_INT_PCCIEN_SENC2RI		0x00000800
 #define PLUM_INT_PCCIEN_SENC2IO		0x00000400
 #define PLUM_INT_PCCIEN_SENC1RI		0x00000200
 #define PLUM_INT_PCCIEN_SENC1IO		0x00000100
+#define PLUM_INT_PCCIEN_IENC2RI		0x00000008
+#define PLUM_INT_PCCIEN_IENC2IO		0x00000004
+#define PLUM_INT_PCCIEN_IENC1RI		0x00000002
+#define PLUM_INT_PCCIEN_IENC1IO		0x00000001
 
 /* PC-card interrupt detection register */
 #define	PLUM_INT_PCCLKSL_REG		0x220
 #define	PLUM_INT_PCCLKSL_RTC		0x00000001 /*(for suspend mode)*/
 
+/*
+ *  USB interrupts
+ */
 /* USB interrupt enable register */
 #define	PLUM_INT_USBINTEN_REG		0x310
 
-#define	PLUM_INT_USBINTEN_WIEN		0x00000002
-#define	PLUM_INT_USBINTEN_IEN		0x00000001
+/* master-enables the USB interrupts */
+#define	PLUM_INT_USBINTEN_IEN		0x00000002
+/* enbales the clock restart request interrupts */
+#define	PLUM_INT_USBINTEN_WIEN		0x00000001
 
+/*
+ *  SmartMedia interrupts
+ */
 /* SmartMedia interrupt enable register */
 #define	PLUM_INT_SMIEN_REG		0x410