First cut of a driver for the Memory Controller ASICs found
on mvme16x and mvme17x boards.
This commit is contained in:
scw
parent
ca7a0ec817
commit
dcd1f30fb8
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@ -1,4 +1,4 @@
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# $NetBSD: files.mvme68k,v 1.37 2000/11/24 08:54:08 scw Exp $
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# $NetBSD: files.mvme68k,v 1.38 2000/11/24 09:42:09 scw Exp $
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# config file for mvme68k
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@ -78,6 +78,11 @@ file arch/mvme68k/dev/if_ie.c ie_pcctwo
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attach clmpcc at pcctwo with clmpcc_pcctwo
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file arch/mvme68k/dev/clmpcc_pcctwo.c clmpcc_pcctwo needs-flag
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# MVME16x and MVME17x Memory Controller ASICs
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device memc
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attach memc at pcctwo
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file arch/mvme68k/dev/memc.c memc
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# Memory disk for boot tape
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file dev/md_root.c memory_disk_hooks
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@ -0,0 +1,156 @@
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/* $NetBSD: memc.c,v 1.1 2000/11/24 09:42:10 scw Exp $ */
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/*-
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* Copyright (c) 2000 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Steve C. Woodford.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Support for the MEMECC and MEMC40 memory controllers on MVME1[67][27]
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*/
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#include <sys/param.h>
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#include <sys/kernel.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/malloc.h>
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#include <machine/cpu.h>
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#include <machine/bus.h>
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#include <mvme68k/mvme68k/isr.h>
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#include <mvme68k/dev/pcctwovar.h>
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#include <mvme68k/dev/memcreg.h>
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struct memc_softc {
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struct device sc_dev;
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bus_space_tag_t sc_bust;
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bus_space_handle_t sc_bush;
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};
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int memc_match(struct device *, struct cfdata *, void *);
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void memc_attach(struct device *, struct device *, void *);
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struct cfattach memc_ca = {
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sizeof(struct memc_softc), memc_match, memc_attach
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};
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extern struct cfdriver memc_cd;
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static void memc040_attach(struct memc_softc *, struct pcctwo_attach_args *);
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static void memecc_attach(struct memc_softc *, struct pcctwo_attach_args *);
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/* ARGSUSED */
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int
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memc_match(parent, cf, aux)
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struct device *parent;
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struct cfdata *cf;
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void *aux;
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{
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struct pcctwo_attach_args *pa = aux;
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bus_space_handle_t bh;
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u_int8_t chipid;
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int rv;
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if (machineid != MVME_167 && machineid != MVME_177 &&
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machineid != MVME_162 && machineid != MVME_172)
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return (0);
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if (strcmp(pa->pa_name, memc_cd.cd_name))
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return (0);
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if (bus_space_map(pa->pa_bust, pa->pa_offset, MEMC_REGSIZE, 0, &bh))
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return (0);
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rv = bus_space_peek_1(pa->pa_bust, bh, MEMC_REG_CHIP_ID, &chipid);
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bus_space_unmap(pa->pa_bust, bh, MEMC_REGSIZE);
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if (rv)
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return (0);
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/* Verify the Chip Id register is sane */
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if (chipid != MEMC_CHIP_ID_MEMC040 && chipid != MEMC_CHIP_ID_MEMECC)
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return (0);
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return (1);
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}
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/* ARGSUSED */
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void
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memc_attach(parent, self, aux)
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struct device *parent;
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struct device *self;
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void *aux;
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{
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struct pcctwo_attach_args *pa = aux;
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struct memc_softc *sc = (struct memc_softc *) self;
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u_int8_t chipid;
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u_int8_t memcfg;
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sc->sc_bust = pa->pa_bust;
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/* Map the memory controller's registers */
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bus_space_map(sc->sc_bust, pa->pa_offset, MEMC_REGSIZE, 0,
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&sc->sc_bush);
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chipid = bus_space_read_1(pa->pa_bust, sc->sc_bush, MEMC_REG_CHIP_ID);
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memcfg = bus_space_read_1(pa->pa_bust, sc->sc_bush, MEMC_REG_MEMORY_CONFIG);
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printf(": %dMB %s Memory Controller Chip\n",
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MEMC_MEMORY_CONFIG_2_MB(memcfg),
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(chipid == MEMC_CHIP_ID_MEMC040) ? "Parity" : "ECC");
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switch (chipid) {
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case MEMC_CHIP_ID_MEMC040:
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memc040_attach(sc, pa);
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break;
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case MEMC_CHIP_ID_MEMECC:
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memecc_attach(sc, pa);
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break;
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}
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}
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static void
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memc040_attach(struct memc_softc *sc, struct pcctwo_attach_args *pa)
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{
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/* XXX: TBD */
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}
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static void
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memecc_attach(struct memc_softc *sc, struct pcctwo_attach_args *pa)
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{
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/* XXX: TBD */
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}
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@ -0,0 +1,118 @@
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/* $NetBSD: memcreg.h,v 1.1 2000/11/24 09:42:10 scw Exp $ */
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/*-
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* Copyright (c) 2000 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Steve C. Woodford.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Register definitions for the MEMECC and MEMC040 devices.
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*/
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#ifndef _MVME68K_MEMCREG_H
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#define _MVME68K_MEMCREG_H
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/*
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* Size, in bytes, of the memory controller's register set
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* (Actually, the MEMC040's register set is only 0x20 bytes in size, but
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* we go with the larger of the two).
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*/
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#define MEMC_REGSIZE 0x80
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/* Both memory controllers share some registers in common */
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#define MEMC_REG_CHIP_ID 0x00
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#define MEMC_CHIP_ID_MEMC040 0x80 /* It's a MEMC040 */
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#define MEMC_CHIP_ID_MEMECC 0x81 /* It's a MEMECC */
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/* Revision of the ASIC */
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#define MEMC_REG_CHIP_REVISION 0x04
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/* Configuration of the memory block controlled by this ASIC */
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#define MEMC_REG_MEMORY_CONFIG 0x08
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#define MEMC_MEMORY_CONFIG_2_BYTES(x) (0x400000 << ((x) & 0x07))
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#define MEMC_MEMORY_CONFIG_2_MB(x) (4 << ((x) & 0x07))
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#define MEMC040_MEMORY_CONFIG_EXTPEN (1u << 3) /* External parity enabled */
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#define MEMC040_MEMORY_CONFIG_WPB (1u << 4) /* Write Per Bit mode */
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#define MEMC_MEMORY_CONFIG_FSTRD (1u << 5) /* Fast RAM Read enabled */
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/* Where, in the cpu's address space, does this memory appear? */
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#define MEMC_REG_BASE_ADDRESS_HI 0x14
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#define MEMC_REG_BASE_ADDRESS_LO 0x18
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#define MEMC_BASE_ADDRESS(hi,lo) (((hi) << 24) | (((lo) & 0xc0) << 22))
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/* Tells the memory controller what the board's Bus Clock frequency is */
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#define MEMC_REG_BUS_CLOCK 0x1c
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/* Register offsets and definitions for the Parity Memory Controller */
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#define MEMC040_REG_ALT_STATUS 0x0c /* Not used */
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#define MEMC040_REG_ALT_CONTROL 0x10 /* Not used */
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/* Memory Control Register */
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#define MEMC040_REG_RAM_CONTROL 0x18
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#define MEMC040_RAM_CONTROL_RAMEN (1u << 0)
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#define MEMC040_RAM_CONTROL_PAREN (1u << 1)
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#define MEMC040_RAM_CONTROL_PARINT (1u << 2)
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#define MEMC040_RAM_CONTROL_WWP (1u << 3)
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#define MEMC040_RAM_CONTROL_SWAIT (1u << 4)
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#define MEMC040_RAM_CONTROL_DMCTL (1u << 5)
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/* Register offsets and definitions for the ECC Memory Controller */
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#define MEMECC_REG_DRAM_CONTROL 0x18
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#define MEMECC_REG_DATA_CONTROL 0x20
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#define MEMECC_REG_SCRUB_CONTROL 0x24
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#define MEMECC_REG_SCRUB_PERIOD_HI 0x28
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#define MEMECC_REG_SCRUB_PERIOD_LO 0x2c
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#define MEMECC_REG_CHIP_PRESCALE 0x30
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#define MEMECC_REG_SCRUB_TIME_ONOFF 0x34
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#define MEMECC_REG_SCRUB_PRESCALE_HI 0x38
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#define MEMECC_REG_SCRUB_PRESCALE_MID 0x3c
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#define MEMECC_REG_SCRUB_PRESCALE_LO 0x40
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#define MEMECC_REG_SCRUB_TIMER_HI 0x44
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#define MEMECC_REG_SCRUB_TIMER_LO 0x48
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#define MEMECC_REG_SCRUB_ADDR_CNTR_HIHI 0x4c
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#define MEMECC_REG_SCRUB_ADDR_CNTR_HI 0x50
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#define MEMECC_REG_SCRUB_ADDR_CNTR_MID 0x54
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#define MEMECC_REG_SCRUB_ADDR_CNTR_LO 0x58
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#define MEMECC_REG_ERROR_LOGGER 0x5c
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#define MEMECC_REG_ERROR_ADDRESS_HIHI 0x60
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#define MEMECC_REG_ERROR_ADDRESS_HI 0x64
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#define MEMECC_REG_ERROR_ADDRESS_MID 0x68
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#define MEMECC_REG_ERROR_ADDRESS_LO 0x6c
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#define MEMECC_REG_ERROR_SYNDROME 0x70
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#define MEMECC_REG_DEFAULTS1 0x74
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#define MEMECC_REG_DEFAULTS2 0x78
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#define MEMECC_REG_SDRAM_CONFIG 0x7c
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#endif /* _MVME68K_MEMCREG_H */
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@ -1,4 +1,4 @@
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/* $NetBSD: pcctwo.c,v 1.6 2000/11/24 09:36:41 scw Exp $ */
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/* $NetBSD: pcctwo.c,v 1.7 2000/11/24 09:42:10 scw Exp $ */
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/*-
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* Copyright (c) 1999 The NetBSD Foundation, Inc.
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*/
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static struct pcctwo_device pcctwo_devices[] = {
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{"clock", PCCTWO_RTC_OFF},
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{"memc", PCCTWO_MEMC1_OFF},
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{"memc", PCCTWO_MEMC2_OFF},
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{"clmpcc", PCCTWO_SCC_OFF},
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{"ie", PCCTWO_IE_OFF},
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{"ncrsc", PCCTWO_NCRSC_OFF},
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*/
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static struct pcctwo_device mcchip_devices[] = {
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{"clock", PCCTWO_RTC_OFF},
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{"memc", PCCTWO_MEMC1_OFF},
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{"memc", PCCTWO_MEMC2_OFF},
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{"zsc", MCCHIP_ZS0_OFF},
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{"zsc", MCCHIP_ZS1_OFF},
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{"ie", PCCTWO_IE_OFF},
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@ -1,4 +1,4 @@
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/* $NetBSD: pcctworeg.h,v 1.6 2000/09/06 19:51:44 scw Exp $ */
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/* $NetBSD: pcctworeg.h,v 1.7 2000/11/24 09:42:10 scw Exp $ */
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/*-
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* Copyright (c) 1999 The NetBSD Foundation, Inc.
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@ -50,7 +50,8 @@
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*/
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#define PCCTWO_REG_OFF 0x00000 /* Offset of PCCChip2's own registers */
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#define PCCTWO_LPT_OFF 0x00000 /* Offset of parallel port registers */
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#define PCCTWO_MEMC_OFF 0x01000 /* Offset of Memory Controller's regs */
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#define PCCTWO_MEMC1_OFF 0x01000 /* Offset of Memory Controller #1 */
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#define PCCTWO_MEMC2_OFF 0x01100 /* Offset of Memory Controller #2 */
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#define PCCTWO_SCC_OFF 0x03000 /* Offset of CD2401 Serial Comms chip */
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#define PCCTWO_IE_OFF 0x04000 /* Offset of 82596 LAN controller */
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#define PCCTWO_NCRSC_OFF 0x05000 /* Offset of NCR53C710 SCSI chip */
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