Use the common code in <arm/cortex/a9_mpsubr.S>
This commit is contained in:
matt
parent
cd57af6ece
commit
d5a9a9283f
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@ -1,4 +1,4 @@
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/* $NetBSD: bcm53xx_start.S,v 1.1 2012/09/01 00:15:11 matt Exp $ */
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/* $NetBSD: bcm53xx_start.S,v 1.2 2012/09/02 05:02:36 matt Exp $ */
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/*-
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* Copyright (c) 2012 The NetBSD Foundation, Inc.
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* All rights reserved.
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@ -41,15 +41,20 @@
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#include <arm/cortex/a9tmr_reg.h>
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RCSID("$NetBSD: bcm53xx_start.S,v 1.1 2012/09/01 00:15:11 matt Exp $")
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#ifndef CONADDR
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#define CONADDR 0x18000300
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#endif
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RCSID("$NetBSD: bcm53xx_start.S,v 1.2 2012/09/02 05:02:36 matt Exp $")
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#undef VERBOSE_INIT_ARM
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#define VERBOSE_INIT_ARM
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#if defined(VERBOSE_INIT_ARM)
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#define PUTC(n) mov r0, n; bl xputc
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#define XPUTC(n) mov r0, n; bl xputc
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#define XPUTC_COM 1
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#else
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#define PUTC(n)
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#define XPUTC(n)
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#endif
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/*
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@ -61,150 +66,55 @@ RCSID("$NetBSD: bcm53xx_start.S,v 1.1 2012/09/01 00:15:11 matt Exp $")
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.global _C_LABEL(bcm53xx_start)
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_C_LABEL(bcm53xx_start):
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cpsid if, #PSR_SVC32_MODE
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PUTC(#64)
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bl _C_LABEL(armv7_icache_inv_all) @ invalidate i-cache
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/*
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* Let's turn on the CCA watchdog in case something goes horribly wrong.
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*/
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ldr r0, .Lcca_wdog
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ldr r1, .Lcca_wdog + 4
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str r1, [r0]
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/*
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* Step 1a, invalidate the all cache tags in all ways on the SCU.
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* Cal the initial start code for the a9
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*/
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PUTC(#65)
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mrc p15, 4, r3, c15, c0, 0 @ read cbar
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bl a9_start
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mrc p15, 0, r0, c0, c0, 5 @ get MPIDR
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and r0, r0, #7 @ get our cpu numder
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lsl r0, r0, #2 @ multiply by 4
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mov r1, #0xf @ select all ways
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lsl r1, r1, r0 @ shift into place
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str r1, [r3, #12] @ write scu invalidate all
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dsb
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isb
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/*
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* Step 1b, invalidate the data cache
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*/
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PUTC(#66)
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bl _C_LABEL(armv7_dcache_wbinv_all) @ writeback/invalidate d-cache
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/*
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* Step 2, disable the data cache
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*/
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mrc p15, 0, r2, c1, c0, 0 @ get system ctl register (save)
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bic r1, r2, #CPU_CONTROL_DC_ENABLE @ clear data cache enable
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mcr p15, 0, r1, c1, c0, 0 @ set system ctl register
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isb
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/*
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* Step 3, enable the SCU (and set SMP mode)
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*/
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ldr r1, [r3, #4] @ read scu config
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orr r1, r1, #0xf0 @ set smp mode
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str r1, [r3, #4] @ write scu config
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ldr r1, [r3, #0] @ read scu control
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orr r1, r1, #1 @ set scu enable flag
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str r1, [r3, #4] @ write scu control
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dsb
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isb
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/*
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* Step 4a, enable the data cache
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*/
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mcr p15, 0, r2, c1, c0, 0 @ reenable caches
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isb
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/*
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* Step 4b, set ACTLR.SMP=1 (and ACTRL.FX=1)
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*/
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mrc p15, 0, r0, c1, c0, 1 @ read aux ctl
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orr r0, #0x40 @ enable SMP mode
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mcr p15, 0, r0, c1, c0, 1 @ write aux ctl
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isb
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orr r0, #0x1 @ enable cache/tlb/coherency
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mcr p15, 0, r0, c1, c0, 1 @ write aux ctl
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isb
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PUTC(#67)
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/*
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* Set up a preliminary mapping in the MMU to allow us to run
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* at KERNEL_BASE with caches on.
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*/
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/* Build page table from scratch */
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ldr r0, .Ltemp_l1_table /* The page table address - entered into TTB later */
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mov r1, r0 /* Start address to clear memory. */
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/* Zero the entire table so all virtual addresses are invalid. */
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mov r2, #L1_TABLE_SIZE /* in bytes */
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mov r3, #0
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mov r4, r3
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mov r5, r3
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mov r6, r3
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mov r7, r3
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mov r8, r3
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mov r10, r3
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mov r11, r3
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1: stmia r1!, {r3-r8,r10-r11}
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stmia r1!, {r3-r8,r10-r11}
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stmia r1!, {r3-r8,r10-r11}
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stmia r1!, {r3-r8,r10-r11}
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subs r2, r2, #(4 * 4 * 8) /* bytes per loop */
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bne 1b
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ldr r0, .Ltemp_l1_table /* The L1PT address - entered into TTB later */
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adr r1, mmu_init_table
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bl arm_boot_l1pt_init
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/* Now create our entries per the mmu_init_table. */
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l1table .req r0
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va .req r1
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pa .req r2
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n_sec .req r3
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attr .req r4
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itable .req r5
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adr itable, mmu_init_table
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b 3f
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2: str pa, [l1table, va]
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add va, va, #4
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add pa, pa, #(L1_S_SIZE)
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subs n_sec, n_sec, #1
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bhi 2b
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3: ldmia itable!, {va,pa,n_sec,attr}
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/* Convert va to l1 offset: va = 4 * (va >> L1_S_SHIFT) */
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lsr va, va, #L1_S_SHIFT
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lsl va, va, #2
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/* Convert pa to l1 entry: pa = (pa & L1_S_FRAME) | attr */
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bfc pa, #0, #L1_S_SHIFT
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orr pa, pa, attr
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cmp n_sec, #0
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bne 2b
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.unreq va
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.unreq pa
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.unreq n_sec
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.unreq attr
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.unreq itable
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.unreq l1table
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PUTC(#68)
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XPUTC(#68)
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/*
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* Before we turn on the MMU, let's the other process out of the
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* SKU ROM but setting the magic LUT address to our own mp_start
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* routine.
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*/
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ldr r1, .Lsku_rom_lut
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adr r2, mp_start
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adr r2, a9_mpstart
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str r2, [r1]
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sev /* wake up the others */
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/*
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* init the CPU TLB, Cache, MMU.
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*/
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PUTC(#69)
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XPUTC(#69)
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ldr r0, .Ltemp_l1_table /* The page table address */
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bl cpu_init
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bl a9_cpuinit
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PUTC(#33)
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PUTC(#10)
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PUTC(#13)
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XPUTC(#33)
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XPUTC(#10)
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XPUTC(#13)
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/*
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* Let's turn off the CCA watchdog since nothing went horribly wrong.
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*/
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ldr r0, .Lcca_wdog
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mov r1, #0
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str r1, [r0]
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/*
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* Jump to start in locore.S, which in turn will call initarm and main.
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@ -220,44 +130,15 @@ _C_LABEL(bcm53xx_start):
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.Lsku_rom_lut:
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.word 0xffff0400
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.Lcca_wdog:
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.word 0x18000080
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.word 0x0fffffff /* maximum watchdog time out, about 10 seconds */
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.Ltemp_l1_table:
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/* Put the temporary L1 translation table far enough away. */
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.word KERNEL_BASE_phys + 31 * 0x100000 - L1_TABLE_SIZE
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/*
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* Coprocessor register initialization values
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*/
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.p2align 3
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/* bits to clear in the Control Register */
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.Lcontrol_clr:
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.word 0
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/* bits to set in the Control Register */
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.Lcontrol_set:
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.word CPU_CONTROL_MMU_ENABLE | \
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CPU_CONTROL_AFLT_ENABLE | \
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CPU_CONTROL_DC_ENABLE | \
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CPU_CONTROL_SYST_ENABLE | \
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CPU_CONTROL_SWP_ENABLE | \
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CPU_CONTROL_IC_ENABLE
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#if 0
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(15 << 3) | /* SBOP */ \
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(1 << 16) | /* SBO */ \
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(1 << 18) | /* SBO */ \
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(3 << 22) /* SB0 */
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#endif
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/* bits to disable the caches */
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.Lctl_ID_dis:
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.word ~(CPU_CONTROL_IC_ENABLE|CPU_CONTROL_DC_ENABLE)
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/* We'll modify va and pa at run time so we can use relocatable addresses. */
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#define MMU_INIT(va,pa,n_sec,attr) \
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.word va ; \
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.word pa ; \
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.word n_sec ; \
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.word attr ;
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#include <arm/cortex/a9_mpsubr.S>
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mmu_init_table:
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/* Add 32MB of VA==PA at 0x80000000 so we can keep the kernel going */
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@ -287,239 +168,3 @@ mmu_init_table:
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/* end of table */
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MMU_INIT(0, 0, 0, 0)
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cpu_init:
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/*
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* In theory, because the MMU is off, we shouldn't need all of this,
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* but let's not take any chances and do a typical sequence to set
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* the Translation Table Base.
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*/
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mov ip, lr
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mov r10, r0
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mov r1, #0 /* SBZ */
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ldr r3, .Lctl_ID_dis /* Disable I+D caches */
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mrc p15, 0, r2, c1, c0, 0 /* " " " */
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and r2, r2, r3 /* " " " */
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mcr p15, 0, r2, c1, c0, 0 /* " " " */
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PUTC(#70)
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mov r1, #0
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mcr p15, 0, r1, c7, c10, 4 /* Drain the write buffers. */
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PUTC(#71)
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mcr p15, 0, r10, c2, c0, 0 /* Set Translation Table Base */
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PUTC(#72)
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mov r1, #0
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mcr p15, 0, r1, c8, c7, 0 /* Invalidate TLBs */
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/* Set the Domain Access register. Very important! */
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PUTC(#74)
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mov r1, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT)
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mcr p15, 0, r1, c3, c0, 0
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/*
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* Enable the MMU, etc.
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*/
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PUTC(#75)
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mrc p15, 0, r0, c1, c0, 0
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ldr r2, .Lcontrol_clr
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bic r0, r0, r2
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ldr r3, .Lcontrol_set
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orr r0, r0, r3
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dsb
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.align 5
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@ turn mmu on!
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mov r0, r0
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mcr p15, 0, r0, c1, c0, 0
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/*
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* Ensure that the coprocessor has finished turning on the MMU.
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*/
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mrc p15, 0, r0, c0, c0, 0 /* Read an arbitrary value. */
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mov r0, r0 /* Stall until read completes. */
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bx ip /* return */
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#if defined(VERBOSE_INIT_ARM)
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#define TIMO 0x25000
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xputc:
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mov r2, #1
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ldr r3, .Lcomlock
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10:
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ldrex r1, [r3]
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cmp r1, #0
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bne 10b
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strex r1, r2, [r3]
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cmp r1, #0
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bne 10b
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mov r2, #TIMO
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ldr r3, .Luart0
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1: ldrb r1, [r3, #COM_LSR]
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tst r1, #LSR_TXRDY
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bne 2f
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subs r2, r2, #1
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bne 1b
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2:
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strb r0, [r3, #COM_DATA]
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mov r2, #TIMO
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3: ldrb r1, [r3, #COM_LSR]
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tst r1, #LSR_TSRE
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bne 4f
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subs r2, r2, #1
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bne 3b
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4:
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ldr r3, .Lcomlock
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mov r0, #0
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str r0, [r3]
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dsb
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bx lr
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.Luart0:
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.word 0x18000300
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.Lcomlock:
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.word comlock
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.pushsection .data
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comlock:
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.p2align 2
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.word 0 @ not in bss
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.popsection
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#endif /* VERBOSE_INIT_ARM */
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/*
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* Secondary processors come here after exiting the SKU ROM.
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*/
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mp_start:
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#ifdef MULTIPROCESSOR
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/*
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* Step 1, invalidate the caches
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*/
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bl _C_LABEL(armv7_icache_inv_all) @ toss i-cache
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bl _C_LABEL(armv7_dcache_inv_all) @ toss d-cache
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mrc p15, 0, r4, c0, c0, 5 @ get MPIDR
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and r4, r4, #7 @ get our cpu numder
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/*
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* Step 2, wait for the SCU to be enabled
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*/
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mrc p15, 4, r3, c15, c0, 0 @ read cbar
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1: ldr r0, [r3, #0] @ read scu control
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tst r0, #1 @ enable bit set yet?
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bne 1b @ try again
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lsl r0, r4, #2 @ multiply our cpu num by 4
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mov r1, #0xf @ select all ways
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lsl r1, r1, r0 @ shift into place
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str r1, [r3, #12] @ write scu invalidate all
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dsb
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isb
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/*
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* Step 3, set ACTLR.SMP=1 (and ACTRL.FX=1)
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*/
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mrc p15, 0, r0, c1, c0, 1 @ read aux ctl
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orr r0, #0x40 @ enable SMP
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mcr p15, 0, r0, c1, c0, 1 @ write aux ctl
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isb
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orr r0, #0x01 @ enable cache/tlb/coherency
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mcr p15, 0, r0, c1, c0, 1 @ write aux ctl
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isb
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/*
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* We should be in SMP mode now.
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*/
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#if defined(VERBOSE_INIT_ARM)
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add r0, r4, #48
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bl xputc
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#endif
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ldr r0, .Lcpu_hatched @ now show we've hatched
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mov r5, #1
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lsl r5, r5, r4
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mov r1, r5
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bl _C_LABEL(atomic_or_32)
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PUTC(#97)
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#endif
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cpsid if, #PSR_SVC32_MODE @ make sure we are in SVC mode
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/* Now we will wait for someone tell this cpu to start running */
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#ifdef MULTIPROCESSOR
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ldr r0, .Lcpu_mbox
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#else
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cmp r0, r0
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#endif
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2:
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#ifdef MULTIPROCESSOR
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dmb
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ldr r2, [r0]
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tst r2, r5
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#endif
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@wfeeq
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beq 2b
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#ifdef MULTIPROCESSOR
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3: PUTC(#98)
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ldr r0, .Lcpu_marker
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str pc, [r0]
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ldr r0, .Lkernel_l1pt /* get address of l1pt pvaddr */
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ldr r0, [r0, #PV_PA] /* Now get the phys addr */
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bl cpu_init
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ldr r0, .Lcpu_marker
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str pc, [r0]
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/* MMU, L1, are now on. */
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ldr r0, .Lcpu_info /* get pointer to cpu_infos */
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ldr r5, [r0, r4, lsl #2] /* load our cpu_info */
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ldr r6, [r5, #CI_IDLELWP] /* get the idlelwp */
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ldr r7, [r6, #L_PCB] /* now get its pcb */
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ldr sp, [r7, #PCB_SP] /* finally, we can load our SP */
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#ifdef TPIDRPRW_IS_CURCPU
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mcr p15, 0, r5, c13, c0, 4 /* squirrel away curcpu() */
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#elif defined(TPIDRPRW_IS_CURLWP)
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mcr p15, 0, r6, c13, c0, 4 /* squirrel away curlwp() */
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#else
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#error either TPIDRPRW_IS_CURCPU or TPIDRPRW_IS_CURLWP must be defined
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#endif
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str r6, [r5, #CI_CURLWP] /* and note we are running on it */
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ldr r0, .Lcpu_marker
|
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str pc, [r0]
|
||||
|
||||
mov r0, r5 /* pass cpu_info */
|
||||
mov r1, r4 /* pass cpu_id */
|
||||
ldr r2, .Lbcm53xx_cpu_hatch /* pass md_cpu_hatch */
|
||||
bl _C_LABEL(cpu_hatch)
|
||||
b _C_LABEL(idle_loop)
|
||||
|
||||
/* NOT REACHED */
|
||||
|
||||
.Lkernel_l1pt:
|
||||
.word _C_LABEL(kernel_l1pt)
|
||||
.Lcpu_info:
|
||||
.word _C_LABEL(cpu_info)
|
||||
.Lcpu_max:
|
||||
.word _C_LABEL(arm_cpu_max)
|
||||
.Lcpu_hatched:
|
||||
.word _C_LABEL(arm_cpu_hatched)
|
||||
.Lcpu_mbox:
|
||||
.word _C_LABEL(arm_cpu_mbox)
|
||||
.Lcpu_marker:
|
||||
.word _C_LABEL(arm_cpu_marker)
|
||||
.Lbcm53xx_cpu_hatch:
|
||||
.word _C_LABEL(bcm53xx_cpu_hatch)
|
||||
#endif /* MULTIPROCESSOR */
|
||||
|
|
|
|||
Loading…
Reference in New Issue