Cleanup and bring forwards from bcm53xx_start.S
Use more symbolic names ...
This commit is contained in:
matt
parent
5638e4cc1f
commit
cd57af6ece
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@ -1,4 +1,4 @@
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/* $NetBSD: a9_mpsubr.S,v 1.1 2012/09/01 00:03:14 matt Exp $ */
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/* $NetBSD: a9_mpsubr.S,v 1.2 2012/09/02 05:01:54 matt Exp $ */
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/*-
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* Copyright (c) 2012 The NetBSD Foundation, Inc.
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* All rights reserved.
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@ -34,14 +34,23 @@
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#include <arm/asm.h>
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#include <arm/armreg.h>
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#include <arm/cortex/scu_reg.h>
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#include "assym.h"
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/* We'll modify va and pa at run time so we can use relocatable addresses. */
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#define MMU_INIT(va,pa,n_sec,attr) \
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.word va ; \
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.word pa ; \
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.word n_sec ; \
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.word attr ;
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/*
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* Set up a preliminary mapping in the MMU to allow us to run
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* at KERNEL_BASE with caches on.
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*/
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arm_boot_l1pt_init:
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mv ip, r1 @ save mmu table addr
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mov ip, r1 @ save mmu table addr
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/* Build page table from scratch */
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mov r1, r0 /* Start address to clear memory. */
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/* Zero the entire table so all virtual addresses are invalid. */
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@ -72,8 +81,8 @@ arm_boot_l1pt_init:
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mov itable, ip @ reclaim table address
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b 3f
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2: str pa, [l1table, va]
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add va, va, #4
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2: str pa, [l1table, va, lsl #2]
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add va, va, #1
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add pa, pa, #(L1_S_SIZE)
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subs n_sec, n_sec, #1
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bhi 2b
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@ -81,14 +90,13 @@ arm_boot_l1pt_init:
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3: ldmia itable!, {va,pa,n_sec,attr}
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/* Convert va to l1 offset: va = 4 * (va >> L1_S_SHIFT) */
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lsr va, va, #L1_S_SHIFT
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lsl va, va, #2
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/* Convert pa to l1 entry: pa = (pa & L1_S_FRAME) | attr */
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#ifdef _ARM_ARCH_7
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bfc pa, #0, #L1_S_SHIFT
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#else
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lsr pa, pa, #L1_S_SHIFT
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lsl pa, pa, #L1_S_SHIFT
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#ndif
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#endif
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orr pa, pa, attr
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cmp n_sec, #0
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bne 2b
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@ -101,9 +109,6 @@ arm_boot_l1pt_init:
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.unreq itable
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.unreq l1table
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.Lctl_ID:
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.word CPU_CONTROL_IC_ENABLE|CPU_CONTROL_DC_ENABLE
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a9_cpuinit:
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/*
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* In theory, because the MMU is off, we shouldn't need all of this,
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@ -159,8 +164,29 @@ a9_cpuinit:
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bx ip /* return */
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#if defined(VERBOSE_INIT_ARM) && XPUTC
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/*
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* Coprocessor register initialization values
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*/
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.p2align 2
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/* bits to clear in the Control Register */
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.Lcontrol_clr:
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.word 0
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/* bits to set in the Control Register */
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.Lcontrol_set:
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.word CPU_CONTROL_MMU_ENABLE | \
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CPU_CONTROL_AFLT_ENABLE | \
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CPU_CONTROL_DC_ENABLE | \
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CPU_CONTROL_SYST_ENABLE | \
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CPU_CONTROL_SWP_ENABLE | \
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CPU_CONTROL_IC_ENABLE
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#if defined(VERBOSE_INIT_ARM) && XPUTC_COM
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#define TIMO 0x25000
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#ifndef COM_MULT
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#define COM_MULT 1
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#endif
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xputc:
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#ifdef MULTIPROCESSOR
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mov r2, #1
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@ -172,11 +198,12 @@ xputc:
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strex r1, r2, [r3]
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cmp r1, #0
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bne 10b
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dsb
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#endif
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mov r2, #TIMO
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ldr r3, .Luart0
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1: ldrb r1, [r3, #COM_LSR]
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1: ldrb r1, [r3, #(COM_LSR*COM_MULT)]
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tst r1, #LSR_TXRDY
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bne 2f
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subs r2, r2, #1
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@ -185,7 +212,7 @@ xputc:
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strb r0, [r3, #COM_DATA]
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mov r2, #TIMO
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3: ldrb r1, [r3, #COM_LSR]
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3: ldrb r1, [r3, #(COM_LSR*COM_MULT)]
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tst r1, #LSR_TSRE
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bne 4f
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subs r2, r2, #1
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@ -200,7 +227,7 @@ xputc:
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bx lr
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.Luart0:
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.word CONSADDR
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.word CONADDR
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#ifdef MULTIPROCESSOR
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.Lcomlock:
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@ -229,12 +256,12 @@ a9_start:
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*/
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XPUTC(#65)
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mrc p15, 4, r3, c15, c0, 0 @ read cbar
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ldr r0, [r3, #4] @ read scu config
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ldr r0, [r3, #SCU_CFG] @ read scu config
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and r0, r0, #7 @ get cpu max
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add r0, r0, #1 @ adjust to cpu num
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lsl r0, r0, #4 @ multiply by 16
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sub r0, r0, #1 @ make it into a mask
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str r0, [r3, #12] @ write scu invalidate all
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add r0, r0, #2 @ adjust to cpu num
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mov r1, #0xf @ select all ways
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lsl r1, r1, r0 @ shift into place
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str r1, [r3, #SCU_INV_ALL_REG] @ write scu invalidate all
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dsb
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isb
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@ -255,12 +282,9 @@ a9_start:
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/*
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* Step 3, enable the SCU (and set SMP mode)
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*/
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ldr r1, [r3, #4] @ read scu config
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orr r1, r1, #0xf0 @ set smp mode
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str r1, [r3, #4] @ write scu config
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ldr r1, [r3, #0] @ read scu control
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orr r1, r1, #1 @ set scu enable flag
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str r1, [r3, #4] @ write scu control
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ldr r1, [r3, #SCU_CTL] @ read scu control
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orr r1, r1, #SCU_CTL_SCU_ENA @ set scu enable flag
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str r1, [r3, #SCU_CTL] @ write scu control
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dsb
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isb
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@ -274,12 +298,15 @@ a9_start:
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* Step 4b, set ACTLR.SMP=1 (and ACTRL.FX=1)
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*/
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mrc p15, 0, r0, c1, c0, 1 @ read aux ctl
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orr r0, #0x41 @ enable cache/tlb/coherency
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orr r0, #CORTEXA9_AUXCTL_SMP @ enable SMP
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mcr p15, 0, r0, c1, c0, 1 @ write aux ctl
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isb
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orr r0, #CORTEXA9_AUXCTL_FW @ enable cache/tlb/coherency
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mcr p15, 0, r0, c1, c0, 1 @ write aux ctl
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isb
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bx r10
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ASEND(a9_startup)
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ASEND(a9_start)
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/*
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* Secondary processors come here after exiting the SKU ROM.
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@ -296,16 +323,20 @@ a9_mpstart:
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* Step 2, wait for the SCU to be enabled
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*/
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mrc p15, 4, r3, c15, c0, 0 @ read cbar
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1: ldr r0, [r3, #0] @ read scu control
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tst r0, #1 @ enable bit set yet?
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1: ldr r0, [r3, #SCU_CTL] @ read scu control
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tst r0, #SCU_CTL_SCU_ENA @ enable bit set yet?
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bne 1b @ try again
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/*
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* Step 3, set ACTLR.SMP=1 (and ACTRL.FX=1)
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*/
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mrc p15, 0, r0, c1, c0, 1 @ read aux ctl
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orr r0, #0x41 @ enable cache/tlb/coherency
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orr r0, #CORTEXA9_AUXCTL_SMP @ enable SMP
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mcr p15, 0, r0, c1, c0, 1 @ write aux ctl
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mov r0, r0
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orr r0, #CORTEXA9_AUXCTL_FW @ enable cache/tlb/coherency
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mcr p15, 0, r0, c1, c0, 1 @ write aux ctl
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mov r0, r0
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/*
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* We should be in SMP mode now.
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@ -380,7 +411,7 @@ a9_mpstart:
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ldr r2, .Lbcm53xx_cpu_hatch /* pass md_cpu_hatch */
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bl _C_LABEL(cpu_hatch)
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b _C_LABEL(idle_loop)
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ASEND(a9_mpstart)
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/* NOT REACHED */
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.Lkernel_l1pt:
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