Cleanup ICU (i8259 compatible PIC) interrupt handling code:
- move ICU interrupt stuff from pci/pcib.h to cobalt/machdep.c because ICU should be initialized before pcib is attached - initialize ICU more properly - check interrupt types and set ELCR (edge/level control registers) accordingly in icu_intr_establish() - check requested IRQ line and call only a necessary hander in icu_intr() - use specific EOI to ack interrupts rather than AEOI - use macro defined in <dev/ic/i8259reg.h>
This commit is contained in:
tsutsui
parent
4b02662f6c
commit
cbe0593dd5
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@ -1,4 +1,4 @@
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/* $NetBSD: autoconf.c,v 1.19 2006/04/21 18:17:45 tsutsui Exp $ */
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/* $NetBSD: autoconf.c,v 1.20 2006/05/31 12:59:39 tsutsui Exp $ */
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/*
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* Copyright (c) 2000 Soren S. Jorvang. All rights reserved.
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@ -26,7 +26,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.19 2006/04/21 18:17:45 tsutsui Exp $");
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__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.20 2006/05/31 12:59:39 tsutsui Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -35,6 +35,7 @@ __KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.19 2006/04/21 18:17:45 tsutsui Exp $"
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#include <sys/device.h>
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#include <machine/cpu.h>
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#include <machine/intr.h>
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#include <cobalt/cobalt/clockvar.h>
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@ -52,6 +53,7 @@ cpu_configure(void)
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(void)splhigh();
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evcnt_attach_static(&hardclock_ev);
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icu_init();
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if (config_rootfound("mainbus", NULL) == NULL)
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panic("no mainbus found");
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@ -1,4 +1,31 @@
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/* $NetBSD: machdep.c,v 1.66 2006/04/21 18:21:30 tsutsui Exp $ */
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/* $NetBSD: machdep.c,v 1.67 2006/05/31 12:59:39 tsutsui Exp $ */
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/*
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* Copyright (c) 2006 Izumi Tsutsui.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 2000 Soren S. Jorvang. All rights reserved.
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@ -26,7 +53,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.66 2006/04/21 18:21:30 tsutsui Exp $");
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__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.67 2006/05/31 12:59:39 tsutsui Exp $");
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#include "opt_ddb.h"
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#include "opt_kgdb.h"
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@ -61,6 +88,7 @@ __KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.66 2006/04/21 18:21:30 tsutsui Exp $")
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#include <machine/pte.h>
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#include <machine/autoconf.h>
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#include <machine/bootinfo.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <mips/locore.h>
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@ -69,10 +97,14 @@ __KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.66 2006/04/21 18:21:30 tsutsui Exp $")
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#include <dev/cons.h>
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#include <dev/ic/i8259reg.h>
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#include <dev/isa/isareg.h>
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#include <cobalt/cobalt/clockvar.h>
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#include <cobalt/dev/gtreg.h>
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#define GT_BASE 0x14000000 /* XXX */
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#define PCIB_BASE 0x10000000 /* XXX */
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#ifdef KGDB
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#include <sys/kgdb.h>
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@ -400,9 +432,28 @@ cpu_reboot(int howto, char *bootstr)
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;
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}
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#define NINTR 6
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static struct cobalt_intrhand intrtab[NINTR];
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#define NCPU_INT 6
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#define NICU_INT 16
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#define IRQ_SLAVE 2
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#define IO_ELCR 0x4d0
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#define IO_ELCRSIZE 2
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#define ELCR0 0
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#define ELCR1 1
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#define ICU1_READ(reg) \
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bus_space_read_1(icu_bst, icu1_bsh, (reg))
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#define ICU1_WRITE(reg, val) \
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bus_space_write_1(icu_bst, icu1_bsh, (reg), (val))
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#define ICU2_READ(reg) \
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bus_space_read_1(icu_bst, icu2_bsh, (reg))
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#define ICU2_WRITE(reg, val) \
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bus_space_write_1(icu_bst, icu2_bsh, (reg), (val))
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#define ELCR_READ(reg) \
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bus_space_read_1(icu_bst, elcr_bsh, (reg))
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#define ELCR_WRITE(reg, val) \
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bus_space_write_1(icu_bst, elcr_bsh, (reg), (val))
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const uint32_t mips_ipl_si_to_sr[_IPL_NSOFT] = {
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MIPS_SOFT_INT_MASK_0, /* IPL_SOFT */
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@ -411,15 +462,195 @@ const uint32_t mips_ipl_si_to_sr[_IPL_NSOFT] = {
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MIPS_SOFT_INT_MASK_1, /* IPL_SOFTSERIAL */
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};
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u_int icu_imen;
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static bus_space_tag_t icu_bst;
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static bus_space_handle_t icu1_bsh, icu2_bsh, elcr_bsh;
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static struct cobalt_intrhand cpu_intrtab[NCPU_INT];
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static struct cobalt_intrhand icu_intrtab[NICU_INT];
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static int icu_intr(void *);
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static void icu_reinit_irqs(void);
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static u_int icu_setmask(u_int);
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void
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icu_init(void)
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{
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icu_bst = 0; /* XXX unused on cobalt */
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bus_space_map(icu_bst, PCIB_BASE + IO_ICU1, IO_ICUSIZE, 0, &icu1_bsh);
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bus_space_map(icu_bst, PCIB_BASE + IO_ICU2, IO_ICUSIZE, 0, &icu2_bsh);
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bus_space_map(icu_bst, PCIB_BASE + IO_ELCR, IO_ELCRSIZE, 0, &elcr_bsh);
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/* Initialize master PIC */
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/* reset; program device, four bytes */
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ICU1_WRITE(PIC_ICW1, ICW1_SELECT | ICW1_IC4);
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/* starting at this vector index */
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ICU1_WRITE(PIC_ICW2, 0); /* XXX */
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/* slave on line 2 */
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ICU1_WRITE(PIC_ICW3, ICW3_CASCADE(IRQ_SLAVE));
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/* special fully nested mode, 8086 mode */
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ICU1_WRITE(PIC_ICW4, ICW4_SFNM | ICW4_8086);
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/* special mask mode */
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ICU1_WRITE(PIC_OCW3, OCW3_SELECT | OCW3_SSMM | OCW3_SMM);
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/* read IRR by default */
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ICU1_WRITE(PIC_OCW3, OCW3_SELECT | OCW3_RR);
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/* Initialize slave PIC */
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/* reset; program device, four bytes */
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ICU2_WRITE(PIC_ICW1, ICW1_SELECT | ICW1_IC4);
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/* starting at this vector index */
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ICU2_WRITE(PIC_ICW2, 8); /* XXX */
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/* slave connected to line 2 of master */
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ICU2_WRITE(PIC_ICW3, ICW3_SIC(IRQ_SLAVE));
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/* special fully nested mode, 8086 mode */
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ICU2_WRITE(PIC_ICW4, ICW4_SFNM | ICW4_8086);
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/* special mask mode */
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ICU2_WRITE(PIC_OCW3, OCW3_SELECT | OCW3_SSMM | OCW3_SMM);
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/* read IRR by default */
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ICU2_WRITE(PIC_OCW3, OCW3_SELECT | OCW3_RR);
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icu_setmask(0xffff); /* mask all interrupts */
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/* default to edge-triggered */
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ELCR_WRITE(ELCR0, 0);
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ELCR_WRITE(ELCR1, 0);
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wbflush();
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cpu_intr_establish(4, IPL_NONE, icu_intr, NULL);
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}
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void *
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icu_intr_establish(int irq, int type, int ipl, int (*func)(void *),
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void *arg)
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{
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struct cobalt_intrhand *ih;
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ih = &icu_intrtab[irq];
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if (ih->ih_func != NULL)
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panic("icu_intr_establish(): irq %d is already in use", irq);
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ih->ih_cookie_type = COBALT_COOKIE_TYPE_ICU;
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ih->ih_func = func;
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ih->ih_arg = arg;
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ih->ih_type = type;
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snprintf(ih->ih_evname, sizeof(ih->ih_evname), "irq %d", irq);
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evcnt_attach_dynamic(&ih->ih_evcnt, EVCNT_TYPE_INTR, NULL, "icu",
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ih->ih_evname);
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icu_reinit_irqs();
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return ih;
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}
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void
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icu_intr_disestablish(void *cookie)
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{
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struct cobalt_intrhand *ih = cookie;
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if (ih->ih_cookie_type == COBALT_COOKIE_TYPE_ICU) {
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ih->ih_func = NULL;
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ih->ih_arg = NULL;
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ih->ih_cookie_type = 0;
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ih->ih_type = IST_NONE;
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evcnt_detach(&ih->ih_evcnt);
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icu_reinit_irqs();
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}
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}
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void
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icu_reinit_irqs(void)
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{
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u_int i, irqs, elcr;
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/* unmask interrupts */
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irqs = 0;
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elcr = 0;
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for (i = 0; i < NICU_INT; i++) {
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if (icu_intrtab[i].ih_func) {
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irqs |= 1 << i;
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if (icu_intrtab[i].ih_type == IST_LEVEL)
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elcr |= 1 << i;
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}
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}
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if (irqs & 0xff00) /* any slave IRQs in use */
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irqs |= 1 << IRQ_SLAVE;
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icu_imen = ~irqs;
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ICU1_WRITE(PIC_OCW1, icu_imen);
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ICU2_WRITE(PIC_OCW1, icu_imen >> 8);
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ELCR_WRITE(ELCR0, elcr);
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ELCR_WRITE(ELCR1, elcr >> 8);
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}
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u_int
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icu_setmask(u_int mask)
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{
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u_int old;
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old = icu_imen;
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icu_imen = mask;
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ICU1_WRITE(PIC_OCW1, icu_imen);
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ICU2_WRITE(PIC_OCW1, icu_imen >> 8);
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return old;
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}
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int
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icu_intr(void *arg)
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{
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struct cobalt_intrhand *ih;
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int irq, handled;
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handled = 0;
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/* check requested irq */
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ICU1_WRITE(PIC_OCW3, OCW3_SELECT | OCW3_POLL);
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irq = ICU1_READ(PIC_OCW3);
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if ((irq & OCW3_POLL_PENDING) == 0)
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goto out;
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irq = OCW3_POLL_IRQ(irq);
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if (irq == IRQ_SLAVE) {
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ICU2_WRITE(PIC_OCW3, OCW3_SELECT | OCW3_POLL);
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irq = OCW3_POLL_IRQ(ICU2_READ(PIC_OCW3)) + 8;
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}
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ih = &icu_intrtab[irq];
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if (ih->ih_func == NULL) {
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printf("icu_intr(): spurious interrupt (irq = %d)\n", irq);
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} else if ((*ih->ih_func)(ih->ih_arg)) {
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ih->ih_evcnt.ev_count++;
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handled = 1;
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}
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/* issue EOI to ack */
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if (irq >= 8) {
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ICU2_WRITE(PIC_OCW2,
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OCW2_SELECT | OCW2_SL | OCW2_EOI | OCW2_ILS(irq - 8));
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irq = IRQ_SLAVE;
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}
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ICU1_WRITE(PIC_OCW2, OCW2_SELECT | OCW2_SL | OCW2_EOI | OCW2_ILS(irq));
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out:
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return handled;
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}
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void *
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cpu_intr_establish(int level, int ipl, int (*func)(void *), void *arg)
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{
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struct cobalt_intrhand *ih;
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if (level < 0 || level >= NINTR)
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if (level < 0 || level >= NCPU_INT)
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panic("invalid interrupt level");
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ih = &intrtab[level];
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ih = &cpu_intrtab[level];
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if (ih->ih_func != NULL)
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panic("cannot share CPU interrupts");
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@ -427,7 +658,7 @@ cpu_intr_establish(int level, int ipl, int (*func)(void *), void *arg)
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ih->ih_cookie_type = COBALT_COOKIE_TYPE_CPU;
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ih->ih_func = func;
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ih->ih_arg = arg;
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snprintf(ih->ih_evname, sizeof(ih->ih_evname), "level %d", level);
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snprintf(ih->ih_evname, sizeof(ih->ih_evname), "int %d", level);
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evcnt_attach_dynamic(&ih->ih_evcnt, EVCNT_TYPE_INTR, NULL,
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"cpu", ih->ih_evname);
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@ -451,11 +682,23 @@ void
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cpu_intr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending)
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{
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struct clockframe cf;
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static uint32_t cycles;
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struct cobalt_intrhand *ih;
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uvmexp.intrs++;
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if (ipending & MIPS_INT_MASK_5) {
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mips3_cp0_compare_write(mips3_cp0_count_read()); /* XXX */
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#if 0
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cf.pc = pc;
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cf.sr = status;
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statclock(&cf);
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#endif
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cause &= ~MIPS_INT_MASK_5;
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}
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_splset((status & MIPS_INT_MASK_5) | MIPS_SR_INT_IE);
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if (ipending & MIPS_INT_MASK_0) {
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/* GT64x11 timer0 for hardclock */
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volatile uint32_t *irq_src =
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@ -467,6 +710,29 @@ cpu_intr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending)
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cf.pc = pc;
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cf.sr = status;
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if ((status & MIPS_INT_MASK) == MIPS_INT_MASK) {
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if ((ipending & MIPS_INT_MASK &
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~MIPS_INT_MASK_0) == 0) {
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/*
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* If all interrupts were enabled and
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* there is no pending interrupts,
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* set MIPS_SR_INT_IE so that
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* spllowerclock() in hardclock()
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* works properly.
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*/
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#if 0 /* MIPS_SR_INT_IE is enabled above */
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_splset(MIPS_SR_INT_IE);
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#endif
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} else {
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/*
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* If there are any pending interrputs,
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* clear MIPS_SR_INT_IE in cf.sr so that
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* spllowerclock() in hardclock() will
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* not happen.
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*/
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cf.sr &= ~MIPS_SR_INT_IE;
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}
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}
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hardclock(&cf);
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hardclock_ev.ev_count++;
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}
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@ -474,23 +740,9 @@ cpu_intr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending)
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}
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_splset((status & ~cause & MIPS_HARD_INT_MASK) | MIPS_SR_INT_IE);
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if (ipending & MIPS_INT_MASK_5) {
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cycles = mips3_cp0_count_read();
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mips3_cp0_compare_write(cycles + 1250000); /* XXX */
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#if 0
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cf.pc = pc;
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cf.sr = status;
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statclock(&cf);
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#endif
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cause &= ~MIPS_INT_MASK_5;
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}
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_splset((status & ~cause & MIPS_HARD_INT_MASK) | MIPS_SR_INT_IE);
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if (ipending & MIPS_INT_MASK_3) {
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/* 16650 serial */
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ih = &intrtab[3];
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ih = &cpu_intrtab[3];
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if (ih->ih_func != NULL) {
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if ((*ih->ih_func)(ih->ih_arg)) {
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cause &= ~MIPS_INT_MASK_3;
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|
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@ -502,7 +754,7 @@ cpu_intr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending)
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if (ipending & MIPS_INT_MASK_1) {
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/* tulip primary */
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ih = &intrtab[1];
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ih = &cpu_intrtab[1];
|
||||
if (ih->ih_func != NULL) {
|
||||
if ((*ih->ih_func)(ih->ih_arg)) {
|
||||
cause &= ~MIPS_INT_MASK_1;
|
||||
|
|
@ -512,7 +764,7 @@ cpu_intr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending)
|
|||
}
|
||||
if (ipending & MIPS_INT_MASK_2) {
|
||||
/* tulip secondary */
|
||||
ih = &intrtab[2];
|
||||
ih = &cpu_intrtab[2];
|
||||
if (ih->ih_func != NULL) {
|
||||
if ((*ih->ih_func)(ih->ih_arg)) {
|
||||
cause &= ~MIPS_INT_MASK_2;
|
||||
|
|
@ -524,7 +776,7 @@ cpu_intr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending)
|
|||
|
||||
if (ipending & MIPS_INT_MASK_4) {
|
||||
/* ICU interrupts */
|
||||
ih = &intrtab[4];
|
||||
ih = &cpu_intrtab[4];
|
||||
if (ih->ih_func != NULL) {
|
||||
if ((*ih->ih_func)(ih->ih_arg)) {
|
||||
cause &= ~MIPS_INT_MASK_4;
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: intr.h,v 1.20 2006/04/21 18:17:45 tsutsui Exp $ */
|
||||
/* $NetBSD: intr.h,v 1.21 2006/05/31 12:59:39 tsutsui Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2000 Soren S. Jorvang. All rights reserved.
|
||||
|
|
@ -103,6 +103,7 @@ struct cobalt_intrhand {
|
|||
LIST_ENTRY(cobalt_intrhand) ih_q;
|
||||
int (*ih_func)(void *);
|
||||
void *ih_arg;
|
||||
int ih_type;
|
||||
int ih_cookie_type;
|
||||
#define COBALT_COOKIE_TYPE_CPU 0x1
|
||||
#define COBALT_COOKIE_TYPE_ICU 0x2
|
||||
|
|
@ -117,6 +118,7 @@ void *cpu_intr_establish(int, int, int (*)(void *), void *);
|
|||
void *icu_intr_establish(int, int, int, int (*)(void *), void *);
|
||||
void cpu_intr_disestablish(void *);
|
||||
void icu_intr_disestablish(void *);
|
||||
void icu_init(void);
|
||||
|
||||
#endif /* !_LOCORE */
|
||||
#endif /* _LOCORE */
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: pcib.c,v 1.17 2006/04/21 18:17:45 tsutsui Exp $ */
|
||||
/* $NetBSD: pcib.c,v 1.18 2006/05/31 12:59:39 tsutsui Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2000 Soren S. Jorvang. All rights reserved.
|
||||
|
|
@ -26,7 +26,7 @@
|
|||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: pcib.c,v 1.17 2006/04/21 18:17:45 tsutsui Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: pcib.c,v 1.18 2006/05/31 12:59:39 tsutsui Exp $");
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <sys/param.h>
|
||||
|
|
@ -37,25 +37,17 @@ __KERNEL_RCSID(0, "$NetBSD: pcib.c,v 1.17 2006/04/21 18:17:45 tsutsui Exp $");
|
|||
#include <machine/cpu.h>
|
||||
#include <machine/bus.h>
|
||||
#include <machine/autoconf.h>
|
||||
#include <machine/intr.h>
|
||||
|
||||
#include <dev/pci/pcivar.h>
|
||||
#include <dev/pci/pcireg.h>
|
||||
#include <dev/pci/pcidevs.h>
|
||||
|
||||
#include <dev/isa/isareg.h>
|
||||
|
||||
#define PCIB_BASE 0x10000000 /* XXX */
|
||||
|
||||
static int pcib_match(struct device *, struct cfdata *, void *);
|
||||
static void pcib_attach(struct device *, struct device *, void *);
|
||||
static int icu_intr(void *);
|
||||
|
||||
CFATTACH_DECL(pcib, sizeof(struct device),
|
||||
pcib_match, pcib_attach, NULL, NULL);
|
||||
|
||||
static struct cobalt_intrhand icu[IO_ICUSIZE];
|
||||
|
||||
static int
|
||||
pcib_match(struct device *parent, struct cfdata *match, void *aux)
|
||||
{
|
||||
|
|
@ -78,74 +70,4 @@ pcib_attach(struct device *parent, struct device *self, void *aux)
|
|||
printf("\n%s: %s, rev %d\n", self->dv_xname, devinfo,
|
||||
PCI_REVISION(pa->pa_class));
|
||||
|
||||
/*
|
||||
* Initialize ICU. Since we block all these interrupts with
|
||||
* splbio(), we can just enable all of them all the time here.
|
||||
*/
|
||||
*(volatile uint8_t *)MIPS_PHYS_TO_KSEG1(PCIB_BASE + IO_ICU1) = 0x10;
|
||||
*(volatile uint8_t *)MIPS_PHYS_TO_KSEG1(PCIB_BASE + IO_ICU1 + 1) = 0xff;
|
||||
*(volatile uint8_t *)MIPS_PHYS_TO_KSEG1(PCIB_BASE + IO_ICU2) = 0x10;
|
||||
*(volatile uint8_t *)MIPS_PHYS_TO_KSEG1(PCIB_BASE + IO_ICU2 + 1) = 0xff;
|
||||
wbflush();
|
||||
|
||||
cpu_intr_establish(4, IPL_NONE, icu_intr, NULL);
|
||||
}
|
||||
|
||||
void *
|
||||
icu_intr_establish(int irq, int type, int level, int (*func)(void *),
|
||||
void *arg)
|
||||
{
|
||||
struct cobalt_intrhand *ih;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < IO_ICUSIZE; i++) {
|
||||
ih = &icu[i];
|
||||
if (ih->ih_func == NULL) {
|
||||
ih->ih_cookie_type = COBALT_COOKIE_TYPE_ICU;
|
||||
ih->ih_func = func;
|
||||
ih->ih_arg = arg;
|
||||
snprintf(ih->ih_evname, sizeof(ih->ih_evname),
|
||||
"irq %d", irq);
|
||||
evcnt_attach_dynamic(&ih->ih_evcnt, EVCNT_TYPE_INTR,
|
||||
NULL, "icu", ih->ih_evname);
|
||||
return ih;
|
||||
}
|
||||
}
|
||||
|
||||
panic("too many IRQs");
|
||||
}
|
||||
|
||||
void
|
||||
icu_intr_disestablish(void *cookie)
|
||||
{
|
||||
struct cobalt_intrhand *ih = cookie;
|
||||
|
||||
if (ih->ih_cookie_type == COBALT_COOKIE_TYPE_ICU) {
|
||||
ih->ih_func = NULL;
|
||||
ih->ih_arg = NULL;
|
||||
ih->ih_cookie_type = 0;
|
||||
evcnt_detach(&ih->ih_evcnt);
|
||||
}
|
||||
}
|
||||
|
||||
int
|
||||
icu_intr(void *arg)
|
||||
{
|
||||
struct cobalt_intrhand *ih;
|
||||
int i, handled;
|
||||
|
||||
handled = 0;
|
||||
|
||||
for (i = 0; i < IO_ICUSIZE; i++) {
|
||||
ih = &icu[i];
|
||||
if (ih->ih_func == NULL)
|
||||
break;
|
||||
|
||||
if ((*ih->ih_func)(ih->ih_arg)) {
|
||||
ih->ih_evcnt.ev_count++;
|
||||
handled = 1;
|
||||
}
|
||||
}
|
||||
|
||||
return handled;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue