Now using dev/ic/ncr53c9x.c
This commit is contained in:
gwr
parent
c921c9b954
commit
c3f299a527
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@ -1,4 +1,4 @@
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/* $NetBSD: dma.c,v 1.3 1997/03/15 18:11:00 is Exp $ */
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/* $NetBSD: dma.c,v 1.4 1997/03/20 16:01:38 gwr Exp $ */
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/*
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* Copyright (c) 1994 Paul Kranenburg. All rights reserved.
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@ -48,33 +48,15 @@
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#include <scsi/scsi_all.h>
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#include <scsi/scsiconf.h>
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#include <dev/ic/ncr53c9xreg.h>
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#include <dev/ic/ncr53c9xvar.h>
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#include <sun3x/dev/dmareg.h>
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#include <sun3x/dev/dmavar.h>
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#include <sun3x/dev/espreg.h>
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#include <sun3x/dev/espvar.h>
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void dmaattach __P((struct device *, struct device *, void *));
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void dma_reset __P((struct dma_softc *));
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void dma_enintr __P((struct dma_softc *));
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int dma_isintr __P((struct dma_softc *));
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int espdmaintr __P((struct dma_softc *));
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int dma_setup __P((struct dma_softc *, caddr_t *, size_t *,
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int, size_t *));
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void dma_go __P((struct dma_softc *));
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#if 0
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struct cfattach dma_ca = {
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sizeof(struct dma_softc), dmamatch, dmaattach
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};
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struct cfdriver dma_cd = {
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NULL, "dma", DV_DULL
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};
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#endif /* 0 */
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/*
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* Pseudo-attach function. Called from the esp driver during its
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* attach function.
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* attach function. This needs to be silent.
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*/
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void
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dmaattach(parent, self, aux)
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@ -99,8 +81,25 @@ dmaattach(parent, self, aux)
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* Sun3x works ok (so far) without it.
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*/
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printf(": rev ");
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sc->sc_rev = sc->sc_regs->csr & D_DEV_ID;
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#if 0
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/* indirect functions */
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sc->intr = espdmaintr;
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sc->enintr = dma_enintr;
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sc->isintr = dma_isintr;
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sc->reset = dma_reset;
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sc->setup = dma_setup;
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sc->go = dma_go;
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#endif
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}
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void
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dma_print_rev(sc)
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struct dma_softc *sc;
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{
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printf("espdma: rev ");
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switch (sc->sc_rev) {
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case DMAREV_0:
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printf("0");
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@ -121,16 +120,9 @@ dmaattach(parent, self, aux)
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printf("unknown (0x%x)", sc->sc_rev);
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}
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printf("\n");
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/* indirect functions */
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sc->intr = espdmaintr;
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sc->enintr = dma_enintr;
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sc->isintr = dma_isintr;
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sc->reset = dma_reset;
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sc->setup = dma_setup;
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sc->go = dma_go;
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}
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#define DMAWAIT(SC, COND, MSG, DONTPANIC) do if (COND) { \
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int count = 500000; \
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while ((COND) && --count > 0) DELAY(1); \
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@ -178,8 +170,6 @@ dma_reset(sc)
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/*DMAWAIT1(sc); why was this here? */
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DMACSR(sc) &= ~D_RESET; /* de-assert reset line */
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DMACSR(sc) |= D_INT_EN; /* enable interrupts */
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if (sc->sc_rev > DMAREV_1) /* XXX - needed in 3x? */
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DMACSR(sc) |= D_FASTER;
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sc->sc_active = 0; /* and of course we aren't */
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}
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@ -223,7 +213,7 @@ dma_setup(sc, addr, len, datain, dmasize)
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sc->sc_dmaaddr = addr;
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sc->sc_dmalen = len;
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ESP_DMA(("%s: start %d@%p,%d\n", sc->sc_dev.dv_xname,
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NCR_DMA(("%s: start %d@%p,%d\n", sc->sc_dev.dv_xname,
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*sc->sc_dmalen, *sc->sc_dmaaddr, datain ? 1 : 0));
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/*
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@ -234,7 +224,7 @@ dma_setup(sc, addr, len, datain, dmasize)
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*dmasize = sc->sc_dmasize =
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min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr));
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ESP_DMA(("dma_setup: dmasize = %d\n", sc->sc_dmasize));
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NCR_DMA(("dma_setup: dmasize = %d\n", sc->sc_dmasize));
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/* Program the DMA address */
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if (sc->sc_dmasize) {
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@ -243,7 +233,7 @@ dma_setup(sc, addr, len, datain, dmasize)
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*/
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sc->sc_dvmaaddr = *sc->sc_dmaaddr;
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sc->sc_dvmakaddr = dvma_mapin(sc->sc_dvmaaddr,
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sc->sc_dmasize, 0);
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sc->sc_dmasize, 0);
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if (sc->sc_dvmakaddr == NULL)
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panic("dma: cannot allocate DVMA address");
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sc->sc_dmasaddr = dvma_kvtopa(sc->sc_dvmakaddr, BUS_OBIO);
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@ -292,14 +282,15 @@ int
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espdmaintr(sc)
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struct dma_softc *sc;
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{
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struct ncr53c9x_softc *nsc = sc->sc_esp;
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char bits[64];
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int trans, resid;
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u_long csr;
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csr = DMACSR(sc);
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ESP_DMA(("%s: intr: addr %x, csr %s\n", sc->sc_dev.dv_xname,
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DMADDR(sc), bitmask_snprintf(csr, DMACSRBITS, bits,
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sizeof(bits))));
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NCR_DMA(("%s: intr: addr %x, csr %s\n",
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sc->sc_dev.dv_xname, DMADDR(sc),
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bitmask_snprintf(csr, DMACSRBITS, bits, sizeof(bits))));
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if (csr & D_ERR_PEND) {
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DMACSR(sc) &= ~D_EN_DMA; /* Stop DMA */
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@ -321,11 +312,11 @@ espdmaintr(sc)
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if (sc->sc_dmasize == 0) {
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/* A "Transfer Pad" operation completed */
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ESP_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n",
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ESP_READ_REG(sc->sc_esp, ESP_TCL) |
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(ESP_READ_REG(sc->sc_esp, ESP_TCM) << 8),
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ESP_READ_REG(sc->sc_esp, ESP_TCL),
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ESP_READ_REG(sc->sc_esp, ESP_TCM)));
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NCR_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n",
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NCR_READ_REG(nsc, NCR_TCL) |
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(NCR_READ_REG(nsc, NCR_TCM) << 8),
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NCR_READ_REG(nsc, NCR_TCL),
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NCR_READ_REG(nsc, NCR_TCM)));
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return 0;
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}
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@ -337,24 +328,24 @@ espdmaintr(sc)
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* bytes are clocked into the FIFO.
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*/
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if (!(csr & D_WRITE) &&
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(resid = (ESP_READ_REG(sc->sc_esp, ESP_FFLAG) & ESPFIFO_FF)) != 0) {
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ESP_DMA(("dmaintr: empty esp FIFO of %d ", resid));
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ESPCMD(sc->sc_esp, ESPCMD_FLUSH);
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(resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) {
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NCR_DMA(("dmaintr: empty esp FIFO of %d ", resid));
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NCRCMD(nsc, NCRCMD_FLUSH);
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}
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if ((sc->sc_esp->sc_espstat & ESPSTAT_TC) == 0) {
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if ((nsc->sc_espstat & NCRSTAT_TC) == 0) {
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/*
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* `Terminal count' is off, so read the residue
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* out of the ESP counter registers.
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*/
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resid += ( ESP_READ_REG(sc->sc_esp, ESP_TCL) |
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(ESP_READ_REG(sc->sc_esp, ESP_TCM) << 8) |
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((sc->sc_esp->sc_cfg2 & ESPCFG2_FE)
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? (ESP_READ_REG(sc->sc_esp, ESP_TCH) << 16)
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resid += (NCR_READ_REG(nsc, NCR_TCL) |
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(NCR_READ_REG(nsc, NCR_TCM) << 8) |
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((nsc->sc_cfg2 & NCRCFG2_FE)
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? (NCR_READ_REG(nsc, NCR_TCH) << 16)
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: 0));
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if (resid == 0 && sc->sc_dmasize == 65536 &&
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(sc->sc_esp->sc_cfg2 & ESPCFG2_FE) == 0)
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(nsc->sc_cfg2 & NCRCFG2_FE) == 0)
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/* A transfer of 64K is encoded as `TCL=TCM=0' */
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resid = 65536;
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}
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@ -366,11 +357,11 @@ espdmaintr(sc)
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trans = sc->sc_dmasize;
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}
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ESP_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n",
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ESP_READ_REG(sc->sc_esp, ESP_TCL),
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ESP_READ_REG(sc->sc_esp, ESP_TCM),
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(sc->sc_esp->sc_cfg2 & ESPCFG2_FE)
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? ESP_READ_REG(sc->sc_esp, ESP_TCH) : 0,
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NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n",
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NCR_READ_REG(nsc, NCR_TCL),
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NCR_READ_REG(nsc, NCR_TCM),
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(nsc->sc_cfg2 & NCRCFG2_FE)
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? NCR_READ_REG(nsc, NCR_TCH) : 0,
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trans, resid));
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#ifdef SUN3X_470_EVENTUALLY
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@ -386,7 +377,7 @@ espdmaintr(sc)
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#if 0 /* this is not normal operation just yet */
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if (*sc->sc_dmalen == 0 ||
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sc->sc_esp->sc_phase != sc->sc_esp->sc_prevphase)
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nsc->sc_phase != nsc->sc_prevphase)
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return 0;
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/* and again */
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@ -1,4 +1,4 @@
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/* $NetBSD: dmavar.h,v 1.2 1997/03/15 18:11:02 is Exp $ */
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/* $NetBSD: dmavar.h,v 1.3 1997/03/20 16:01:39 gwr Exp $ */
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/*
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* Copyright (c) 1994 Peter Galbavy. All rights reserved.
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@ -30,7 +30,7 @@
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struct dma_softc {
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struct device sc_dev; /* us as a device */
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struct esp_softc *sc_esp; /* my scsi */
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struct ncr53c9x_softc *sc_esp; /* my scsi */
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struct dma_regs *sc_regs; /* the registers */
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int sc_active; /* DMA active ? */
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u_int sc_rev; /* revision */
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@ -41,25 +41,27 @@ struct dma_softc {
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size_t sc_dmasize;
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caddr_t *sc_dmaaddr;
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size_t *sc_dmalen;
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#if 0
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void (*reset)(struct dma_softc *); /* reset routine */
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void (*enintr)(struct dma_softc *); /* enable interrupts */
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int (*isintr)(struct dma_softc *); /* interrupt ? */
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int (*intr)(struct dma_softc *); /* interrupt ! */
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int (*setup)(struct dma_softc *, caddr_t *, size_t *, int, size_t *);
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void (*go)(struct dma_softc *);
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#endif
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};
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#define DMACSR(sc) (sc->sc_regs->csr)
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#define DMADDR(sc) (sc->sc_regs->addr)
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#define DMACNT(sc) (sc->sc_regs->bcnt)
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/* DMA engine functions */
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#define DMA_ENINTR(r) (((r)->enintr)(r))
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#define DMA_ISINTR(r) (((r)->isintr)(r))
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#define DMA_RESET(r) (((r)->reset)(r))
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#define DMA_INTR(r) (((r)->intr)(r))
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#define DMA_ISACTIVE(r) ((r)->sc_active)
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#define DMA_SETUP(a, b, c, d, e) (((a)->setup)(a, b, c, d, e))
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#define DMA_GO(r) (((r)->go)(r))
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void dmaattach __P((struct device *, struct device *, void *));
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void dma_print_rev __P((struct dma_softc *));
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void dma_reset __P((struct dma_softc *));
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void dma_enintr __P((struct dma_softc *));
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int dma_isintr __P((struct dma_softc *));
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int dma_setup __P((struct dma_softc *, caddr_t *, size_t *, int, size_t *));
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void dma_go __P((struct dma_softc *));
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int espdmaintr __P((struct dma_softc *));
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File diff suppressed because it is too large
Load Diff
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@ -1,4 +1,4 @@
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# $NetBSD: files.sun3x,v 1.14 1997/03/17 19:46:53 gwr Exp $
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# $NetBSD: files.sun3x,v 1.15 1997/03/20 16:01:36 gwr Exp $
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#
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# sun3x-specific configuration info
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@ -106,7 +106,7 @@ device iommu
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attach iommu at obio
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file arch/sun3x/sun3x/iommu.c iommu
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device esp: scsi
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device esp: scsi, ncr53c9x
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attach esp at obio
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file arch/sun3x/dev/esp.c esp
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file arch/sun3x/dev/dma.c esp
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@ -1,4 +1,4 @@
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/* $NetBSD: dma.c,v 1.3 1997/03/15 18:11:00 is Exp $ */
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/* $NetBSD: dma.c,v 1.4 1997/03/20 16:01:38 gwr Exp $ */
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/*
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* Copyright (c) 1994 Paul Kranenburg. All rights reserved.
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@ -48,33 +48,15 @@
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#include <scsi/scsi_all.h>
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#include <scsi/scsiconf.h>
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#include <dev/ic/ncr53c9xreg.h>
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#include <dev/ic/ncr53c9xvar.h>
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#include <sun3x/dev/dmareg.h>
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#include <sun3x/dev/dmavar.h>
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#include <sun3x/dev/espreg.h>
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#include <sun3x/dev/espvar.h>
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void dmaattach __P((struct device *, struct device *, void *));
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void dma_reset __P((struct dma_softc *));
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void dma_enintr __P((struct dma_softc *));
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int dma_isintr __P((struct dma_softc *));
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int espdmaintr __P((struct dma_softc *));
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int dma_setup __P((struct dma_softc *, caddr_t *, size_t *,
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int, size_t *));
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void dma_go __P((struct dma_softc *));
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#if 0
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struct cfattach dma_ca = {
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sizeof(struct dma_softc), dmamatch, dmaattach
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};
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struct cfdriver dma_cd = {
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NULL, "dma", DV_DULL
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};
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#endif /* 0 */
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/*
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* Pseudo-attach function. Called from the esp driver during its
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* attach function.
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* attach function. This needs to be silent.
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*/
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void
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dmaattach(parent, self, aux)
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@ -99,8 +81,25 @@ dmaattach(parent, self, aux)
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* Sun3x works ok (so far) without it.
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*/
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printf(": rev ");
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sc->sc_rev = sc->sc_regs->csr & D_DEV_ID;
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#if 0
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/* indirect functions */
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sc->intr = espdmaintr;
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sc->enintr = dma_enintr;
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sc->isintr = dma_isintr;
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sc->reset = dma_reset;
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sc->setup = dma_setup;
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sc->go = dma_go;
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#endif
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}
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void
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dma_print_rev(sc)
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struct dma_softc *sc;
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{
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printf("espdma: rev ");
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switch (sc->sc_rev) {
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case DMAREV_0:
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printf("0");
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@ -121,16 +120,9 @@ dmaattach(parent, self, aux)
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printf("unknown (0x%x)", sc->sc_rev);
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}
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printf("\n");
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/* indirect functions */
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sc->intr = espdmaintr;
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sc->enintr = dma_enintr;
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sc->isintr = dma_isintr;
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sc->reset = dma_reset;
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sc->setup = dma_setup;
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sc->go = dma_go;
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}
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#define DMAWAIT(SC, COND, MSG, DONTPANIC) do if (COND) { \
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int count = 500000; \
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while ((COND) && --count > 0) DELAY(1); \
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@ -178,8 +170,6 @@ dma_reset(sc)
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/*DMAWAIT1(sc); why was this here? */
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DMACSR(sc) &= ~D_RESET; /* de-assert reset line */
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DMACSR(sc) |= D_INT_EN; /* enable interrupts */
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if (sc->sc_rev > DMAREV_1) /* XXX - needed in 3x? */
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DMACSR(sc) |= D_FASTER;
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sc->sc_active = 0; /* and of course we aren't */
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}
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@ -223,7 +213,7 @@ dma_setup(sc, addr, len, datain, dmasize)
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sc->sc_dmaaddr = addr;
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sc->sc_dmalen = len;
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ESP_DMA(("%s: start %d@%p,%d\n", sc->sc_dev.dv_xname,
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NCR_DMA(("%s: start %d@%p,%d\n", sc->sc_dev.dv_xname,
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*sc->sc_dmalen, *sc->sc_dmaaddr, datain ? 1 : 0));
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/*
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@ -234,7 +224,7 @@ dma_setup(sc, addr, len, datain, dmasize)
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*dmasize = sc->sc_dmasize =
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||||
min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr));
|
||||
|
||||
ESP_DMA(("dma_setup: dmasize = %d\n", sc->sc_dmasize));
|
||||
NCR_DMA(("dma_setup: dmasize = %d\n", sc->sc_dmasize));
|
||||
|
||||
/* Program the DMA address */
|
||||
if (sc->sc_dmasize) {
|
||||
|
|
@ -243,7 +233,7 @@ dma_setup(sc, addr, len, datain, dmasize)
|
|||
*/
|
||||
sc->sc_dvmaaddr = *sc->sc_dmaaddr;
|
||||
sc->sc_dvmakaddr = dvma_mapin(sc->sc_dvmaaddr,
|
||||
sc->sc_dmasize, 0);
|
||||
sc->sc_dmasize, 0);
|
||||
if (sc->sc_dvmakaddr == NULL)
|
||||
panic("dma: cannot allocate DVMA address");
|
||||
sc->sc_dmasaddr = dvma_kvtopa(sc->sc_dvmakaddr, BUS_OBIO);
|
||||
|
|
@ -292,14 +282,15 @@ int
|
|||
espdmaintr(sc)
|
||||
struct dma_softc *sc;
|
||||
{
|
||||
struct ncr53c9x_softc *nsc = sc->sc_esp;
|
||||
char bits[64];
|
||||
int trans, resid;
|
||||
u_long csr;
|
||||
csr = DMACSR(sc);
|
||||
|
||||
ESP_DMA(("%s: intr: addr %x, csr %s\n", sc->sc_dev.dv_xname,
|
||||
DMADDR(sc), bitmask_snprintf(csr, DMACSRBITS, bits,
|
||||
sizeof(bits))));
|
||||
NCR_DMA(("%s: intr: addr %x, csr %s\n",
|
||||
sc->sc_dev.dv_xname, DMADDR(sc),
|
||||
bitmask_snprintf(csr, DMACSRBITS, bits, sizeof(bits))));
|
||||
|
||||
if (csr & D_ERR_PEND) {
|
||||
DMACSR(sc) &= ~D_EN_DMA; /* Stop DMA */
|
||||
|
|
@ -321,11 +312,11 @@ espdmaintr(sc)
|
|||
|
||||
if (sc->sc_dmasize == 0) {
|
||||
/* A "Transfer Pad" operation completed */
|
||||
ESP_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n",
|
||||
ESP_READ_REG(sc->sc_esp, ESP_TCL) |
|
||||
(ESP_READ_REG(sc->sc_esp, ESP_TCM) << 8),
|
||||
ESP_READ_REG(sc->sc_esp, ESP_TCL),
|
||||
ESP_READ_REG(sc->sc_esp, ESP_TCM)));
|
||||
NCR_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n",
|
||||
NCR_READ_REG(nsc, NCR_TCL) |
|
||||
(NCR_READ_REG(nsc, NCR_TCM) << 8),
|
||||
NCR_READ_REG(nsc, NCR_TCL),
|
||||
NCR_READ_REG(nsc, NCR_TCM)));
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -337,24 +328,24 @@ espdmaintr(sc)
|
|||
* bytes are clocked into the FIFO.
|
||||
*/
|
||||
if (!(csr & D_WRITE) &&
|
||||
(resid = (ESP_READ_REG(sc->sc_esp, ESP_FFLAG) & ESPFIFO_FF)) != 0) {
|
||||
ESP_DMA(("dmaintr: empty esp FIFO of %d ", resid));
|
||||
ESPCMD(sc->sc_esp, ESPCMD_FLUSH);
|
||||
(resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) {
|
||||
NCR_DMA(("dmaintr: empty esp FIFO of %d ", resid));
|
||||
NCRCMD(nsc, NCRCMD_FLUSH);
|
||||
}
|
||||
|
||||
if ((sc->sc_esp->sc_espstat & ESPSTAT_TC) == 0) {
|
||||
if ((nsc->sc_espstat & NCRSTAT_TC) == 0) {
|
||||
/*
|
||||
* `Terminal count' is off, so read the residue
|
||||
* out of the ESP counter registers.
|
||||
*/
|
||||
resid += ( ESP_READ_REG(sc->sc_esp, ESP_TCL) |
|
||||
(ESP_READ_REG(sc->sc_esp, ESP_TCM) << 8) |
|
||||
((sc->sc_esp->sc_cfg2 & ESPCFG2_FE)
|
||||
? (ESP_READ_REG(sc->sc_esp, ESP_TCH) << 16)
|
||||
resid += (NCR_READ_REG(nsc, NCR_TCL) |
|
||||
(NCR_READ_REG(nsc, NCR_TCM) << 8) |
|
||||
((nsc->sc_cfg2 & NCRCFG2_FE)
|
||||
? (NCR_READ_REG(nsc, NCR_TCH) << 16)
|
||||
: 0));
|
||||
|
||||
if (resid == 0 && sc->sc_dmasize == 65536 &&
|
||||
(sc->sc_esp->sc_cfg2 & ESPCFG2_FE) == 0)
|
||||
(nsc->sc_cfg2 & NCRCFG2_FE) == 0)
|
||||
/* A transfer of 64K is encoded as `TCL=TCM=0' */
|
||||
resid = 65536;
|
||||
}
|
||||
|
|
@ -366,11 +357,11 @@ espdmaintr(sc)
|
|||
trans = sc->sc_dmasize;
|
||||
}
|
||||
|
||||
ESP_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n",
|
||||
ESP_READ_REG(sc->sc_esp, ESP_TCL),
|
||||
ESP_READ_REG(sc->sc_esp, ESP_TCM),
|
||||
(sc->sc_esp->sc_cfg2 & ESPCFG2_FE)
|
||||
? ESP_READ_REG(sc->sc_esp, ESP_TCH) : 0,
|
||||
NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n",
|
||||
NCR_READ_REG(nsc, NCR_TCL),
|
||||
NCR_READ_REG(nsc, NCR_TCM),
|
||||
(nsc->sc_cfg2 & NCRCFG2_FE)
|
||||
? NCR_READ_REG(nsc, NCR_TCH) : 0,
|
||||
trans, resid));
|
||||
|
||||
#ifdef SUN3X_470_EVENTUALLY
|
||||
|
|
@ -386,7 +377,7 @@ espdmaintr(sc)
|
|||
|
||||
#if 0 /* this is not normal operation just yet */
|
||||
if (*sc->sc_dmalen == 0 ||
|
||||
sc->sc_esp->sc_phase != sc->sc_esp->sc_prevphase)
|
||||
nsc->sc_phase != nsc->sc_prevphase)
|
||||
return 0;
|
||||
|
||||
/* and again */
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: dmavar.h,v 1.2 1997/03/15 18:11:02 is Exp $ */
|
||||
/* $NetBSD: dmavar.h,v 1.3 1997/03/20 16:01:39 gwr Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1994 Peter Galbavy. All rights reserved.
|
||||
|
|
@ -30,7 +30,7 @@
|
|||
|
||||
struct dma_softc {
|
||||
struct device sc_dev; /* us as a device */
|
||||
struct esp_softc *sc_esp; /* my scsi */
|
||||
struct ncr53c9x_softc *sc_esp; /* my scsi */
|
||||
struct dma_regs *sc_regs; /* the registers */
|
||||
int sc_active; /* DMA active ? */
|
||||
u_int sc_rev; /* revision */
|
||||
|
|
@ -41,25 +41,27 @@ struct dma_softc {
|
|||
size_t sc_dmasize;
|
||||
caddr_t *sc_dmaaddr;
|
||||
size_t *sc_dmalen;
|
||||
#if 0
|
||||
void (*reset)(struct dma_softc *); /* reset routine */
|
||||
void (*enintr)(struct dma_softc *); /* enable interrupts */
|
||||
int (*isintr)(struct dma_softc *); /* interrupt ? */
|
||||
int (*intr)(struct dma_softc *); /* interrupt ! */
|
||||
int (*setup)(struct dma_softc *, caddr_t *, size_t *, int, size_t *);
|
||||
void (*go)(struct dma_softc *);
|
||||
#endif
|
||||
};
|
||||
|
||||
#define DMACSR(sc) (sc->sc_regs->csr)
|
||||
#define DMADDR(sc) (sc->sc_regs->addr)
|
||||
#define DMACNT(sc) (sc->sc_regs->bcnt)
|
||||
|
||||
/* DMA engine functions */
|
||||
#define DMA_ENINTR(r) (((r)->enintr)(r))
|
||||
#define DMA_ISINTR(r) (((r)->isintr)(r))
|
||||
#define DMA_RESET(r) (((r)->reset)(r))
|
||||
#define DMA_INTR(r) (((r)->intr)(r))
|
||||
#define DMA_ISACTIVE(r) ((r)->sc_active)
|
||||
#define DMA_SETUP(a, b, c, d, e) (((a)->setup)(a, b, c, d, e))
|
||||
#define DMA_GO(r) (((r)->go)(r))
|
||||
|
||||
void dmaattach __P((struct device *, struct device *, void *));
|
||||
void dma_print_rev __P((struct dma_softc *));
|
||||
|
||||
void dma_reset __P((struct dma_softc *));
|
||||
void dma_enintr __P((struct dma_softc *));
|
||||
int dma_isintr __P((struct dma_softc *));
|
||||
int dma_setup __P((struct dma_softc *, caddr_t *, size_t *, int, size_t *));
|
||||
void dma_go __P((struct dma_softc *));
|
||||
|
||||
int espdmaintr __P((struct dma_softc *));
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,148 +0,0 @@
|
|||
/* $NetBSD: espreg.h,v 1.2 1997/03/15 18:11:04 is Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1994 Peter Galbavy. All rights reserved.
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Peter Galbavy.
|
||||
* 4. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Register addresses, relative to some base address
|
||||
*/
|
||||
|
||||
#define ESP_TCL 0x00 /* RW - Transfer Count Low */
|
||||
#define ESP_TCM 0x01 /* RW - Transfer Count Mid */
|
||||
#define ESP_TCH 0x0e /* RW - Transfer Count High */
|
||||
/* NOT on 53C90 */
|
||||
|
||||
#define ESP_FIFO 0x02 /* RW - FIFO data */
|
||||
|
||||
#define ESP_CMD 0x03 /* RW - Command (2 deep) */
|
||||
#define ESPCMD_DMA 0x80 /* DMA Bit */
|
||||
#define ESPCMD_NOP 0x00 /* No Operation */
|
||||
#define ESPCMD_FLUSH 0x01 /* Flush FIFO */
|
||||
#define ESPCMD_RSTCHIP 0x02 /* Reset Chip */
|
||||
#define ESPCMD_RSTSCSI 0x03 /* Reset SCSI Bus */
|
||||
#define ESPCMD_RESEL 0x40 /* Reselect Sequence */
|
||||
#define ESPCMD_SELNATN 0x41 /* Select without ATN */
|
||||
#define ESPCMD_SELATN 0x42 /* Select with ATN */
|
||||
#define ESPCMD_SELATNS 0x43 /* Select with ATN & Stop */
|
||||
#define ESPCMD_ENSEL 0x44 /* Enable (Re)Selection */
|
||||
#define ESPCMD_DISSEL 0x45 /* Disable (Re)Selection */
|
||||
#define ESPCMD_SELATN3 0x46 /* Select with ATN3 */
|
||||
#define ESPCMD_RESEL3 0x47 /* Reselect3 Sequence */
|
||||
#define ESPCMD_SNDMSG 0x20 /* Send Message */
|
||||
#define ESPCMD_SNDSTAT 0x21 /* Send Status */
|
||||
#define ESPCMD_SNDDATA 0x22 /* Send Data */
|
||||
#define ESPCMD_DISCSEQ 0x23 /* Disconnect Sequence */
|
||||
#define ESPCMD_TERMSEQ 0x24 /* Terminate Sequence */
|
||||
#define ESPCMD_TCCS 0x25 /* Target Command Comp Seq */
|
||||
#define ESPCMD_DISC 0x27 /* Disconnect */
|
||||
#define ESPCMD_RECMSG 0x28 /* Receive Message */
|
||||
#define ESPCMD_RECCMD 0x29 /* Receive Command */
|
||||
#define ESPCMD_RECDATA 0x2a /* Receive Data */
|
||||
#define ESPCMD_RECCSEQ 0x2b /* Receive Command Sequence*/
|
||||
#define ESPCMD_ABORT 0x04 /* Target Abort DMA */
|
||||
#define ESPCMD_TRANS 0x10 /* Transfer Information */
|
||||
#define ESPCMD_ICCS 0x11 /* Initiator Cmd Comp Seq */
|
||||
#define ESPCMD_MSGOK 0x12 /* Message Accepted */
|
||||
#define ESPCMD_TRPAD 0x18 /* Transfer Pad */
|
||||
#define ESPCMD_SETATN 0x1a /* Set ATN */
|
||||
#define ESPCMD_RSTATN 0x1b /* Reset ATN */
|
||||
|
||||
#define ESP_STAT 0x04 /* RO - Status */
|
||||
#define ESPSTAT_INT 0x80 /* Interrupt */
|
||||
#define ESPSTAT_GE 0x40 /* Gross Error */
|
||||
#define ESPSTAT_PE 0x20 /* Parity Error */
|
||||
#define ESPSTAT_TC 0x10 /* Terminal Count */
|
||||
#define ESPSTAT_VGC 0x08 /* Valid Group Code */
|
||||
#define ESPSTAT_PHASE 0x07 /* Phase bits */
|
||||
|
||||
#define ESP_SELID 0x04 /* WO - Select/Reselect Bus ID */
|
||||
|
||||
#define ESP_INTR 0x05 /* RO - Interrupt */
|
||||
#define ESPINTR_SBR 0x80 /* SCSI Bus Reset */
|
||||
#define ESPINTR_ILL 0x40 /* Illegal Command */
|
||||
#define ESPINTR_DIS 0x20 /* Disconnect */
|
||||
#define ESPINTR_BS 0x10 /* Bus Service */
|
||||
#define ESPINTR_FC 0x08 /* Function Complete */
|
||||
#define ESPINTR_RESEL 0x04 /* Reselected */
|
||||
#define ESPINTR_SELATN 0x02 /* Select with ATN */
|
||||
#define ESPINTR_SEL 0x01 /* Selected */
|
||||
|
||||
#define ESP_TIMEOUT 0x05 /* WO - Select/Reselect Timeout */
|
||||
|
||||
#define ESP_STEP 0x06 /* RO - Sequence Step */
|
||||
#define ESPSTEP_MASK 0x07 /* the last 3 bits */
|
||||
#define ESPSTEP_DONE 0x04 /* command went out */
|
||||
|
||||
#define ESP_SYNCTP 0x06 /* WO - Synch Transfer Period */
|
||||
/* Default 5 (53C9X) */
|
||||
|
||||
#define ESP_FFLAG 0x07 /* RO - FIFO Flags */
|
||||
#define ESPFIFO_SS 0xe0 /* Sequence Step (Dup) */
|
||||
#define ESPFIFO_FF 0x1f /* Bytes in FIFO */
|
||||
|
||||
#define ESP_SYNCOFF 0x07 /* WO - Synch Offset */
|
||||
/* 0 = ASYNC */
|
||||
/* 1 - 15 = SYNC bytes */
|
||||
|
||||
#define ESP_CFG1 0x08 /* RW - Configuration #1 */
|
||||
#define ESPCFG1_SLOW 0x80 /* Slow Cable Mode */
|
||||
#define ESPCFG1_SRR 0x40 /* SCSI Reset Rep Int Dis */
|
||||
#define ESPCFG1_PTEST 0x20 /* Parity Test Mod */
|
||||
#define ESPCFG1_PARENB 0x10 /* Enable Parity Check */
|
||||
#define ESPCFG1_CTEST 0x08 /* Enable Chip Test */
|
||||
#define ESPCFG1_BUSID 0x07 /* Bus ID */
|
||||
|
||||
#define ESP_CCF 0x09 /* WO - Clock Conversion Factor */
|
||||
/* 0 = 35.01 - 40Mhz */
|
||||
/* NEVER SET TO 1 */
|
||||
/* 2 = 10Mhz */
|
||||
/* 3 = 10.01 - 15Mhz */
|
||||
/* 4 = 15.01 - 20Mhz */
|
||||
/* 5 = 20.01 - 25Mhz */
|
||||
/* 6 = 25.01 - 30Mhz */
|
||||
/* 7 = 30.01 - 35Mhz */
|
||||
|
||||
#define ESP_TEST 0x0a /* WO - Test (Chip Test Only) */
|
||||
|
||||
#define ESP_CFG2 0x0b /* RW - Configuration #2 */
|
||||
#define ESPCFG2_RSVD 0xa0 /* reserved */
|
||||
#define ESPCFG2_FE 0x40 /* Features Enable */
|
||||
#define ESPCFG2_DREQ 0x10 /* DREQ High Impedance */
|
||||
#define ESPCFG2_SCSI2 0x08 /* SCSI-2 Enable */
|
||||
#define ESPCFG2_BPA 0x04 /* Target Bad Parity Abort */
|
||||
#define ESPCFG2_RPE 0x02 /* Register Parity Error */
|
||||
#define ESPCFG2_DPE 0x01 /* DMA Parity Error */
|
||||
|
||||
/* Config #3 only on 53C9X */
|
||||
#define ESP_CFG3 0x0c /* RW - Configuration #3 */
|
||||
#define ESPCFG3_RSVD 0xe0 /* reserved */
|
||||
#define ESPCFG3_IDM 0x10 /* ID Message Res Check */
|
||||
#define ESPCFG3_QTE 0x08 /* Queue Tag Enable */
|
||||
#define ESPCFG3_CDB 0x04 /* CDB 10-bytes OK */
|
||||
#define ESPCFG3_FSCSI 0x02 /* Fast SCSI */
|
||||
#define ESPCFG3_FCLK 0x01 /* Fast Clock (>25Mhz) */
|
||||
|
|
@ -1,282 +0,0 @@
|
|||
/* $NetBSD: espvar.h,v 1.2 1997/03/15 18:11:05 is Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1994 Peter Galbavy. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Peter Galbavy.
|
||||
* 4. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#define ESP_DEBUG 0
|
||||
|
||||
#define ESP_ABORT_TIMEOUT 2000 /* time to wait for abort */
|
||||
|
||||
#define FREQTOCCF(freq) (((freq + 4) / 5))
|
||||
|
||||
/* esp revisions */
|
||||
#define ESP100 0x01
|
||||
#define ESP100A 0x02
|
||||
#define ESP200 0x03
|
||||
#define NCR53C94 0x04
|
||||
|
||||
/*
|
||||
* ECB. Holds additional information for each SCSI command Comments: We
|
||||
* need a separate scsi command block because we may need to overwrite it
|
||||
* with a request sense command. Basicly, we refrain from fiddling with
|
||||
* the scsi_xfer struct (except do the expected updating of return values).
|
||||
* We'll generally update: xs->{flags,resid,error,sense,status} and
|
||||
* occasionally xs->retries.
|
||||
*/
|
||||
struct esp_ecb {
|
||||
TAILQ_ENTRY(esp_ecb) chain;
|
||||
struct scsi_xfer *xs; /* SCSI xfer ctrl block from above */
|
||||
int flags;
|
||||
#define ECB_ALLOC 0x01
|
||||
#define ECB_NEXUS 0x02
|
||||
#define ECB_SENSE 0x04
|
||||
#define ECB_ABORT 0x40
|
||||
#define ECB_RESET 0x80
|
||||
int timeout;
|
||||
|
||||
struct scsi_generic cmd; /* SCSI command block */
|
||||
int clen;
|
||||
char *daddr; /* Saved data pointer */
|
||||
int dleft; /* Residue */
|
||||
u_char stat; /* SCSI status byte */
|
||||
|
||||
#if ESP_DEBUG > 0
|
||||
char trace[1000];
|
||||
#endif
|
||||
};
|
||||
#if ESP_DEBUG > 0
|
||||
#define ECB_TRACE(ecb, msg, a, b) do { \
|
||||
const char *f = "[" msg "]"; \
|
||||
int n = strlen((ecb)->trace); \
|
||||
if (n < (sizeof((ecb)->trace)-100)) \
|
||||
sprintf((ecb)->trace + n, f, a, b); \
|
||||
} while(0)
|
||||
#else
|
||||
#define ECB_TRACE(ecb, msg, a, b)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Some info about each (possible) target on the SCSI bus. This should
|
||||
* probably have been a "per target+lunit" structure, but we'll leave it at
|
||||
* this for now. Is there a way to reliably hook it up to sc->fordriver??
|
||||
*/
|
||||
struct esp_tinfo {
|
||||
int cmds; /* #commands processed */
|
||||
int dconns; /* #disconnects */
|
||||
int touts; /* #timeouts */
|
||||
int perrs; /* #parity errors */
|
||||
int senses; /* #request sense commands sent */
|
||||
ushort lubusy; /* What local units/subr. are busy? */
|
||||
u_char flags;
|
||||
#define T_NEED_TO_RESET 0x01 /* Should send a BUS_DEV_RESET */
|
||||
#define T_NEGOTIATE 0x02 /* (Re)Negotiate synchronous options */
|
||||
#define T_BUSY 0x04 /* Target is busy, i.e. cmd in progress */
|
||||
#define T_SYNCMODE 0x08 /* sync mode has been negotiated */
|
||||
#define T_SYNCHOFF 0x10 /* .. */
|
||||
#define T_RSELECTOFF 0x20 /* .. */
|
||||
u_char period; /* Period suggestion */
|
||||
u_char offset; /* Offset suggestion */
|
||||
} tinfo_t;
|
||||
|
||||
/* Register a linenumber (for debugging) */
|
||||
#define LOGLINE(p)
|
||||
|
||||
#define ESP_SHOWECBS 0x01
|
||||
#define ESP_SHOWINTS 0x02
|
||||
#define ESP_SHOWCMDS 0x04
|
||||
#define ESP_SHOWMISC 0x08
|
||||
#define ESP_SHOWTRAC 0x10
|
||||
#define ESP_SHOWSTART 0x20
|
||||
#define ESP_SHOWPHASE 0x40
|
||||
#define ESP_SHOWDMA 0x80
|
||||
#define ESP_SHOWCCMDS 0x100
|
||||
#define ESP_SHOWMSGS 0x200
|
||||
|
||||
#ifdef ESP_DEBUG
|
||||
extern int esp_debug;
|
||||
#define ESP_ECBS(str) do {if (esp_debug & ESP_SHOWECBS) printf str;} while (0)
|
||||
#define ESP_MISC(str) do {if (esp_debug & ESP_SHOWMISC) printf str;} while (0)
|
||||
#define ESP_INTS(str) do {if (esp_debug & ESP_SHOWINTS) printf str;} while (0)
|
||||
#define ESP_TRACE(str) do {if (esp_debug & ESP_SHOWTRAC) printf str;} while (0)
|
||||
#define ESP_CMDS(str) do {if (esp_debug & ESP_SHOWCMDS) printf str;} while (0)
|
||||
#define ESP_START(str) do {if (esp_debug & ESP_SHOWSTART) printf str;}while (0)
|
||||
#define ESP_PHASE(str) do {if (esp_debug & ESP_SHOWPHASE) printf str;}while (0)
|
||||
#define ESP_DMA(str) do {if (esp_debug & ESP_SHOWDMA) printf str;}while (0)
|
||||
#define ESP_MSGS(str) do {if (esp_debug & ESP_SHOWMSGS) printf str;}while (0)
|
||||
#else
|
||||
#define ESP_ECBS(str)
|
||||
#define ESP_MISC(str)
|
||||
#define ESP_INTS(str)
|
||||
#define ESP_TRACE(str)
|
||||
#define ESP_CMDS(str)
|
||||
#define ESP_START(str)
|
||||
#define ESP_PHASE(str)
|
||||
#define ESP_DMA(str)
|
||||
#define ESP_MSGS(str)
|
||||
#endif
|
||||
|
||||
#define ESP_MAX_MSG_LEN 8
|
||||
|
||||
struct esp_softc {
|
||||
struct device sc_dev; /* us as a device */
|
||||
struct evcnt sc_intrcnt; /* intr count */
|
||||
struct scsi_link sc_link; /* scsi lint struct */
|
||||
volatile u_char *sc_reg; /* the registers */
|
||||
struct dma_softc *sc_dma; /* pointer to my dma */
|
||||
|
||||
/* register defaults */
|
||||
u_char sc_cfg1; /* Config 1 */
|
||||
u_char sc_cfg2; /* Config 2, not ESP100 */
|
||||
u_char sc_cfg3; /* Config 3, only ESP200 */
|
||||
u_char sc_ccf; /* Clock Conversion */
|
||||
u_char sc_timeout;
|
||||
|
||||
/* register copies, see espreadregs() */
|
||||
u_char sc_espintr;
|
||||
u_char sc_espstat;
|
||||
u_char sc_espstep;
|
||||
u_char sc_espfflags;
|
||||
|
||||
/* Lists of command blocks */
|
||||
TAILQ_HEAD(ecb_list, esp_ecb) free_list,
|
||||
ready_list,
|
||||
nexus_list;
|
||||
|
||||
struct esp_ecb *sc_nexus; /* current command */
|
||||
struct esp_ecb sc_ecb[3*8]; /* three per target */
|
||||
struct esp_tinfo sc_tinfo[8];
|
||||
|
||||
/* Data about the current nexus (updated for every cmd switch) */
|
||||
caddr_t sc_dp; /* Current data pointer */
|
||||
ssize_t sc_dleft; /* Data left to transfer */
|
||||
|
||||
/* Adapter state */
|
||||
int sc_phase; /* Copy of what bus phase we are in */
|
||||
int sc_prevphase; /* Copy of what bus phase we were in */
|
||||
u_char sc_state; /* State applicable to the adapter */
|
||||
u_char sc_flags;
|
||||
u_char sc_selid;
|
||||
u_char sc_lastcmd;
|
||||
|
||||
/* Message stuff */
|
||||
u_char sc_msgpriq; /* One or more messages to send (encoded) */
|
||||
u_char sc_msgout; /* What message is on its way out? */
|
||||
u_char sc_msgoutq; /* What messages have been sent so far? */
|
||||
u_char sc_omess[ESP_MAX_MSG_LEN];
|
||||
caddr_t sc_omp; /* Message pointer (for multibyte messages) */
|
||||
size_t sc_omlen;
|
||||
u_char sc_imess[ESP_MAX_MSG_LEN + 1];
|
||||
caddr_t sc_imp; /* Message pointer (for multibyte messages) */
|
||||
size_t sc_imlen;
|
||||
|
||||
/* hardware stuff */
|
||||
int sc_freq; /* Freq in HZ */
|
||||
int sc_id; /* our scsi id */
|
||||
int sc_rev; /* esp revision */
|
||||
int sc_minsync; /* minimum sync period / 4 */
|
||||
int sc_maxxfer; /* maximum transfer size */
|
||||
};
|
||||
|
||||
/* values for sc_state */
|
||||
#define ESP_IDLE 1 /* waiting for something to do */
|
||||
#define ESP_SELECTING 2 /* SCSI command is arbiting */
|
||||
#define ESP_RESELECTED 3 /* Has been reselected */
|
||||
#define ESP_CONNECTED 4 /* Actively using the SCSI bus */
|
||||
#define ESP_DISCONNECT 5 /* MSG_DISCONNECT received */
|
||||
#define ESP_CMDCOMPLETE 6 /* MSG_CMDCOMPLETE received */
|
||||
#define ESP_CLEANING 7
|
||||
#define ESP_SBR 8 /* Expect a SCSI RST because we commanded it */
|
||||
|
||||
/* values for sc_flags */
|
||||
#define ESP_DROP_MSGI 0x01 /* Discard all msgs (parity err detected) */
|
||||
#define ESP_ABORTING 0x02 /* Bailing out */
|
||||
#define ESP_DOINGDMA 0x04 /* The FIFO data path is active! */
|
||||
#define ESP_SYNCHNEGO 0x08 /* Synch negotiation in progress. */
|
||||
#define ESP_ICCS 0x10 /* Expect status phase results */
|
||||
#define ESP_WAITI 0x20 /* Waiting for non-DMA data to arrive */
|
||||
#define ESP_ATN 0x40 /* ATN asserted */
|
||||
|
||||
/* values for sc_msgout */
|
||||
#define SEND_DEV_RESET 0x01
|
||||
#define SEND_PARITY_ERROR 0x02
|
||||
#define SEND_INIT_DET_ERR 0x04
|
||||
#define SEND_REJECT 0x08
|
||||
#define SEND_IDENTIFY 0x10
|
||||
#define SEND_ABORT 0x20
|
||||
#define SEND_SDTR 0x40
|
||||
#define SEND_WDTR 0x80
|
||||
|
||||
/* SCSI Status codes */
|
||||
#define ST_MASK 0x3e /* bit 0,6,7 is reserved */
|
||||
|
||||
/* phase bits */
|
||||
#define IOI 0x01
|
||||
#define CDI 0x02
|
||||
#define MSGI 0x04
|
||||
|
||||
/* Information transfer phases */
|
||||
#define DATA_OUT_PHASE (0)
|
||||
#define DATA_IN_PHASE (IOI)
|
||||
#define COMMAND_PHASE (CDI)
|
||||
#define STATUS_PHASE (CDI|IOI)
|
||||
#define MESSAGE_OUT_PHASE (MSGI|CDI)
|
||||
#define MESSAGE_IN_PHASE (MSGI|CDI|IOI)
|
||||
|
||||
#define PHASE_MASK (MSGI|CDI|IOI)
|
||||
|
||||
/* Some pseudo phases for getphase()*/
|
||||
#define BUSFREE_PHASE 0x100 /* Re/Selection no longer valid */
|
||||
#define INVALID_PHASE 0x101 /* Re/Selection valid, but no REQ yet */
|
||||
#define PSEUDO_PHASE 0x100 /* "pseudo" bit */
|
||||
|
||||
/*
|
||||
* Macros to read and write the chip's registers.
|
||||
*/
|
||||
#define ESP_READ_REG(sc, reg) \
|
||||
((sc)->sc_reg[(reg) * 4])
|
||||
#define ESP_WRITE_REG(sc, reg, val) \
|
||||
do { \
|
||||
u_char v = (val); \
|
||||
(sc)->sc_reg[(reg) * 4] = v; \
|
||||
} while (0)
|
||||
|
||||
#ifdef ESP_DEBUG
|
||||
#define ESPCMD(sc, cmd) do { \
|
||||
if (esp_debug & ESP_SHOWCCMDS) \
|
||||
printf("<cmd:0x%x>", (unsigned)cmd); \
|
||||
sc->sc_lastcmd = cmd; \
|
||||
ESP_WRITE_REG(sc, ESP_CMD, cmd); \
|
||||
} while (0)
|
||||
#else
|
||||
#define ESPCMD(sc, cmd) ESP_WRITE_REG(sc, ESP_CMD, cmd)
|
||||
#endif
|
||||
|
||||
#define SAME_ESP(sc, bp, ca) \
|
||||
((bp->val[0] == ca->ca_slot && bp->val[1] == ca->ca_offset) || \
|
||||
(bp->val[0] == -1 && bp->val[1] == sc->sc_dev.dv_unit))
|
||||
Loading…
Reference in New Issue