Pull up the following (via patch), requested by msaitoh in ticket #650:
sys/dev/pci/if_wm.c 1.650, 1.652-1.654 sys/dev/pci/if_wmreg.h 1.116-1.117 - Set CTRL_ILOS(Invert loss of signal) bit correctly on 82580 port 1, 2, 3 and newer chips. This change fixes a bug that some fiber, serdes or SFP devices don't detect the link status correctly. - Simplify code by using "struct mii_data *mii" more. No functional change. - MSI-X doesn't use sc->sc_icr variable, so move the code into non-MSI-X part. No functional change intended. - Modify debug printfs a bit. - Rename macro. - Use __BIT() - Fix comment. Add comment. - KNF.
This commit is contained in:
martin
parent
3ba0477766
commit
b6e92bef63
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@ -1,4 +1,4 @@
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/* $NetBSD: if_wm.c,v 1.645.2.3 2020/01/23 10:10:57 martin Exp $ */
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/* $NetBSD: if_wm.c,v 1.645.2.4 2020/01/26 11:13:27 martin Exp $ */
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/*
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* Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
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@ -82,7 +82,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.645.2.3 2020/01/23 10:10:57 martin Exp $");
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__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.645.2.4 2020/01/26 11:13:27 martin Exp $");
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#ifdef _KERNEL_OPT
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#include "opt_net_mpsafe.h"
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@ -2656,10 +2656,11 @@ alloc_retry:
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}
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}
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/* XXX For other than 82580? */
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if (sc->sc_type == WM_T_82580) {
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wm_nvm_read(sc, NVM_OFF_CFG3_PORTA, 1, &nvmword);
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if (nvmword & __BIT(13))
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if ((sc->sc_type >= WM_T_82580) && (sc->sc_type <= WM_T_I211)) {
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wm_nvm_read(sc,
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NVM_OFF_LAN_FUNC_82580(sc->sc_funcid) + NVM_OFF_CFG3_PORTA,
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1, &nvmword);
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if (nvmword & NVM_CFG3_ILOS)
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sc->sc_ctrl |= CTRL_ILOS;
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}
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@ -6047,8 +6048,7 @@ wm_init_locked(struct ifnet *ifp)
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/* Set up the interrupt registers. */
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CSR_WRITE(sc, WMREG_IMC, 0xffffffffU);
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sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 |
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ICR_RXO | ICR_RXT0;
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if (wm_is_using_msix(sc)) {
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uint32_t mask;
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struct wm_queue *wmq;
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@ -6088,8 +6088,11 @@ wm_init_locked(struct ifnet *ifp)
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CSR_WRITE(sc, WMREG_IMS, ICR_LSC);
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break;
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}
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} else
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} else {
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sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 |
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ICR_RXO | ICR_RXT0;
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CSR_WRITE(sc, WMREG_IMS, sc->sc_icr);
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}
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/* Set up the inter-packet gap. */
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CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg);
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@ -9286,7 +9289,7 @@ wm_linkintr_serdes(struct wm_softc *sc, uint32_t icr)
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{
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struct ifnet *ifp = &sc->sc_ethercom.ec_if;
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struct mii_data *mii = &sc->sc_mii;
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struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur;
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struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
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uint32_t pcs_adv, pcs_lpab, reg;
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DPRINTF(WM_DEBUG_LINK, ("%s: %s:\n", device_xname(sc->sc_dev),
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@ -9629,11 +9632,12 @@ wm_linkintr_msix(void *arg)
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uint32_t reg;
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bool has_rxo;
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DPRINTF(WM_DEBUG_LINK,
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("%s: LINK: got link intr\n", device_xname(sc->sc_dev)));
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reg = CSR_READ(sc, WMREG_ICR);
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WM_CORE_LOCK(sc);
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DPRINTF(WM_DEBUG_LINK,
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("%s: LINK: got link intr. ICR = %08x\n",
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device_xname(sc->sc_dev), reg));
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if (sc->sc_core_stopping)
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goto out;
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@ -11411,7 +11415,7 @@ wm_gmii_statchg(struct ifnet *ifp)
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sc->sc_ctrl |= CTRL_RFCE;
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}
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if (sc->sc_mii.mii_media_active & IFM_FDX) {
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if (mii->mii_media_active & IFM_FDX) {
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DPRINTF(WM_DEBUG_LINK,
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("%s: LINK: statchg: FDX\n", ifp->if_xname));
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sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_FDX);
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@ -11426,7 +11430,7 @@ wm_gmii_statchg(struct ifnet *ifp)
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CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? WMREG_OLD_FCRTL
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: WMREG_FCRTL, sc->sc_fcrtl);
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if (sc->sc_type == WM_T_80003) {
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switch (IFM_SUBTYPE(sc->sc_mii.mii_media_active)) {
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switch (IFM_SUBTYPE(mii->mii_media_active)) {
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case IFM_1000_T:
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wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_HD_CTRL,
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KUMCTRLSTA_HD_CTRL_1000_DEFAULT);
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@ -12085,7 +12089,8 @@ wm_tbi_tick(struct wm_softc *sc)
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if ((IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO)
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&& (++sc->sc_tbi_serdes_ticks
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>= sc->sc_tbi_serdes_anegticks)) {
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DPRINTF(WM_DEBUG_LINK, ("EXPIRE\n"));
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DPRINTF(WM_DEBUG_LINK, ("%s: %s: EXPIRE\n",
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device_xname(sc->sc_dev), __func__));
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sc->sc_tbi_serdes_ticks = 0;
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/*
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* Reset the link, and let autonegotiation do
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@ -12192,7 +12197,7 @@ wm_serdes_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
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{
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struct wm_softc *sc = ifp->if_softc;
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struct mii_data *mii = &sc->sc_mii;
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struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur;
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struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
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uint32_t pcs_adv, pcs_lpab, reg;
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ifmr->ifm_status = IFM_AVALID;
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@ -12310,7 +12315,8 @@ wm_serdes_tick(struct wm_softc *sc)
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if ((IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO)
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&& (++sc->sc_tbi_serdes_ticks
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>= sc->sc_tbi_serdes_anegticks)) {
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DPRINTF(WM_DEBUG_LINK, ("EXPIRE\n"));
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DPRINTF(WM_DEBUG_LINK, ("%s: %s: EXPIRE\n",
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device_xname(sc->sc_dev), __func__));
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sc->sc_tbi_serdes_ticks = 0;
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/* XXX */
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wm_serdes_mediachange(ifp);
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@ -12372,6 +12378,7 @@ wm_sfp_get_media_type(struct wm_softc *sc)
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}
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if (rv != 0)
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goto out;
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switch (val) {
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case SFF_SFP_ID_SFF:
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aprint_normal_dev(sc->sc_dev,
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@ -12387,9 +12394,8 @@ wm_sfp_get_media_type(struct wm_softc *sc)
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}
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rv = wm_sfp_read_data_byte(sc, SFF_SFP_ETH_FLAGS_OFF, &val);
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if (rv != 0) {
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if (rv != 0)
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goto out;
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}
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if ((val & (SFF_SFP_ETH_FLAGS_1000SX | SFF_SFP_ETH_FLAGS_1000LX)) != 0)
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mediatype = WM_MEDIATYPE_SERDES;
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@ -15461,7 +15467,7 @@ wm_hv_phy_workarounds_ich8lan(struct wm_softc *sc)
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if ((rv = wm_set_mdio_slow_mode_hv(sc)) != 0)
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return rv;
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child = LIST_FIRST(&sc->sc_mii.mii_phys);
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child = LIST_FIRST(&mii->mii_phys);
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if (child != NULL)
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phyrev = child->mii_mpd_rev;
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@ -15496,8 +15502,7 @@ wm_hv_phy_workarounds_ich8lan(struct wm_softc *sc)
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*/
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if ((child != NULL) && (phyrev < 2)) {
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PHY_RESET(child);
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rv = sc->sc_mii.mii_writereg(dev, 2, MII_BMCR,
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0x3140);
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rv = mii->mii_writereg(dev, 2, MII_BMCR, 0x3140);
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if (rv != 0)
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return rv;
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: if_wmreg.h,v 1.115 2019/07/23 09:37:08 msaitoh Exp $ */
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/* $NetBSD: if_wmreg.h,v 1.115.2.1 2020/01/26 11:13:28 martin Exp $ */
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/*
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* Copyright (c) 2001 Wasabi Systems, Inc.
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@ -435,7 +435,7 @@ struct livengood_tcpip_ctxdesc {
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#define CTRL_D_UD_EN (1U << 13) /* Dock/Undock enable */
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#define CTRL_D_UD_POL (1U << 14) /* Defined polarity of Dock/Undock indication in SDP[0] */
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#define CTRL_F_PHY_R (1U << 15) /* Reset both PHY ports, through PHYRST_N pin */
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#define CTRL_EXT_LINK_EN (1U << 16) /* enable link status from external LINK_0 and LINK_1 pins */
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#define CTRL_EXTLINK_EN (1U << 16) /* enable link status from external LINK_0 and LINK_1 pins */
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#define CTRL_LANPHYPC_OVERRIDE (1U << 16) /* SW control of LANPHYPC */
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#define CTRL_LANPHYPC_VALUE (1U << 17) /* SW value of LANPHYPC */
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#define CTRL_SWDPINS_SHIFT 18
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@ -639,6 +639,14 @@ struct livengood_tcpip_ctxdesc {
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#define KUMCTRLSTA_OPMODE_MASK 0x000c
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#define KUMCTRLSTA_OPMODE_INBAND_MDIO 0x0004
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#define WMREG_CONNSW 0x0034 /* Copper/Fiber Switch Control (>= 82575) */
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#define CONNSW_AUTOSENSE_EN __BIT(0) /* Auto Sense Enable */
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#define CONNSW_AUTOSENSE_CONF __BIT(1) /* Auto Sense Config Mode */
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#define CONNSW_ENRGSRC __BIT(2) /* SerDes Energy Detect Src */
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#define CONNSW_SERDESD __BIT(9) /* SerDes Signal Detect Ind. */
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#define CONNSW_PHYSD __BIT(10) /* PHY Signal Detect Ind. */
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#define CONNSW_PHY_PDN __BIT(11) /* Internal PHY in powerdown */
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#define WMREG_VET 0x0038 /* VLAN Ethertype */
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#define WMREG_MDPHYA 0x003c /* PHY address - RW */
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@ -1153,13 +1161,23 @@ struct livengood_tcpip_ctxdesc {
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#define PCS_CFG_PCS_EN __BIT(3)
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#define WMREG_PCS_LCTL 0x4208 /* PCS Link Control */
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#define PCS_LCTL_FSV_1000 __BIT(2) /* AN Timeout Enable */
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#define PCS_LCTL_FDV_FULL __BIT(3) /* AN Timeout Enable */
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#define PCS_LCTL_FSD __BIT(4) /* AN Timeout Enable */
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#define PCS_LCTL_FORCE_FC __BIT(7) /* AN Timeout Enable */
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#define PCS_LCTL_AN_ENABLE __BIT(16) /* AN Timeout Enable */
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#define PCS_LCTL_AN_RESTART __BIT(17) /* AN Timeout Enable */
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#define PCS_LCTL_AN_TIMEOUT __BIT(18) /* AN Timeout Enable */
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#define PCS_LCTL_FLV_LINK_UP __BIT(0) /* Forced Link Value */
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#define PCS_LCTL_FSV_MASK __BITS(2, 1) /* Forced Speed Value */
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#define PCS_LCTL_FSV_10 0 /* 10Mbps */
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#define PCS_LCTL_FSV_100 __BIT(1) /* 100Mbps */
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#define PCS_LCTL_FSV_1000 __BIT(2) /* 1Gpbs */
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#define PCS_LCTL_FDV_FULL __BIT(3) /* Force Duplex Value */
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#define PCS_LCTL_FSD __BIT(4) /* Force Speed and Duplex */
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#define PCS_LCTL_FORCE_LINK __BIT(5) /* Force Link */
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#define PCS_LCTL_LINK_LATCH_LOW __BIT(6) /* Link Latch Low */
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#define PCS_LCTL_FORCE_FC __BIT(7) /* Force Flow Control */
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#define PCS_LCTL_AN_ENABLE __BIT(16) /* AN enable */
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#define PCS_LCTL_AN_RESTART __BIT(17) /* AN restart */
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#define PCS_LCTL_AN_TIMEOUT __BIT(18) /* AN Timeout Enable */
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#define PCS_LCTL_AN_SGMII_BYP __BIT(19) /* AN SGMII Bypass */
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#define PCS_LCTL_AN_SGMII_TRIG __BIT(20) /* AN SGMII Trigger */
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#define PCS_LCTL_FAST_LINKTIMER __BIT(24) /* Fast Link Timer */
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#define PCS_LCTL_LINK_OK_FIX_EN __BIT(25) /* Link OK Fix Enable */
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#define WMREG_PCS_LSTS 0x420c /* PCS Link Status */
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#define PCS_LSTS_LINKOK __BIT(0)
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@ -1172,6 +1190,7 @@ struct livengood_tcpip_ctxdesc {
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#define WMREG_PCS_ANADV 0x4218 /* AN Advertsement */
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#define WMREG_PCS_LPAB 0x421c /* Link Partnet Ability */
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#define WMREG_PCS_NPTX 0x4220 /* Next Page Transmit */
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#define WMREG_RXCSUM 0x5000 /* Receive Checksum register */
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#define RXCSUM_PCSS 0x000000ff /* Packet Checksum Start */
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@ -1424,7 +1443,7 @@ struct livengood_tcpip_ctxdesc {
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#define NVM_CFG1_LSSID (1U << 1)
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#define NVM_CFG1_PME_CLOCK (1U << 2)
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#define NVM_CFG1_PM (1U << 3)
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#define NVM_CFG1_ILOS (1U << 4)
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#define NVM_CFG1_ILOS (1U << 4) /* Invert loss of signal */
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#define NVM_CFG1_SWDPIO_SHIFT 5
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#define NVM_CFG1_SWDPIO_MASK (0xf << NVM_CFG1_SWDPIO_SHIFT)
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#define NVM_CFG1_IPS1 (1U << 8)
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@ -1468,9 +1487,10 @@ struct livengood_tcpip_ctxdesc {
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#define NVM_3GIO_3_ASPM_MASK (0x3 << 2) /* Active State PM Support */
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#define NVM_CFG3_APME (1U << 10)
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#define NVM_CFG3_PORTA_EXT_MDIO (1U << 2) /* External MDIO Interface */
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#define NVM_CFG3_PORTA_COM_MDIO (1U << 3) /* MDIO Interface is shared */
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#define NVM_CFG3_PORTA_EXT_MDIO __BIT(2) /* External MDIO Interface */
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#define NVM_CFG3_PORTA_COM_MDIO __BIT(3) /* MDIO Interface is shared */
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#define NVM_CFG3_APME __BIT(10) /* APM Enable */
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#define NVM_CFG3_ILOS __BIT(13) /* Invert loss of signal */
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#define NVM_OFF_MACADDR_82571(x) (3 * (x))
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