Add driver for Exynos PWM timer.
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jmcneill
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bfa0614efd
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adc41efb5b
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/* $NetBSD: exynos_pwm.c,v 1.1 2018/07/04 23:06:54 jmcneill Exp $ */
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/*-
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* Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(1, "$NetBSD: exynos_pwm.c,v 1.1 2018/07/04 23:06:54 jmcneill Exp $");
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/device.h>
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#include <sys/intr.h>
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#include <sys/systm.h>
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#include <sys/time.h>
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#include <dev/pwm/pwmvar.h>
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#include <dev/fdt/fdtvar.h>
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#define TCFG0 0x00
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#define TCFG1 0x04
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#define TCON 0x08
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#define _TCON_OFF(n) ((n) == 0 ? 0 : (((n) + 1) * 4))
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#define TCON_START(n) __BIT(_TCON_OFF(n) + 0)
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#define TCON_UPDATE(n) __BIT(_TCON_OFF(n) + 1)
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#define TCON_OUTINV(n) __BIT(_TCON_OFF(n) + 2)
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#define TCON_AUTO_RELOAD(n) __BIT(_TCON_OFF(n) + 3)
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#define TCON_DEADZONE_EN(n) __BIT(_TCON_OFF(n) + 4)
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#define TCNTB(n) (0x0c + (n) * 12)
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#define TCMPB(n) (0x10 + (n) * 12)
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#define TCNTO(n) (0x14 + (n) * 12)
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#define TINT_CSTAT 0x44
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#define PWM_NTIMERS 5
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static const char * const compatible[] = {
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"samsung,exynos4210-pwm",
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NULL
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};
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struct exynos_pwm_softc;
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struct exynos_pwm_timer {
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u_int timer_index;
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struct pwm_controller timer_pwm;
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};
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struct exynos_pwm_softc {
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device_t sc_dev;
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bus_space_tag_t sc_bst;
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bus_space_handle_t sc_bsh;
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struct exynos_pwm_timer sc_timer[PWM_NTIMERS];
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u_int sc_timermask;
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u_int sc_clkfreq;
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};
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#define PWM_READ(sc, reg) \
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bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
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#define PWM_WRITE(sc, reg, val) \
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bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
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static int
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exynos_pwm_enable(pwm_tag_t pwm, bool enable)
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{
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struct exynos_pwm_timer * const timer = pwm->pwm_priv;
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struct exynos_pwm_softc * const sc = device_private(pwm->pwm_dev);
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uint32_t tcon;
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if (enable) {
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tcon = PWM_READ(sc, TCON);
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tcon &= ~TCON_START(timer->timer_index);
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tcon |= TCON_UPDATE(timer->timer_index);
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PWM_WRITE(sc, TCON, tcon);
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tcon &= ~TCON_UPDATE(timer->timer_index);
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tcon |= TCON_START(timer->timer_index);
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tcon |= TCON_AUTO_RELOAD(timer->timer_index);
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PWM_WRITE(sc, TCON, tcon);
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} else {
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tcon = PWM_READ(sc, TCON);
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tcon &= ~TCON_AUTO_RELOAD(timer->timer_index);
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PWM_WRITE(sc, TCON, tcon);
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}
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return 0;
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}
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static int
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exynos_pwm_get_config(pwm_tag_t pwm, struct pwm_config *conf)
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{
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struct exynos_pwm_timer * const timer = pwm->pwm_priv;
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struct exynos_pwm_softc * const sc = device_private(pwm->pwm_dev);
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uint32_t tcon, tcntb, tcmpb;
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tcon = PWM_READ(sc, TCON);
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tcntb = PWM_READ(sc, TCNTB(timer->timer_index));
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tcmpb = PWM_READ(sc, TCMPB(timer->timer_index));
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conf->polarity = (tcon & TCON_OUTINV(timer->timer_index)) ? PWM_ACTIVE_HIGH : PWM_ACTIVE_LOW;
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conf->period = (u_int)(((uint64_t)tcntb * 1000000000) / sc->sc_clkfreq);
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conf->duty_cycle = (u_int)(((uint64_t)tcmpb * 1000000000) / sc->sc_clkfreq);
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return 0;
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}
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static int
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exynos_pwm_set_config(pwm_tag_t pwm, const struct pwm_config *conf)
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{
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struct exynos_pwm_timer * const timer = pwm->pwm_priv;
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struct exynos_pwm_softc * const sc = device_private(pwm->pwm_dev);
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uint32_t tcon, tcntb, tcmpb;
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tcon = PWM_READ(sc, TCON);
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if (conf->polarity == PWM_ACTIVE_HIGH)
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tcon |= TCON_OUTINV(timer->timer_index);
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else
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tcon &= ~TCON_OUTINV(timer->timer_index);
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PWM_WRITE(sc, TCON, tcon);
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tcntb = conf->period / (1000000000 / sc->sc_clkfreq);
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tcmpb = conf->duty_cycle / (1000000000 / sc->sc_clkfreq);
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if (tcmpb == 0)
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tcmpb = 1;
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tcmpb = tcntb - tcmpb;
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PWM_WRITE(sc, TCNTB(timer->timer_index), tcntb - 1);
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PWM_WRITE(sc, TCMPB(timer->timer_index), tcmpb - 1);
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tcon = PWM_READ(sc, TCON);
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tcon |= TCON_UPDATE(timer->timer_index);
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tcon |= TCON_AUTO_RELOAD(timer->timer_index);
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PWM_WRITE(sc, TCON, tcon);
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tcon &= ~TCON_UPDATE(timer->timer_index);
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PWM_WRITE(sc, TCON, tcon);
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return 0;
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}
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static pwm_tag_t
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exynos_pwm_get_tag(device_t dev, const void *data, size_t len)
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{
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struct exynos_pwm_softc * const sc = device_private(dev);
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struct exynos_pwm_timer *timer;
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const u_int *pwm = data;
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struct pwm_config conf;
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if (len != 16)
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return NULL;
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const u_int index = be32toh(pwm[1]);
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if (index >= 32 || (sc->sc_timermask & __BIT(index)) == 0)
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return NULL;
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const u_int period = be32toh(pwm[2]);
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const u_int polarity = be32toh(pwm[3]);
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timer = &sc->sc_timer[index];
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/* Set initial timer polarity and period from specifier */
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exynos_pwm_get_config(&timer->timer_pwm, &conf);
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conf.period = period;
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conf.polarity = polarity ? PWM_ACTIVE_LOW : PWM_ACTIVE_HIGH;
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exynos_pwm_set_config(&timer->timer_pwm, &conf);
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return &timer->timer_pwm;
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}
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static struct fdtbus_pwm_controller_func exynos_pwm_funcs = {
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.get_tag = exynos_pwm_get_tag
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};
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static int
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exynos_pwm_match(device_t parent, cfdata_t cf, void *aux)
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{
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struct fdt_attach_args * const faa = aux;
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return of_match_compatible(faa->faa_phandle, compatible);
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}
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static void
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exynos_pwm_attach(device_t parent, device_t self, void *aux)
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{
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struct exynos_pwm_softc * const sc = device_private(self);
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struct fdt_attach_args * const faa = aux;
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const int phandle = faa->faa_phandle;
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const u_int *data;
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struct clk *clk;
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bus_addr_t addr;
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bus_size_t size;
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int error, len, n;
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if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
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aprint_error(": couldn't get registers\n");
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return;
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}
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clk = fdtbus_clock_get(phandle, "timers");
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if (clk == NULL || clk_enable(clk) != 0) {
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aprint_error(": couldn't enable timers clock\n");
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return;
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}
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sc->sc_dev = self;
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sc->sc_clkfreq = clk_get_rate(clk);
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sc->sc_bst = faa->faa_bst;
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error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh);
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if (error) {
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aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error);
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return;
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}
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for (n = 0; n < PWM_NTIMERS; n++) {
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sc->sc_timer[n].timer_index = n;
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sc->sc_timer[n].timer_pwm.pwm_enable = exynos_pwm_enable;
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sc->sc_timer[n].timer_pwm.pwm_get_config = exynos_pwm_get_config;
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sc->sc_timer[n].timer_pwm.pwm_set_config = exynos_pwm_set_config;
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sc->sc_timer[n].timer_pwm.pwm_dev = self;
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sc->sc_timer[n].timer_pwm.pwm_priv = &sc->sc_timer[n];
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sc->sc_timermask |= __BIT(n);
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}
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data = fdtbus_get_prop(phandle, "samsung,pwm-outputs", &len);
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if (data) {
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sc->sc_timermask = 0;
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for (n = 0; n < len / 4; n++) {
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sc->sc_timermask |= __BIT(be32toh(data[n]));
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}
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}
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aprint_naive("\n");
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aprint_normal(": PWM\n");
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fdtbus_register_pwm_controller(self, phandle,
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&exynos_pwm_funcs);
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}
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CFATTACH_DECL_NEW(exynos_pwm, sizeof(struct exynos_pwm_softc),
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exynos_pwm_match, exynos_pwm_attach, NULL, NULL);
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@ -1,4 +1,4 @@
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# $NetBSD: files.exynos,v 1.28 2018/07/03 16:09:04 jmcneill Exp $
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# $NetBSD: files.exynos,v 1.29 2018/07/04 23:06:54 jmcneill Exp $
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#
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# Configuration info for Samsung Exynos SoC ARM Peripherals
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#
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@ -106,6 +106,11 @@ device exyoi2c: i2cbus, i2c_bitbang
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attach exyoi2c at fdt with exynos_i2c
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file arch/arm/samsung/exynos_i2c.c exynos_i2c needs-flag
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# PWM timer
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device expwm: pwm
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attach expwm at fdt with exynos_pwm
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file arch/arm/samsung/exynos_pwm.c exynos_pwm
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device exy5422clk: clk
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attach exy5422clk at fdt with exynos5422_clock
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file arch/arm/samsung/exynos5422_clock.c exynos5422_clock
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