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Add pwm clocks

This commit is contained in:
jmcneill 2018-07-04 23:06:28 +00:00
parent 637d09aaa9
commit bfa0614efd
1 changed files with 20 additions and 3 deletions
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23
sys/arch/arm/samsung/exynos5422_clock.c
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@ -1,4 +1,4 @@
/* $NetBSD: exynos5422_clock.c,v 1.10 2018/07/03 16:30:13 jmcneill Exp $ */
/* $NetBSD: exynos5422_clock.c,v 1.11 2018/07/04 23:06:28 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
@ -29,7 +29,7 @@
#include "locators.h"
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: exynos5422_clock.c,v 1.10 2018/07/03 16:30:13 jmcneill Exp $");
__KERNEL_RCSID(0, "$NetBSD: exynos5422_clock.c,v 1.11 2018/07/04 23:06:28 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@ -378,6 +378,7 @@ static const struct clk_funcs exynos5422_clock_funcs = {
#define EXYNOS5422_SRC_TOP12 0x10288
#define EXYNOS5422_DIV_TOP0 0x10500
#define EXYNOS5422_DIV_TOP1 0x10504
#define EXYNOS5422_DIV_FSYS0 0x10548
#define EXYNOS5422_DIV_FSYS1 0x1054c
#define EXYNOS5422_DIV_PERIC0 0x10558
@ -385,7 +386,8 @@ static const struct clk_funcs exynos5422_clock_funcs = {
#define EXYNOS5422_GATE_BUS_FSYS0 0x10740
#define EXYNOS5422_GATE_TOP_SCLK_FSYS 0x10840
#define EXYNOS5422_GATE_TOP_SCLK_PERIC 0x10850
#define EXYNOS5422_GATE_IP_FSYS 0x10944
#define EXYNOS5422_GATE_IP_FSYS 0x10944
#define EXYNOS5422_GATE_IP_PERIC 0x10950
static const char *mout_cpll_p[] = { "fin_pll", "fout_cpll" };
static const char *mout_dpll_p[] = { "fin_pll", "fout_dpll" };
@ -403,6 +405,10 @@ static const char *mout_user_aclk200_fsys_p[] =
{ "fin_pll", "mout_sw_aclk200_fsys" };
static const char *mout_user_aclk200_fsys2_p[] =
{ "fin_pll", "mout_sw_aclk200_fsys2" };
static const char *mout_user_aclk66_peric_p[] =
{ "fin_pll", "mout_sw_aclk66" };
static const char *mout_sw_aclk66_p[] =
{ "dout_aclk66", "sclk_spll" };
static const char *mout_sw_aclk200_fsys_p[] =
{ "dout_aclk200_fsys", "sclk_spll" };
static const char *mout_sw_aclk200_fsys2_p[] =
@ -457,11 +463,18 @@ static struct exynos_clk exynos5422_clocks[] = {
mout_user_aclk200_fsys_p),
CLK_MUX("mout_user_aclk200_fsys2", EXYNOS5422_SRC_TOP3, __BIT(12),
mout_user_aclk200_fsys2_p),
CLK_MUX("mout_aclk66", EXYNOS5422_SRC_TOP1, __BITS(9,8),
mout_group1_p),
CLK_MUX("mout_aclk200_fsys", EXYNOS5422_SRC_TOP0, __BITS(25,24),
mout_group1_p),
CLK_MUX("mout_aclk200_fsys2", EXYNOS5422_SRC_TOP0, __BITS(13,12),
mout_group1_p),
CLK_MUX("mout_sw_aclk66", EXYNOS5422_SRC_TOP11, __BIT(8),
mout_sw_aclk66_p),
CLK_MUX("mout_user_aclk66_peric", EXYNOS5422_SRC_TOP4, __BIT(8),
mout_user_aclk66_peric_p),
CLK_MUX("mout_usbd301", EXYNOS5422_SRC_FSYS, __BITS(6,4),
mout_group2_p),
CLK_MUX("mout_usbd300", EXYNOS5422_SRC_FSYS, __BITS(22,20),
@ -481,6 +494,7 @@ static struct exynos_clk exynos5422_clocks[] = {
CLK_MUX("mout_uart3", EXYNOS5422_SRC_PERIC0, __BITS(18,16),
mout_group2_p),
CLK_DIV("dout_aclk66", "mout_aclk66", EXYNOS5422_DIV_TOP1, __BITS(13,8)),
CLK_DIV("dout_aclk200_fsys", "mout_aclk200_fsys", EXYNOS5422_DIV_TOP0, __BITS(30,28)),
CLK_DIV("dout_aclk200_fsys2", "mout_aclk200_fsys2", EXYNOS5422_DIV_TOP0, __BITS(14,12)),
@ -540,6 +554,9 @@ static struct exynos_clk exynos5422_clocks[] = {
__BIT(19), CLK_SET_RATE_PARENT),
CLK_GATE("usbd301", "aclk200_fsys", EXYNOS5422_GATE_IP_FSYS,
__BIT(20), CLK_SET_RATE_PARENT),
CLK_GATE("pwm", "mout_user_aclk66_peric", EXYNOS5422_GATE_IP_PERIC,
__BIT(24), CLK_SET_RATE_PARENT),
};
static int exynos5422_clock_match(device_t, cfdata_t, void *);