The iic and rtc are now devices and have been rewritten ane moved to the
mainbus directory.
This commit is contained in:
mark
parent
11fb5f4ba0
commit
ab4a325e4c
@ -1,242 +0,0 @@
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/* $NetBSD: iic.S,v 1.1 1996/01/31 23:16:02 mark Exp $ */
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/*
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* Copyright (c) 1994 Mark Brinicombe.
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* Copyright (c) 1994 Brini.
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* All rights reserved.
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*
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* This code is derived from software written for Brini by Mark Brinicombe
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*
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||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Brini.
|
||||
* 4. The name of the company nor the name of the author may be used to
|
||||
* endorse or promote products derived from this software without specific
|
||||
* prior written permission.
|
||||
*
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||||
* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* RiscBSD kernel project
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*
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* iic.s
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*
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* Low level routines to with IIC bus devices
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*
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* Created : 13/10/94
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* Last updated : 15/10/94
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*
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* Based of kate/display/iic.s
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*
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* $Id: iic.S,v 1.1 1996/01/31 23:16:02 mark Exp $
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*/
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#include <machine/cpu.h>
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#include <machine/iomd.h>
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#define IIC_BITDELAY 10
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sp .req r13
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lr .req r14
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pc .req r15
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.text
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.global _iic_set_state
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_iic_set_state:
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/*
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* Parameters
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* r0 - IIC data bit
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* r1 - IIC clock bit
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*/
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/* Store temporary register */
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/* stmfd sp!, {r4}*/
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/*
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* Mask the data and clock bits
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* Since these routines are only called from iiccontrol.c this is not
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* really needed
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*/
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and r0, r0, #0x00000001
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and r1, r1, #0x00000001
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/* Get address of IOMD control register */
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mov r2, #(IOMD_BASE)
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/* Get the current CPSR */
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/* mrs r4, cpsr_all
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orr r3, r4, #(I32_bit | F32_bit)
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msr cpsr_all, r3
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*/
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IRQdisable
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/* Get current value of control register */
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ldrb r3, [r2, #(IOMD_IOCR - IOMD_BASE)]
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/* Preserve non-IIC bits */
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bic r3, r3, #0x00000003
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orr r3, r3, #0x000000c0
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/* Set the IIC clock and data bits */
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orr r3, r3, r0
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orr r3, r3, r1, lsl #1
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/* Store the new value of control register */
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strb r3, [r2, #(IOMD_IOCR - IOMD_BASE)]
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/* Restore CPSR state */
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/* msr cpsr_all, r4 */
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IRQenable
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/* Restore temporary register */
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/* ldmfd sp!, {r4} */
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/* Pause a bit */
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mov r0, #(IIC_BITDELAY)
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/* Exit via iic_delay routine */
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b _iic_delay
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.global _iic_set_state_and_ack
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_iic_set_state_and_ack:
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/*
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* Parameters
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* r0 - IIC data bit
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* r1 - IIC clock bit
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*/
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/* Store temporary register */
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/* stmfd sp!, {r4} */
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/*
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* Mask the data and clock bits
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* Since these routines are only called from iiccontrol.c this is not
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* really needed
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*/
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and r0, r0, #0x00000001
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and r1, r1, #0x00000001
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/* Get address of IOMD control register */
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mov r2, #(IOMD_BASE)
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/* Get the current CPSR */
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/* mrs r4, cpsr_all
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orr r3, r4, #(I32_bit | F32_bit)
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msr cpsr_all, r3
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*/
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IRQdisable
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/* Get current value of control register */
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ldrb r3, [r2, #(IOMD_IOCR - IOMD_BASE)]
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/* Preserve non-IIC bits */
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bic r3, r3, #0x00000003
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orr r3, r3, #0x000000c0
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/* Set the IIC clock and data bits */
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orr r3, r3, r0
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orr r3, r3, r1, lsl #1
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/* Store the new value of control register */
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strb r3, [r2, #(IOMD_IOCR - IOMD_BASE)]
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iic_set_state_and_ack_loop:
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ldrb r3, [r2, #(IOMD_IOCR - IOMD_BASE)]
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tst r3, #0x00000002
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beq iic_set_state_and_ack_loop
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/* Restore CPSR state */
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/* msr cpsr_all, r4 */
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IRQenable
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/* Restore temporary register */
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/* ldmfd sp!, {r4} */
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/* Pause a bit */
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mov r0, #(IIC_BITDELAY)
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/* Exit via iic_delay routine */
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b _iic_delay
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.global _iic_delay
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_iic_delay:
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/*
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* Parameters
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* r0 - time to wait
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*/
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/* Load address of IOMD */
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mov r2, #(IOMD_BASE)
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/* Latch current value of timer 1 */
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strb r2, [r2, #(IOMD_T0LATCH - IOMD_BASE)]
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/* Get the latched value */
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ldrb r1, [r2, #(IOMD_T0LOW - IOMD_BASE)]
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/* Loop until timer reaches end value */
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iic_delay_loop:
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/* Latch the current value of timer1 */
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strb r2, [r2, #(IOMD_T0LATCH - IOMD_BASE)]
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/* Get the latched value */
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ldrb r3, [r2, #(IOMD_T0LOW - IOMD_BASE)]
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/* Loop until timer reached expected value */
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teq r3, r1
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movne r1, r3
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beq iic_delay_loop
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subs r0, r0, #0x00000001
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bne iic_delay_loop
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/* Exit */
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mov pc, lr
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/* End of iic.S */
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@ -1,211 +0,0 @@
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/* $NetBSD: iiccontrol.c,v 1.2 1996/03/27 22:42:14 mark Exp $ */
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/*
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* Copyright (c) 1994 Mark Brinicombe.
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* Copyright (c) 1994 Brini.
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* All rights reserved.
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*
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* This code is derived from software written for Brini by Mark Brinicombe
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*
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Brini.
|
||||
* 4. The name of the company nor the name of the author may be used to
|
||||
* endorse or promote products derived from this software without specific
|
||||
* prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
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||||
*
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* RiscBSD kernel project
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*
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* iiccontrol.c
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*
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* Routines to communicate with IIC bus devices
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*
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* Created : 13/10/94
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*
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* Based of kate/display/iiccontrol.c
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*/
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#include <sys/types.h>
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#include <machine/iomd.h>
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#include <machine/katelib.h>
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#include <machine/cpu.h>
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#include <machine/irqhandler.h>
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#define iic_bitdelay 10
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int iic_control __P((u_char /*address*/, u_char */*buffer*/, int /*count*/));
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void iic_set_state __P((int /*data*/, int /*clock*/));
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void iic_set_state_and_ack __P((int /*data*/, int /*clock*/));
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void iic_delay __P((int /*delay*/));
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static int iic_getack __P((void));
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static void iic_write_bit __P((int /*bit*/));
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static int iic_write_byte __P((u_char /*value*/));
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static u_char iic_read_byte __P((void));
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static void iic_start_bit __P((void));
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static void iic_stop_bit __P((void));
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/*
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* Main entry to IIC driver.
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*/
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int
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iic_control(address, buffer, count)
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u_char address;
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u_char *buffer;
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int count;
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{
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int loop;
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/* Send the start bit */
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iic_start_bit();
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/* Send the address */
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if (!iic_write_byte(address)) {
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iic_stop_bit();
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return(-1);
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}
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/* Read or write the data as required */
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if ((address & 1) == 0) {
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/* Write bytes */
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for (loop = 0; loop < count; ++loop) {
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if (!iic_write_byte(buffer[loop])) {
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iic_stop_bit();
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return(-1);
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}
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}
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}
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else {
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/* Read bytes */
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for (loop = 0; loop < count; ++loop) {
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buffer[loop] = iic_read_byte();
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/* Send final acknowledge */
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if (loop == (count - 1))
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iic_write_bit(1);
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else
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iic_write_bit(0);
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}
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}
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||||
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||||
/* Send stop bit */
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||||
|
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iic_stop_bit();
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return(0);
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}
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static int
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iic_getack()
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{
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u_int oldirqstate;
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int ack;
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iic_set_state(1, 0);
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oldirqstate = disable_interrupts(I32_bit);
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iic_set_state_and_ack(1, 1);
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ack = ReadByte(IOMD_IOCR);
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iic_set_state(1, 0);
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restore_interrupts(oldirqstate);
|
||||
|
||||
return((ack & 1) == 0);
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}
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||||
static void
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iic_write_bit(bit)
|
||||
int bit;
|
||||
{
|
||||
u_int oldirqstate;
|
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|
||||
iic_set_state(bit, 0);
|
||||
oldirqstate = disable_interrupts(I32_bit);
|
||||
iic_set_state_and_ack(bit, 1);
|
||||
iic_set_state(bit, 0);
|
||||
restore_interrupts(oldirqstate);
|
||||
}
|
||||
|
||||
|
||||
static int
|
||||
iic_write_byte(value)
|
||||
u_char value;
|
||||
{
|
||||
int loop;
|
||||
int bit;
|
||||
|
||||
for (loop = 0x80; loop != 0; loop = loop >> 1) {
|
||||
bit = ((value & loop) != 0);
|
||||
iic_write_bit(bit);
|
||||
}
|
||||
|
||||
return(iic_getack());
|
||||
}
|
||||
|
||||
|
||||
static u_char
|
||||
iic_read_byte()
|
||||
{
|
||||
int loop;
|
||||
u_char byte;
|
||||
u_int oldirqstate;
|
||||
|
||||
iic_set_state(1,0);
|
||||
|
||||
byte = 0;
|
||||
|
||||
for (loop = 0; loop < 8; ++loop) {
|
||||
oldirqstate = disable_interrupts(I32_bit);
|
||||
iic_set_state_and_ack(1, 1);
|
||||
byte = (byte << 1) + (ReadByte(IOMD_IOCR) & 1);
|
||||
iic_set_state(1, 0);
|
||||
restore_interrupts(oldirqstate);
|
||||
}
|
||||
|
||||
return(byte);
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
iic_start_bit()
|
||||
{
|
||||
iic_set_state(1, 1);
|
||||
iic_set_state(0, 1);
|
||||
iic_delay(10);
|
||||
iic_set_state(0, 0);
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
iic_stop_bit()
|
||||
{
|
||||
iic_set_state(0, 1);
|
||||
iic_set_state(1, 1);
|
||||
}
|
||||
|
||||
/* End of iiccontrol.c */
|
||||
@ -1,200 +0,0 @@
|
||||
/* $NetBSD: rtc.c,v 1.2 1996/03/08 17:11:13 mark Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1994,1995 Mark Brinicombe.
|
||||
* Copyright (c) 1994 Brini.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This code is derived from software written for Brini by Mark Brinicombe
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Brini.
|
||||
* 4. The name of the company nor the name of the author may be used to
|
||||
* endorse or promote products derived from this software without specific
|
||||
* prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* RiscBSD kernel project
|
||||
*
|
||||
* rtc.c
|
||||
*
|
||||
* Routines to read and write the RTC and CMOS RAM
|
||||
*
|
||||
* Created : 13/10/94
|
||||
* Based of kate/display/iiccontrol.c
|
||||
*/
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <machine/rtc.h>
|
||||
|
||||
/* Read a byte from CMOS RAM */
|
||||
|
||||
int
|
||||
cmos_read(location)
|
||||
int location;
|
||||
{
|
||||
u_char buff;
|
||||
|
||||
/*
|
||||
* This commented code dates from when I was translating CMOS address
|
||||
* from the RISCOS addresses. Now all addresses are specifed as
|
||||
* actual addresses in the CMOS RAM
|
||||
*/
|
||||
|
||||
/*
|
||||
if (location > 0xF0)
|
||||
return(-1);
|
||||
|
||||
if (location < 0xC0)
|
||||
buff = location + 0x40;
|
||||
else
|
||||
buff = location - 0xB0;
|
||||
*/
|
||||
buff = location;
|
||||
|
||||
if (iic_control(RTC_Write, &buff, 1))
|
||||
return(-1);
|
||||
if (iic_control(RTC_Read, &buff, 1))
|
||||
return(-1);
|
||||
|
||||
return(buff);
|
||||
}
|
||||
|
||||
|
||||
/* Write a byte to CMOS RAM */
|
||||
|
||||
int
|
||||
cmos_write(location, value)
|
||||
int location;
|
||||
int value;
|
||||
{
|
||||
u_char buff[2];
|
||||
|
||||
/*
|
||||
* This commented code dates from when I was translating CMOS address
|
||||
* from the RISCOS addresses. Now all addresses are specifed as
|
||||
* actual addresses in the CMOS RAM
|
||||
*/
|
||||
|
||||
/* if (location > 0xF0)
|
||||
return(-1);
|
||||
|
||||
if (location < 0xC0)
|
||||
buff = location + 0x40;
|
||||
else
|
||||
buff = location - 0xB0;
|
||||
*/
|
||||
buff[0] = location;
|
||||
buff[1] = value;
|
||||
|
||||
if (iic_control(RTC_Write, buff, 2))
|
||||
return(-1);
|
||||
|
||||
return(0);
|
||||
}
|
||||
|
||||
|
||||
/* Hex to BCD and BCD to hex conversion routines */
|
||||
|
||||
static inline int
|
||||
hexdectodec(n)
|
||||
u_char n;
|
||||
{
|
||||
return(((n >> 4) & 0x0F) * 10 + (n & 0x0F));
|
||||
}
|
||||
|
||||
static inline int
|
||||
dectohexdec(n)
|
||||
u_char n;
|
||||
{
|
||||
return(((n/10) << 4) + (n%10));
|
||||
}
|
||||
|
||||
|
||||
/* Write the RTC data from an 8 byte buffer */
|
||||
|
||||
int
|
||||
rtc_write(rtc)
|
||||
rtc_t *rtc;
|
||||
{
|
||||
u_char buff[8];
|
||||
|
||||
buff[0] = 0;
|
||||
|
||||
buff[1] = dectohexdec(rtc->rtc_micro);
|
||||
buff[2] = dectohexdec(rtc->rtc_centi);
|
||||
buff[3] = dectohexdec(rtc->rtc_sec);
|
||||
buff[4] = dectohexdec(rtc->rtc_min);
|
||||
buff[5] = dectohexdec(rtc->rtc_hour);
|
||||
buff[6] = dectohexdec(rtc->rtc_day);
|
||||
buff[7] = dectohexdec(rtc->rtc_mon);
|
||||
|
||||
if (iic_control(RTC_Write, buff, 8))
|
||||
return(0);
|
||||
|
||||
cmos_write(RTC_ADDR_YEAR, rtc->rtc_year);
|
||||
cmos_write(RTC_ADDR_CENT, rtc->rtc_cen);
|
||||
|
||||
return(1);
|
||||
}
|
||||
|
||||
|
||||
/* Read the RTC data into a 8 byte buffer */
|
||||
|
||||
int
|
||||
rtc_read(rtc)
|
||||
rtc_t *rtc;
|
||||
{
|
||||
u_char buff[8];
|
||||
int byte;
|
||||
|
||||
buff[0] = 0;
|
||||
|
||||
if (iic_control(RTC_Write, buff, 1))
|
||||
return(0);
|
||||
|
||||
if (iic_control(RTC_Read, buff, 8))
|
||||
return(0);
|
||||
|
||||
rtc->rtc_micro = hexdectodec(buff[0] & 0xff);
|
||||
rtc->rtc_centi = hexdectodec(buff[1] & 0xff);
|
||||
rtc->rtc_sec = hexdectodec(buff[2] & 0x7f);
|
||||
rtc->rtc_min = hexdectodec(buff[3] & 0x7f);
|
||||
rtc->rtc_hour = hexdectodec(buff[4] & 0x3f);
|
||||
rtc->rtc_day = hexdectodec(buff[5] & 0x3f);
|
||||
rtc->rtc_mon = hexdectodec(buff[6] & 0x1f);
|
||||
|
||||
byte = cmos_read(RTC_ADDR_YEAR);
|
||||
if (byte == -1)
|
||||
return(0);
|
||||
rtc->rtc_year = byte;
|
||||
|
||||
byte = cmos_read(RTC_ADDR_CENT);
|
||||
if (byte == -1)
|
||||
return(0);
|
||||
rtc->rtc_cen = byte;
|
||||
|
||||
return(1);
|
||||
}
|
||||
|
||||
/* End of rtc.c */
|
||||
Loading…
x
Reference in New Issue
Block a user