- split siop_pci in attachements vs helper functions, for comming esiop
- add a reset callback to enable PCI-specific features. This improve bandwith by a factor of 2 on my alpha with a 875 ! - sync copyrigth notice
This commit is contained in:
bouyer
parent
73faa41bdf
commit
a1c4db6c37
@ -1,4 +1,4 @@
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/* $NetBSD: siop_pci.c,v 1.7 2000/05/10 17:22:46 thorpej Exp $ */
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/* $NetBSD: siop_pci.c,v 1.8 2000/05/15 07:53:17 bouyer Exp $ */
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/*
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* Copyright (c) 2000 Manuel Bouyer.
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@ -17,17 +17,16 @@
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
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||||
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
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* AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* SYM53c8xx PCI-SCSI I/O Processors driver: PCI front-end */
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@ -35,166 +34,16 @@
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/malloc.h>
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#include <sys/buf.h>
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#include <sys/kernel.h>
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#include <machine/endian.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/scsipi/scsipi_all.h>
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#include <dev/scsipi/scsipiconf.h>
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#include <dev/ic/siopvar.h>
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/* structure describing each chip */
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struct siop_product_desc {
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u_int32_t product;
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int revision;
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const char *name;
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int features; /* features are defined in siopvar.h */
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u_int8_t maxburst;
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u_int8_t maxoff; /* maximum supported offset */
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u_int8_t clock_div; /* clock divider to use for async. logic */
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u_int8_t clock_period; /* clock period (ns * 10) */
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};
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/* List (array, really :) of chips we know how to handle */
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const struct siop_product_desc siop_products[] = {
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{ PCI_PRODUCT_SYMBIOS_810,
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0x00,
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"Symbios Logic 53c810 (fast scsi)",
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SF_PCI_RL,
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4, 8, 3, 250
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},
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{ PCI_PRODUCT_SYMBIOS_810,
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0x10,
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"Symbios Logic 53c810a (fast scsi)",
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SF_PCI_RL | SF_PCI_BOF | SF_CHIP_PF,
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4, 8, 3, 250
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},
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{ PCI_PRODUCT_SYMBIOS_815,
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0x00,
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"Symbios Logic 53c815 (fast scsi)",
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SF_PCI_RL | SF_PCI_BOF,
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4, 8, 3, 250
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},
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{ PCI_PRODUCT_SYMBIOS_820,
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0x00,
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"Symbios Logic 53c820 (fast wide scsi)",
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SF_PCI_RL | SF_BUS_WIDE,
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4, 8, 3, 250
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},
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{ PCI_PRODUCT_SYMBIOS_825,
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0x00,
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"Symbios Logic 53c825 (fast wide scsi)",
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SF_PCI_RL | SF_PCI_BOF | SF_BUS_WIDE,
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4, 8, 3, 250
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},
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{ PCI_PRODUCT_SYMBIOS_825,
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0x10,
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"Symbios Logic 53c825a (fast wide scsi)",
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SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
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SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM |
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SF_BUS_WIDE,
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7, 8, 3, 250
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},
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{ PCI_PRODUCT_SYMBIOS_860,
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0x00,
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"Symbios Logic 53c860 (ultra scsi)",
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SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
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SF_CHIP_PF |
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SF_BUS_ULTRA,
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4, 8, 5, 125
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},
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{ PCI_PRODUCT_SYMBIOS_875,
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0x00,
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"Symbios Logic 53c875 (ultra-wide scsi)",
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SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
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SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM |
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SF_BUS_ULTRA | SF_BUS_WIDE,
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7, 16, 5, 125
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},
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{ PCI_PRODUCT_SYMBIOS_875,
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0x02,
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"Symbios Logic 53c875 (ultra-wide scsi)",
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SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
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SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR |
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SF_BUS_ULTRA | SF_BUS_WIDE,
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7, 16, 5, 125
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},
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{ PCI_PRODUCT_SYMBIOS_875J,
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0x00,
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"Symbios Logic 53c875j (ultra-wide scsi)",
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SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
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SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR |
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SF_BUS_ULTRA | SF_BUS_WIDE,
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7, 16, 5, 125
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},
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{ PCI_PRODUCT_SYMBIOS_885,
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0x00,
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"Symbios Logic 53c885 (ultra-wide scsi)",
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SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
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SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR |
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SF_BUS_ULTRA | SF_BUS_WIDE,
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7, 16, 5, 125
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},
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{ PCI_PRODUCT_SYMBIOS_895,
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0x00,
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"Symbios Logic 53c895 (ultra2-wide scsi)",
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SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
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SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD |
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SF_BUS_ULTRA2 | SF_BUS_WIDE,
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7, 31, 7, 62
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},
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{ PCI_PRODUCT_SYMBIOS_896,
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0x00,
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"Symbios Logic 53c896 (ultra2-wide scsi)",
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SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
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SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD |
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SF_BUS_ULTRA2 | SF_BUS_WIDE,
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7, 31, 7, 62
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},
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{ 0,
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0x00,
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NULL,
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0x00,
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0, 0, 0, 0
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},
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};
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const struct siop_product_desc * siop_lookup_product __P((u_int32_t, int));
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const struct siop_product_desc *
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siop_lookup_product(id, rev)
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u_int32_t id;
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int rev;
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{
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const struct siop_product_desc *pp;
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const struct siop_product_desc *rp = NULL;
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if (PCI_VENDOR(id) != PCI_VENDOR_SYMBIOS)
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return NULL;
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for (pp = siop_products; pp->name != NULL; pp++) {
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if (PCI_PRODUCT(id) == pp->product && pp->revision <= rev)
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if (rp == NULL || pp->revision > rp->revision)
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rp = pp;
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}
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return rp;
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}
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/* Driver internal state */
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struct siop_pci_softc {
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struct siop_softc siop;
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pci_chipset_tag_t sc_pc; /* PCI registers info */
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pcitag_t sc_tag;
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void *sc_ih; /* PCI interrupt handle */
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const struct siop_product_desc *sc_pp; /* Adapter description */
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};
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#include <dev/pci/siop_pci_common.h>
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int siop_pci_match __P((struct device *, struct cfdata *, void *));
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void siop_pci_attach __P((struct device *, struct device *, void *));
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@ -225,82 +74,10 @@ siop_pci_attach(parent, self, aux)
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void *aux;
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{
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struct pci_attach_args *pa = aux;
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pci_chipset_tag_t pc = pa->pa_pc;
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pcitag_t tag = pa->pa_tag;
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struct siop_pci_softc *sc = (struct siop_pci_softc *)self;
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const char *intrstr;
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pci_intr_handle_t intrhandle;
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bus_space_tag_t iot, memt;
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bus_space_handle_t ioh, memh;
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pcireg_t memtype;
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int memh_valid, ioh_valid;
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bus_addr_t ioaddr, memaddr;
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sc->sc_pp = siop_lookup_product(pa->pa_id, PCI_REVISION(pa->pa_class));
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if (sc->sc_pp == NULL) {
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printf("sym: broken match/attach!!\n");
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if (siop_pci_attach_common(sc, pa) == 0)
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return;
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}
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printf(": %s\n", sc->sc_pp->name);
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sc->sc_pc = pc;
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sc->sc_tag = tag;
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sc->siop.sc_dmat = pa->pa_dmat;
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memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 0x14);
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switch (memtype) {
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case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
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case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
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memh_valid = (pci_mapreg_map(pa, 0x14, memtype, 0,
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&memt, &memh, &memaddr, NULL) == 0);
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break;
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default:
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memh_valid = 0;
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}
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ioh_valid = (pci_mapreg_map(pa, 0x10, PCI_MAPREG_TYPE_IO, 0,
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&iot, &ioh, &ioaddr, NULL) == 0);
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if (memh_valid) {
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sc->siop.sc_rt = memt;
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sc->siop.sc_rh = memh;
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sc->siop.sc_raddr = memaddr;
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} else if (ioh_valid) {
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sc->siop.sc_rt = iot;
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sc->siop.sc_rh = ioh;
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sc->siop.sc_raddr = ioaddr;
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} else {
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printf("%s: unable to map device registers\n",
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sc->siop.sc_dev.dv_xname);
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return;
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}
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if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin,
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pa->pa_intrline, &intrhandle) != 0) {
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printf("%s: couldn't map interrupt\n",
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sc->siop.sc_dev.dv_xname);
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return;
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}
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intrstr = pci_intr_string(pa->pa_pc, intrhandle);
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sc->sc_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO,
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siop_intr, &sc->siop);
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if (sc->sc_ih != NULL) {
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printf("%s: interrupting at %s\n",
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sc->siop.sc_dev.dv_xname,
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intrstr ? intrstr : "unknown interrupt");
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} else {
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printf("%s: couldn't establish interrupt",
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sc->siop.sc_dev.dv_xname);
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if (intrstr != NULL)
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printf(" at %s", intrstr);
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printf("\n");
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return;
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}
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/* copy interesting infos about the chip */
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sc->siop.features = sc->sc_pp->features;
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sc->siop.maxburst = sc->sc_pp->maxburst;
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sc->siop.maxoff = sc->sc_pp->maxoff;
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sc->siop.clock_div = sc->sc_pp->clock_div;
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sc->siop.clock_period = sc->sc_pp->clock_period;
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/* attach generic code */
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siop_attach(&sc->siop);
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}
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304
sys/dev/pci/siop_pci_common.c
Normal file
304
sys/dev/pci/siop_pci_common.c
Normal file
@ -0,0 +1,304 @@
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/* $NetBSD: siop_pci_common.c,v 1.1 2000/05/15 07:53:18 bouyer Exp $ */
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/*
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* Copyright (c) 2000 Manuel Bouyer.
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions
|
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* are met:
|
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* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
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* notice, this list of conditions and the following disclaimer in the
|
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
|
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* This product includes software developed by Manuel Bouyer
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* 4. The name of the author may not be used to endorse or promote products
|
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* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/* SYM53c8xx PCI-SCSI I/O Processors driver: PCI front-end */
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/device.h>
|
||||
#include <sys/malloc.h>
|
||||
#include <sys/buf.h>
|
||||
#include <sys/kernel.h>
|
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|
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#include <machine/endian.h>
|
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|
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/scsipi/scsipi_all.h>
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#include <dev/scsipi/scsipiconf.h>
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#include <dev/ic/siopreg.h>
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#include <dev/ic/siopvar.h>
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#include <dev/pci/siop_pci_common.h>
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|
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/* List (array, really :) of chips we know how to handle */
|
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const struct siop_product_desc siop_products[] = {
|
||||
{ PCI_PRODUCT_SYMBIOS_810,
|
||||
0x00,
|
||||
"Symbios Logic 53c810 (fast scsi)",
|
||||
SF_PCI_RL | SF_CHIP_LS,
|
||||
4, 8, 3, 250
|
||||
},
|
||||
{ PCI_PRODUCT_SYMBIOS_810,
|
||||
0x10,
|
||||
"Symbios Logic 53c810a (fast scsi)",
|
||||
SF_PCI_RL | SF_PCI_BOF | SF_CHIP_PF | SF_CHIP_LS,
|
||||
4, 8, 3, 250
|
||||
},
|
||||
{ PCI_PRODUCT_SYMBIOS_815,
|
||||
0x00,
|
||||
"Symbios Logic 53c815 (fast scsi)",
|
||||
SF_PCI_RL | SF_PCI_BOF,
|
||||
4, 8, 3, 250
|
||||
},
|
||||
{ PCI_PRODUCT_SYMBIOS_820,
|
||||
0x00,
|
||||
"Symbios Logic 53c820 (fast wide scsi)",
|
||||
SF_PCI_RL | SF_CHIP_LS | SF_BUS_WIDE,
|
||||
4, 8, 3, 250
|
||||
},
|
||||
{ PCI_PRODUCT_SYMBIOS_825,
|
||||
0x00,
|
||||
"Symbios Logic 53c825 (fast wide scsi)",
|
||||
SF_PCI_RL | SF_PCI_BOF | SF_BUS_WIDE,
|
||||
4, 8, 3, 250
|
||||
},
|
||||
{ PCI_PRODUCT_SYMBIOS_825,
|
||||
0x10,
|
||||
"Symbios Logic 53c825a (fast wide scsi)",
|
||||
SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
|
||||
SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_LS | SF_CHIP_10REGS |
|
||||
SF_BUS_WIDE,
|
||||
7, 8, 3, 250
|
||||
},
|
||||
{ PCI_PRODUCT_SYMBIOS_860,
|
||||
0x00,
|
||||
"Symbios Logic 53c860 (ultra scsi)",
|
||||
SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
|
||||
SF_CHIP_PF | SF_CHIP_LS |
|
||||
SF_BUS_ULTRA,
|
||||
4, 8, 5, 125
|
||||
},
|
||||
{ PCI_PRODUCT_SYMBIOS_875,
|
||||
0x00,
|
||||
"Symbios Logic 53c875 (ultra-wide scsi)",
|
||||
SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
|
||||
SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_LS | SF_CHIP_10REGS |
|
||||
SF_BUS_ULTRA | SF_BUS_WIDE,
|
||||
7, 16, 5, 125
|
||||
},
|
||||
{ PCI_PRODUCT_SYMBIOS_875,
|
||||
0x02,
|
||||
"Symbios Logic 53c875 (ultra-wide scsi)",
|
||||
SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
|
||||
SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR |
|
||||
SF_CHIP_LS | SF_CHIP_10REGS |
|
||||
SF_BUS_ULTRA | SF_BUS_WIDE,
|
||||
7, 16, 5, 125
|
||||
},
|
||||
{ PCI_PRODUCT_SYMBIOS_875J,
|
||||
0x00,
|
||||
"Symbios Logic 53c875j (ultra-wide scsi)",
|
||||
SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
|
||||
SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR |
|
||||
SF_CHIP_LS | SF_CHIP_10REGS |
|
||||
SF_BUS_ULTRA | SF_BUS_WIDE,
|
||||
7, 16, 5, 125
|
||||
},
|
||||
{ PCI_PRODUCT_SYMBIOS_885,
|
||||
0x00,
|
||||
"Symbios Logic 53c885 (ultra-wide scsi)",
|
||||
SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
|
||||
SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR |
|
||||
SF_CHIP_LS | SF_CHIP_10REGS |
|
||||
SF_BUS_ULTRA | SF_BUS_WIDE,
|
||||
7, 16, 5, 125
|
||||
},
|
||||
{ PCI_PRODUCT_SYMBIOS_895,
|
||||
0x00,
|
||||
"Symbios Logic 53c895 (ultra2-wide scsi)",
|
||||
SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
|
||||
SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD |
|
||||
SF_CHIP_LS | SF_CHIP_10REGS |
|
||||
SF_BUS_ULTRA2 | SF_BUS_WIDE,
|
||||
7, 31, 7, 62
|
||||
},
|
||||
{ PCI_PRODUCT_SYMBIOS_896,
|
||||
0x00,
|
||||
"Symbios Logic 53c896 (ultra2-wide scsi)",
|
||||
SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
|
||||
SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD |
|
||||
SF_CHIP_LS | SF_CHIP_10REGS |
|
||||
SF_BUS_ULTRA2 | SF_BUS_WIDE,
|
||||
7, 31, 7, 62
|
||||
},
|
||||
{ 0,
|
||||
0x00,
|
||||
NULL,
|
||||
0x00,
|
||||
0, 0, 0, 0
|
||||
},
|
||||
};
|
||||
|
||||
const struct siop_product_desc *
|
||||
siop_lookup_product(id, rev)
|
||||
u_int32_t id;
|
||||
int rev;
|
||||
{
|
||||
const struct siop_product_desc *pp;
|
||||
const struct siop_product_desc *rp = NULL;
|
||||
|
||||
if (PCI_VENDOR(id) != PCI_VENDOR_SYMBIOS)
|
||||
return NULL;
|
||||
|
||||
for (pp = siop_products; pp->name != NULL; pp++) {
|
||||
if (PCI_PRODUCT(id) == pp->product && pp->revision <= rev)
|
||||
if (rp == NULL || pp->revision > rp->revision)
|
||||
rp = pp;
|
||||
}
|
||||
return rp;
|
||||
}
|
||||
|
||||
int
|
||||
siop_pci_attach_common(sc, pa)
|
||||
struct siop_pci_softc *sc;
|
||||
struct pci_attach_args *pa;
|
||||
{
|
||||
pci_chipset_tag_t pc = pa->pa_pc;
|
||||
pcitag_t tag = pa->pa_tag;
|
||||
const char *intrstr;
|
||||
pci_intr_handle_t intrhandle;
|
||||
bus_space_tag_t iot, memt;
|
||||
bus_space_handle_t ioh, memh;
|
||||
pcireg_t memtype;
|
||||
int memh_valid, ioh_valid;
|
||||
bus_addr_t ioaddr, memaddr;
|
||||
|
||||
sc->sc_pp = siop_lookup_product(pa->pa_id, PCI_REVISION(pa->pa_class));
|
||||
if (sc->sc_pp == NULL) {
|
||||
printf("sym: broken match/attach!!\n");
|
||||
return 0;
|
||||
}
|
||||
printf(": %s\n", sc->sc_pp->name);
|
||||
sc->sc_pc = pc;
|
||||
sc->sc_tag = tag;
|
||||
sc->siop.sc_dmat = pa->pa_dmat;
|
||||
|
||||
memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 0x14);
|
||||
switch (memtype) {
|
||||
case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
|
||||
case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
|
||||
memh_valid = (pci_mapreg_map(pa, 0x14, memtype, 0,
|
||||
&memt, &memh, &memaddr, NULL) == 0);
|
||||
break;
|
||||
default:
|
||||
memh_valid = 0;
|
||||
}
|
||||
|
||||
ioh_valid = (pci_mapreg_map(pa, 0x10, PCI_MAPREG_TYPE_IO, 0,
|
||||
&iot, &ioh, &ioaddr, NULL) == 0);
|
||||
|
||||
if (memh_valid) {
|
||||
sc->siop.sc_rt = memt;
|
||||
sc->siop.sc_rh = memh;
|
||||
sc->siop.sc_raddr = memaddr;
|
||||
} else if (ioh_valid) {
|
||||
sc->siop.sc_rt = iot;
|
||||
sc->siop.sc_rh = ioh;
|
||||
sc->siop.sc_raddr = ioaddr;
|
||||
} else {
|
||||
printf("%s: unable to map device registers\n",
|
||||
sc->siop.sc_dev.dv_xname);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin,
|
||||
pa->pa_intrline, &intrhandle) != 0) {
|
||||
printf("%s: couldn't map interrupt\n",
|
||||
sc->siop.sc_dev.dv_xname);
|
||||
return 0;
|
||||
}
|
||||
intrstr = pci_intr_string(pa->pa_pc, intrhandle);
|
||||
sc->sc_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO,
|
||||
siop_intr, &sc->siop);
|
||||
if (sc->sc_ih != NULL) {
|
||||
printf("%s: interrupting at %s\n",
|
||||
sc->siop.sc_dev.dv_xname,
|
||||
intrstr ? intrstr : "unknown interrupt");
|
||||
} else {
|
||||
printf("%s: couldn't establish interrupt",
|
||||
sc->siop.sc_dev.dv_xname);
|
||||
if (intrstr != NULL)
|
||||
printf(" at %s", intrstr);
|
||||
printf("\n");
|
||||
return 0;
|
||||
}
|
||||
/* copy interesting infos about the chip */
|
||||
sc->siop.features = sc->sc_pp->features;
|
||||
sc->siop.maxburst = sc->sc_pp->maxburst;
|
||||
sc->siop.maxoff = sc->sc_pp->maxoff;
|
||||
sc->siop.clock_div = sc->sc_pp->clock_div;
|
||||
sc->siop.clock_period = sc->sc_pp->clock_period;
|
||||
sc->siop.sc_reset = siop_pci_reset;
|
||||
return 1;
|
||||
}
|
||||
|
||||
void
|
||||
siop_pci_reset(sc)
|
||||
struct siop_softc *sc;
|
||||
{
|
||||
int dmode;
|
||||
|
||||
dmode = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DMODE);
|
||||
if (sc->features & SF_PCI_RL)
|
||||
dmode |= DMODE_ERL;
|
||||
if (sc->features & SF_PCI_RM)
|
||||
dmode |= DMODE_ERMP;
|
||||
if (sc->features & SF_PCI_BOF)
|
||||
dmode |= DMODE_BOF;
|
||||
if (sc->features & SF_PCI_CLS)
|
||||
bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL,
|
||||
bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL) |
|
||||
DCNTL_CLSE);
|
||||
if (sc->features & SF_PCI_WRI)
|
||||
bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3,
|
||||
bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) |
|
||||
CTEST3_WRIE);
|
||||
if (sc->maxburst) {
|
||||
int ctest5 = bus_space_read_1(sc->sc_rt, sc->sc_rh,
|
||||
SIOP_CTEST5);
|
||||
bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4,
|
||||
bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4) &
|
||||
~CTEST4_BDIS);
|
||||
dmode &= ~DMODE_BL_MASK;
|
||||
dmode |= ((sc->maxburst - 1) << DMODE_BL_SHIFT) & DMODE_BL_MASK;
|
||||
ctest5 &= ~CTEST5_BBCK;
|
||||
ctest5 |= (sc->maxburst - 1) & CTEST5_BBCK;
|
||||
bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5, ctest5);
|
||||
} else {
|
||||
bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4,
|
||||
bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4) |
|
||||
CTEST4_BDIS);
|
||||
}
|
||||
bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DMODE, dmode);
|
||||
}
|
||||
59
sys/dev/pci/siop_pci_common.h
Normal file
59
sys/dev/pci/siop_pci_common.h
Normal file
@ -0,0 +1,59 @@
|
||||
/* $NetBSD: siop_pci_common.h,v 1.1 2000/05/15 07:53:18 bouyer Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2000 Manuel Bouyer.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Manuel Bouyer
|
||||
* 4. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/* common functions for the siop and esiop pci front ends */
|
||||
|
||||
/* structure describing each chip */
|
||||
struct siop_product_desc {
|
||||
u_int32_t product;
|
||||
int revision;
|
||||
const char *name;
|
||||
int features; /* features are defined in siopvar.h */
|
||||
u_int8_t maxburst;
|
||||
u_int8_t maxoff; /* maximum supported offset */
|
||||
u_int8_t clock_div; /* clock divider to use for async. logic */
|
||||
u_int8_t clock_period; /* clock period (ns * 10) */
|
||||
};
|
||||
|
||||
const struct siop_product_desc * siop_lookup_product __P((u_int32_t, int));
|
||||
|
||||
/* Driver internal state */
|
||||
struct siop_pci_softc {
|
||||
struct siop_softc siop;
|
||||
pci_chipset_tag_t sc_pc; /* PCI registers info */
|
||||
pcitag_t sc_tag;
|
||||
void *sc_ih; /* PCI interrupt handle */
|
||||
const struct siop_product_desc *sc_pp; /* Adapter description */
|
||||
};
|
||||
|
||||
int siop_pci_attach_common __P((struct siop_pci_softc *,
|
||||
struct pci_attach_args *));
|
||||
void siop_pci_reset __P((struct siop_softc *));
|
||||
Loading…
Reference in New Issue
Block a user