Switch luna68k over to the common m68k vector table.
This commit is contained in:
thorpej
parent
adadcf47c4
commit
a121f918d4
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@ -1,5 +1,5 @@
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#
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# $NetBSD: files.luna68k,v 1.32 2024/01/09 04:16:24 thorpej Exp $
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# $NetBSD: files.luna68k,v 1.33 2024/01/14 00:17:46 thorpej Exp $
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#
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maxpartitions 8
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maxusers 2 8 64
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@ -23,6 +23,7 @@ file arch/m68k/m68k/mmu_subr.s
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file arch/m68k/m68k/pmap_motorola.c
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file arch/m68k/m68k/procfs_machdep.c procfs
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file arch/m68k/m68k/sys_machdep.c
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file arch/m68k/m68k/vectors.c
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file arch/m68k/m68k/vm_machdep.c
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file dev/cons.c
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@ -0,0 +1,50 @@
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/* $NetBSD: vectors.h,v 1.1 2024/01/14 00:17:46 thorpej Exp $ */
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/*-
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* Copyright (c) 2024 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _LUNA68K_VECTORS_H_
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#define _LUNA68K_VECTORS_H_
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#ifdef _KERNEL
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#include <m68k/vectors.h>
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#define MACHINE_AV0_HANDLER spurintr
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#define MACHINE_AV1_HANDLER intrhand_autovec
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#define MACHINE_AV2_HANDLER intrhand_autovec
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#define MACHINE_AV3_HANDLER intrhand_autovec
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#define MACHINE_AV4_HANDLER intrhand_autovec
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#define MACHINE_AV5_HANDLER lev5intr
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#define MACHINE_AV6_HANDLER intrhand_autovec
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#define MACHINE_AV7_HANDLER lev7intr
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#endif /* _KERNEL */
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#endif /* _LUNA68K_VECTORS_H_ */
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@ -1,4 +1,4 @@
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/* $NetBSD: isr.c,v 1.26 2024/01/12 23:36:29 thorpej Exp $ */
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/* $NetBSD: isr.c,v 1.27 2024/01/14 00:17:46 thorpej Exp $ */
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/*-
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* Copyright (c) 1996 The NetBSD Foundation, Inc.
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@ -31,7 +31,7 @@
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: isr.c,v 1.26 2024/01/12 23:36:29 thorpej Exp $");
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__KERNEL_RCSID(0, "$NetBSD: isr.c,v 1.27 2024/01/14 00:17:46 thorpej Exp $");
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/*
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* Link and dispatch interrupts.
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@ -133,51 +133,6 @@ isrlink_autovec(int (*func)(void *), void *arg, int ipl, int priority)
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LIST_INSERT_AFTER(curisr, newisr, isr_link);
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}
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/*
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* Establish a vectored interrupt handler.
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* Called by bus interrupt establish functions.
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*/
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void
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isrlink_vectored(int (*func)(void *), void *arg, int ipl, int vec)
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{
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struct isr_vectored *isr;
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if ((ipl < 0) || (ipl >= NISRAUTOVEC))
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panic("isrlink_vectored: bad ipl %d", ipl);
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if ((vec < ISRVECTORED) || (vec >= ISRVECTORED + NISRVECTORED))
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panic("isrlink_vectored: bad vec 0x%x", vec);
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isr = &isr_vectored[vec - ISRVECTORED];
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if ((vectab[vec] != badtrap) || (isr->isr_func != NULL))
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panic("isrlink_vectored: vec 0x%x not available", vec);
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/* Fill in the new entry. */
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isr->isr_func = func;
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isr->isr_arg = arg;
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isr->isr_ipl = ipl;
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/* Hook into the vector table. */
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vectab[vec] = intrhand_vectored;
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}
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/*
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* Unhook a vectored interrupt.
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*/
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void
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isrunlink_vectored(int vec)
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{
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if ((vec < ISRVECTORED) || (vec >= ISRVECTORED + NISRVECTORED))
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panic("isrunlink_vectored: bad vec 0x%x", vec);
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if (vectab[vec] != intrhand_vectored)
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panic("isrunlink_vectored: not vectored interrupt");
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vectab[vec] = badtrap;
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memset(&isr_vectored[vec - ISRVECTORED], 0, sizeof(struct isr_vectored));
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}
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/*
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* This is the dispatcher called by the low-level
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* assembly language autovectored interrupt routine.
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@ -222,42 +177,6 @@ isrdispatch_autovec(int evec)
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idepth--;
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}
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/*
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* This is the dispatcher called by the low-level
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* assembly language vectored interrupt routine.
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*/
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void
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isrdispatch_vectored(int pc, int evec, void *frame)
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{
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struct isr_vectored *isr;
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int ipl, vec;
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idepth++;
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vec = (evec & 0xfff) >> 2;
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ipl = (getsr() >> 8) & 7;
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intrcnt[ipl]++;
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curcpu()->ci_data.cpu_nintr++;
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if ((vec < ISRVECTORED) || (vec >= (ISRVECTORED + NISRVECTORED)))
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panic("isrdispatch_vectored: bad vec 0x%x", vec);
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isr = &isr_vectored[vec - ISRVECTORED];
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if (isr->isr_func == NULL) {
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printf("isrdispatch_vectored: no handler for vec 0x%x\n", vec);
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vectab[vec] = badtrap;
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idepth--;
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return;
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}
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/*
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* Handler gets exception frame if argument is NULL.
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*/
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if ((*isr->isr_func)(isr->isr_arg ? isr->isr_arg : frame) == 0)
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printf("isrdispatch_vectored: vec 0x%x not claimed\n", vec);
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idepth--;
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}
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bool
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cpu_intr_p(void)
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{
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@ -1,4 +1,4 @@
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/* $NetBSD: isr.h,v 1.4 2009/03/14 14:46:01 dsl Exp $ */
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/* $NetBSD: isr.h,v 1.5 2024/01/14 00:17:46 thorpej Exp $ */
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/*-
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* Copyright (c) 1996 The NetBSD Foundation, Inc.
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@ -79,7 +79,4 @@ struct isr_vectored {
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void isrinit(void);
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void isrlink_autovec(int (*)(void *), void *, int, int);
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void isrlink_vectored(int (*)(void *), void *, int, int);
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void isrunlink_vectored(int);
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void isrdispatch_autovec(int);
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void isrdispatch_vectored(int, int, void *);
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@ -1,4 +1,4 @@
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/* $NetBSD: locore.s,v 1.75 2024/01/12 23:36:29 thorpej Exp $ */
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/* $NetBSD: locore.s,v 1.76 2024/01/14 00:17:46 thorpej Exp $ */
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/*
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* Copyright (c) 1988 University of Utah.
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@ -73,8 +73,6 @@
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.space PAGE_SIZE
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ASLOCAL(tmpstk)
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#include <luna68k/luna68k/vectors.s>
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/*
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* Macro to relocate a symbol, used before MMU is enabled.
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*/
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@ -171,35 +169,6 @@ Lstart1:
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1: movb %a0@+,%a1@+ | copy to bootarg
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dbra %d0,1b | upto 63 characters
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/*
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* Now that we know what CPU we have, initialize the address error
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* and bus error handlers in the vector table:
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*
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* vectab+8 bus error
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* vectab+12 address error
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*/
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lea _C_LABEL(cputype),%a0
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lea _C_LABEL(vectab),%a2
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#if defined(M68040)
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cmpl #CPU_68040,%a0@ | 68040?
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jne 1f | no, skip
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movl #_C_LABEL(buserr40),%a2@(8)
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movl #_C_LABEL(addrerr4060),%a2@(12)
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jra Lstart2
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1:
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#endif
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#if defined(M68030)
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cmpl #CPU_68030,%a0@ | 68030?
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jne 1f | no, skip
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movl #_C_LABEL(busaddrerr2030),%a2@(8)
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movl #_C_LABEL(busaddrerr2030),%a2@(12)
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jra Lstart2
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1:
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#endif
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/* Config botch; no hope. */
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PANIC("Config botch in locore")
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Lstart2:
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/* initialize source/destination control registers for movs */
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moveq #FC_USERD,%d0 | user space
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movc %d0,%sfc | as source
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* Should be running mapped from this point on
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*/
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Lenab1:
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lea _ASM_LABEL(tmpstk),%sp | temporary stack
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lea _ASM_LABEL(tmpstk),%sp | re-load temporary stack
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jbsr _C_LABEL(vec_init) | initialize vector table
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/* call final pmap setup */
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jbsr _C_LABEL(pmap_bootstrap_finalize)
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/* set kernel stack, user SP */
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@ -323,8 +293,6 @@ Lenab2:
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Lenab3:
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/* final setup for C code */
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movl #_C_LABEL(vectab),%d0 | get our %vbr address
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movc %d0,%vbr
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jbsr _C_LABEL(luna68k_init) | additional pre-main initialization
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/*
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@ -595,8 +563,6 @@ Lbrkpt3:
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* For vectored interrupts, we pull the pc, evec, and exception frame
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* and pass them to the vectored interrupt dispatcher. The vectored
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* interrupt dispatcher will deal with strays.
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*
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* _intrhand_vectored is the entry point for vectored interrupts.
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*/
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ENTRY_NOPROFILE(spurintr) /* Level 0 */
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@ -628,18 +594,6 @@ ENTRY_NOPROFILE(lev7intr) /* Level 7: NMI */
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addql #8,%sp | pop SP and stack adjust
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jra _ASM_LABEL(rei) | all done
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ENTRY_NOPROFILE(intrhand_vectored)
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INTERRUPT_SAVEREG
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lea %sp@(16),%a1 | get pointer to frame
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movl %a1,%sp@-
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movw %sp@(26),%d0
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movl %d0,%sp@- | push exception vector info
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movl %sp@(26),%sp@- | and PC
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jbsr _C_LABEL(isrdispatch_vectored) | call dispatcher
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lea %sp@(12),%sp | pop value args
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INTERRUPT_RESTOREREG
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jra _ASM_LABEL(rei) | all done
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#if 1 /* XXX wild timer -- how can I disable/enable the interrupt? */
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ENTRY_NOPROFILE(lev5intr)
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addql #1,_C_LABEL(idepth)
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@ -1,138 +0,0 @@
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| $NetBSD: vectors.s,v 1.4 2013/09/23 17:02:18 tsutsui Exp $
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| Copyright (c) 1997 Jason R. Thorpe. All rights reserved.
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| Copyright (c) 1988 University of Utah
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| Copyright (c) 1990, 1993
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| The Regents of the University of California. All rights reserved.
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|
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| Redistribution and use in source and binary forms, with or without
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| modification, are permitted provided that the following conditions
|
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| are met:
|
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| 1. Redistributions of source code must retain the above copyright
|
||||
| notice, this list of conditions and the following disclaimer.
|
||||
| 2. Redistributions in binary form must reproduce the above copyright
|
||||
| notice, this list of conditions and the following disclaimer in the
|
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| documentation and/or other materials provided with the distribution.
|
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| 3. All advertising materials mentioning features or use of this software
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| must display the following acknowledgement:
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| This product includes software developed by the University of
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| California, Berkeley and its contributors.
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| 4. Neither the name of the University nor the names of its contributors
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| may be used to endorse or promote products derived from this software
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| without specific prior written permission.
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|
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| THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
|
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| ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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| IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
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| ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
|
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| FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
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| DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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| OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
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| HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
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| LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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| OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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| SUCH DAMAGE.
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|
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| @(#)vectors.s 8.2 (Berkeley) 1/21/94
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#define BADTRAP16 \
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VECTOR(badtrap) ; VECTOR(badtrap) ; \
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VECTOR(badtrap) ; VECTOR(badtrap) ; \
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VECTOR(badtrap) ; VECTOR(badtrap) ; \
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VECTOR(badtrap) ; VECTOR(badtrap) ; \
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VECTOR(badtrap) ; VECTOR(badtrap) ; \
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VECTOR(badtrap) ; VECTOR(badtrap) ; \
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VECTOR(badtrap) ; VECTOR(badtrap) ; \
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VECTOR(badtrap) ; VECTOR(badtrap)
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/*
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* bus error and address error vectors are initialized
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* in locore.s once we know our CPU type.
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*/
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.data
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GLOBAL(vectab)
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VECTOR_UNUSED /* 0: (unused reset SSP) */
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VECTOR_UNUSED /* 1: NOT USED (reset PC) */
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VECTOR_UNUSED /* 2: bus error */
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VECTOR_UNUSED /* 3: address error */
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VECTOR(illinst) /* 4: illegal instruction */
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VECTOR(zerodiv) /* 5: zero divide */
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VECTOR(chkinst) /* 6: CHK instruction */
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VECTOR(trapvinst) /* 7: TRAPV instruction */
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VECTOR(privinst) /* 8: privilege violation */
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VECTOR(trace) /* 9: trace */
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VECTOR(illinst) /* 10: line 1010 emulator */
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VECTOR(fpfline) /* 11: line 1111 emulator */
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VECTOR(badtrap) /* 12: unassigned, reserved */
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VECTOR(coperr) /* 13: coprocessor protocol violation */
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VECTOR(fmterr) /* 14: format error */
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VECTOR(badtrap) /* 15: uninitialized interrupt vector */
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VECTOR(badtrap) /* 16: unassigned, reserved */
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VECTOR(badtrap) /* 17: unassigned, reserved */
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VECTOR(badtrap) /* 18: unassigned, reserved */
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VECTOR(badtrap) /* 19: unassigned, reserved */
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VECTOR(badtrap) /* 20: unassigned, reserved */
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VECTOR(badtrap) /* 21: unassigned, reserved */
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VECTOR(badtrap) /* 22: unassigned, reserved */
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VECTOR(badtrap) /* 23: unassigned, reserved */
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VECTOR(spurintr) /* 24: spurious interrupt */
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VECTOR(intrhand_autovec)/* 25: level 1 interrupt autovector */
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VECTOR(intrhand_autovec)/* 26: level 2 interrupt autovector */
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VECTOR(intrhand_autovec)/* 27: level 3 interrupt autovector */
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VECTOR(intrhand_autovec)/* 28: level 4 interrupt autovector */
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VECTOR(lev5intr) /* 29: level 5 interrupt hardwired */
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VECTOR(intrhand_autovec)/* 30: level 6 interrupt autovector */
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VECTOR(lev7intr) /* 31: level 7 interrupt hardwired */
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VECTOR(trap0) /* 32: syscalls */
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#ifdef COMPAT_13
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VECTOR(trap1) /* 33: compat_13_sigreturn */
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#else
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VECTOR(illinst)
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#endif
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VECTOR(trap2) /* 34: trace */
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#ifdef COMPAT_16
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VECTOR(trap3) /* 35: compat_16_sigreturn */
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#else
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VECTOR(illinst)
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#endif
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VECTOR(illinst) /* 36: TRAP instruction vector */
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VECTOR(illinst) /* 37: TRAP instruction vector */
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VECTOR(illinst) /* 38: TRAP instruction vector */
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VECTOR(illinst) /* 39: TRAP instruction vector */
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VECTOR(illinst) /* 40: TRAP instruction vector */
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VECTOR(illinst) /* 41: TRAP instruction vector */
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VECTOR(illinst) /* 42: TRAP instruction vector */
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VECTOR(illinst) /* 43: TRAP instruction vector */
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VECTOR(trap12) /* 44: TRAP instruction vector */
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VECTOR(illinst) /* 45: TRAP instruction vector */
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VECTOR(illinst) /* 46: TRAP instruction vector */
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VECTOR(trap15) /* 47: TRAP instruction vector */
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#ifdef FPSP
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ASVECTOR(bsun) /* 48: FPCP branch/set on unordered cond */
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ASVECTOR(inex) /* 49: FPCP inexact result */
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||||
ASVECTOR(dz) /* 50: FPCP divide by zero */
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||||
ASVECTOR(unfl) /* 51: FPCP underflow */
|
||||
ASVECTOR(operr) /* 52: FPCP operand error */
|
||||
ASVECTOR(ovfl) /* 53: FPCP overflow */
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||||
ASVECTOR(snan) /* 54: FPCP signalling NAN */
|
||||
#else
|
||||
VECTOR(fpfault) /* 48: FPCP branch/set on unordered cond */
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||||
VECTOR(fpfault) /* 49: FPCP inexact result */
|
||||
VECTOR(fpfault) /* 50: FPCP divide by zero */
|
||||
VECTOR(fpfault) /* 51: FPCP underflow */
|
||||
VECTOR(fpfault) /* 52: FPCP operand error */
|
||||
VECTOR(fpfault) /* 53: FPCP overflow */
|
||||
VECTOR(fpfault) /* 54: FPCP signalling NAN */
|
||||
#endif
|
||||
|
||||
VECTOR(fpunsupp) /* 55: FPCP unimplemented data type */
|
||||
VECTOR(badtrap) /* 56: unassigned, reserved */
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||||
VECTOR(badtrap) /* 57: unassigned, reserved */
|
||||
VECTOR(badtrap) /* 58: unassigned, reserved */
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||||
VECTOR(badtrap) /* 59: unassigned, reserved */
|
||||
VECTOR(badtrap) /* 60: unassigned, reserved */
|
||||
VECTOR(badtrap) /* 61: unassigned, reserved */
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||||
VECTOR(badtrap) /* 62: unassigned, reserved */
|
||||
VECTOR(badtrap) /* 63: unassigned, reserved */
|
||||
Loading…
Reference in New Issue