From a121f918d46d3d028290a2fd59a01f9b00d30187 Mon Sep 17 00:00:00 2001 From: thorpej Date: Sun, 14 Jan 2024 00:17:46 +0000 Subject: [PATCH] Switch luna68k over to the common m68k vector table. --- sys/arch/luna68k/conf/files.luna68k | 3 +- sys/arch/luna68k/include/vectors.h | 50 ++++++++++ sys/arch/luna68k/luna68k/isr.c | 85 +---------------- sys/arch/luna68k/luna68k/isr.h | 5 +- sys/arch/luna68k/luna68k/locore.s | 52 +---------- sys/arch/luna68k/luna68k/vectors.s | 138 ---------------------------- 6 files changed, 58 insertions(+), 275 deletions(-) create mode 100644 sys/arch/luna68k/include/vectors.h delete mode 100644 sys/arch/luna68k/luna68k/vectors.s diff --git a/sys/arch/luna68k/conf/files.luna68k b/sys/arch/luna68k/conf/files.luna68k index b981edadc197..de3a244aca76 100644 --- a/sys/arch/luna68k/conf/files.luna68k +++ b/sys/arch/luna68k/conf/files.luna68k @@ -1,5 +1,5 @@ # -# $NetBSD: files.luna68k,v 1.32 2024/01/09 04:16:24 thorpej Exp $ +# $NetBSD: files.luna68k,v 1.33 2024/01/14 00:17:46 thorpej Exp $ # maxpartitions 8 maxusers 2 8 64 @@ -23,6 +23,7 @@ file arch/m68k/m68k/mmu_subr.s file arch/m68k/m68k/pmap_motorola.c file arch/m68k/m68k/procfs_machdep.c procfs file arch/m68k/m68k/sys_machdep.c +file arch/m68k/m68k/vectors.c file arch/m68k/m68k/vm_machdep.c file dev/cons.c diff --git a/sys/arch/luna68k/include/vectors.h b/sys/arch/luna68k/include/vectors.h new file mode 100644 index 000000000000..ab9b7c2ed3ef --- /dev/null +++ b/sys/arch/luna68k/include/vectors.h @@ -0,0 +1,50 @@ +/* $NetBSD: vectors.h,v 1.1 2024/01/14 00:17:46 thorpej Exp $ */ + +/*- + * Copyright (c) 2024 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Jason R. Thorpe. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _LUNA68K_VECTORS_H_ +#define _LUNA68K_VECTORS_H_ + +#ifdef _KERNEL + +#include + +#define MACHINE_AV0_HANDLER spurintr +#define MACHINE_AV1_HANDLER intrhand_autovec +#define MACHINE_AV2_HANDLER intrhand_autovec +#define MACHINE_AV3_HANDLER intrhand_autovec +#define MACHINE_AV4_HANDLER intrhand_autovec +#define MACHINE_AV5_HANDLER lev5intr +#define MACHINE_AV6_HANDLER intrhand_autovec +#define MACHINE_AV7_HANDLER lev7intr + +#endif /* _KERNEL */ + +#endif /* _LUNA68K_VECTORS_H_ */ diff --git a/sys/arch/luna68k/luna68k/isr.c b/sys/arch/luna68k/luna68k/isr.c index dae9065ee868..63888372ee57 100644 --- a/sys/arch/luna68k/luna68k/isr.c +++ b/sys/arch/luna68k/luna68k/isr.c @@ -1,4 +1,4 @@ -/* $NetBSD: isr.c,v 1.26 2024/01/12 23:36:29 thorpej Exp $ */ +/* $NetBSD: isr.c,v 1.27 2024/01/14 00:17:46 thorpej Exp $ */ /*- * Copyright (c) 1996 The NetBSD Foundation, Inc. @@ -31,7 +31,7 @@ #include /* RCS ID & Copyright macro defns */ -__KERNEL_RCSID(0, "$NetBSD: isr.c,v 1.26 2024/01/12 23:36:29 thorpej Exp $"); +__KERNEL_RCSID(0, "$NetBSD: isr.c,v 1.27 2024/01/14 00:17:46 thorpej Exp $"); /* * Link and dispatch interrupts. @@ -133,51 +133,6 @@ isrlink_autovec(int (*func)(void *), void *arg, int ipl, int priority) LIST_INSERT_AFTER(curisr, newisr, isr_link); } -/* - * Establish a vectored interrupt handler. - * Called by bus interrupt establish functions. - */ -void -isrlink_vectored(int (*func)(void *), void *arg, int ipl, int vec) -{ - struct isr_vectored *isr; - - if ((ipl < 0) || (ipl >= NISRAUTOVEC)) - panic("isrlink_vectored: bad ipl %d", ipl); - if ((vec < ISRVECTORED) || (vec >= ISRVECTORED + NISRVECTORED)) - panic("isrlink_vectored: bad vec 0x%x", vec); - - isr = &isr_vectored[vec - ISRVECTORED]; - - if ((vectab[vec] != badtrap) || (isr->isr_func != NULL)) - panic("isrlink_vectored: vec 0x%x not available", vec); - - /* Fill in the new entry. */ - isr->isr_func = func; - isr->isr_arg = arg; - isr->isr_ipl = ipl; - - /* Hook into the vector table. */ - vectab[vec] = intrhand_vectored; -} - -/* - * Unhook a vectored interrupt. - */ -void -isrunlink_vectored(int vec) -{ - - if ((vec < ISRVECTORED) || (vec >= ISRVECTORED + NISRVECTORED)) - panic("isrunlink_vectored: bad vec 0x%x", vec); - - if (vectab[vec] != intrhand_vectored) - panic("isrunlink_vectored: not vectored interrupt"); - - vectab[vec] = badtrap; - memset(&isr_vectored[vec - ISRVECTORED], 0, sizeof(struct isr_vectored)); -} - /* * This is the dispatcher called by the low-level * assembly language autovectored interrupt routine. @@ -222,42 +177,6 @@ isrdispatch_autovec(int evec) idepth--; } -/* - * This is the dispatcher called by the low-level - * assembly language vectored interrupt routine. - */ -void -isrdispatch_vectored(int pc, int evec, void *frame) -{ - struct isr_vectored *isr; - int ipl, vec; - - idepth++; - vec = (evec & 0xfff) >> 2; - ipl = (getsr() >> 8) & 7; - - intrcnt[ipl]++; - curcpu()->ci_data.cpu_nintr++; - - if ((vec < ISRVECTORED) || (vec >= (ISRVECTORED + NISRVECTORED))) - panic("isrdispatch_vectored: bad vec 0x%x", vec); - isr = &isr_vectored[vec - ISRVECTORED]; - - if (isr->isr_func == NULL) { - printf("isrdispatch_vectored: no handler for vec 0x%x\n", vec); - vectab[vec] = badtrap; - idepth--; - return; - } - - /* - * Handler gets exception frame if argument is NULL. - */ - if ((*isr->isr_func)(isr->isr_arg ? isr->isr_arg : frame) == 0) - printf("isrdispatch_vectored: vec 0x%x not claimed\n", vec); - idepth--; -} - bool cpu_intr_p(void) { diff --git a/sys/arch/luna68k/luna68k/isr.h b/sys/arch/luna68k/luna68k/isr.h index 10903b978cbc..64936f333997 100644 --- a/sys/arch/luna68k/luna68k/isr.h +++ b/sys/arch/luna68k/luna68k/isr.h @@ -1,4 +1,4 @@ -/* $NetBSD: isr.h,v 1.4 2009/03/14 14:46:01 dsl Exp $ */ +/* $NetBSD: isr.h,v 1.5 2024/01/14 00:17:46 thorpej Exp $ */ /*- * Copyright (c) 1996 The NetBSD Foundation, Inc. @@ -79,7 +79,4 @@ struct isr_vectored { void isrinit(void); void isrlink_autovec(int (*)(void *), void *, int, int); -void isrlink_vectored(int (*)(void *), void *, int, int); -void isrunlink_vectored(int); void isrdispatch_autovec(int); -void isrdispatch_vectored(int, int, void *); diff --git a/sys/arch/luna68k/luna68k/locore.s b/sys/arch/luna68k/luna68k/locore.s index dfc47e563cdf..0abcd5c81040 100644 --- a/sys/arch/luna68k/luna68k/locore.s +++ b/sys/arch/luna68k/luna68k/locore.s @@ -1,4 +1,4 @@ -/* $NetBSD: locore.s,v 1.75 2024/01/12 23:36:29 thorpej Exp $ */ +/* $NetBSD: locore.s,v 1.76 2024/01/14 00:17:46 thorpej Exp $ */ /* * Copyright (c) 1988 University of Utah. @@ -73,8 +73,6 @@ .space PAGE_SIZE ASLOCAL(tmpstk) -#include - /* * Macro to relocate a symbol, used before MMU is enabled. */ @@ -171,35 +169,6 @@ Lstart1: 1: movb %a0@+,%a1@+ | copy to bootarg dbra %d0,1b | upto 63 characters - /* - * Now that we know what CPU we have, initialize the address error - * and bus error handlers in the vector table: - * - * vectab+8 bus error - * vectab+12 address error - */ - lea _C_LABEL(cputype),%a0 - lea _C_LABEL(vectab),%a2 -#if defined(M68040) - cmpl #CPU_68040,%a0@ | 68040? - jne 1f | no, skip - movl #_C_LABEL(buserr40),%a2@(8) - movl #_C_LABEL(addrerr4060),%a2@(12) - jra Lstart2 -1: -#endif -#if defined(M68030) - cmpl #CPU_68030,%a0@ | 68030? - jne 1f | no, skip - movl #_C_LABEL(busaddrerr2030),%a2@(8) - movl #_C_LABEL(busaddrerr2030),%a2@(12) - jra Lstart2 -1: -#endif - /* Config botch; no hope. */ - PANIC("Config botch in locore") - -Lstart2: /* initialize source/destination control registers for movs */ moveq #FC_USERD,%d0 | user space movc %d0,%sfc | as source @@ -294,7 +263,8 @@ Lmotommu1: * Should be running mapped from this point on */ Lenab1: - lea _ASM_LABEL(tmpstk),%sp | temporary stack + lea _ASM_LABEL(tmpstk),%sp | re-load temporary stack + jbsr _C_LABEL(vec_init) | initialize vector table /* call final pmap setup */ jbsr _C_LABEL(pmap_bootstrap_finalize) /* set kernel stack, user SP */ @@ -323,8 +293,6 @@ Lenab2: Lenab3: /* final setup for C code */ - movl #_C_LABEL(vectab),%d0 | get our %vbr address - movc %d0,%vbr jbsr _C_LABEL(luna68k_init) | additional pre-main initialization /* @@ -595,8 +563,6 @@ Lbrkpt3: * For vectored interrupts, we pull the pc, evec, and exception frame * and pass them to the vectored interrupt dispatcher. The vectored * interrupt dispatcher will deal with strays. - * - * _intrhand_vectored is the entry point for vectored interrupts. */ ENTRY_NOPROFILE(spurintr) /* Level 0 */ @@ -628,18 +594,6 @@ ENTRY_NOPROFILE(lev7intr) /* Level 7: NMI */ addql #8,%sp | pop SP and stack adjust jra _ASM_LABEL(rei) | all done -ENTRY_NOPROFILE(intrhand_vectored) - INTERRUPT_SAVEREG - lea %sp@(16),%a1 | get pointer to frame - movl %a1,%sp@- - movw %sp@(26),%d0 - movl %d0,%sp@- | push exception vector info - movl %sp@(26),%sp@- | and PC - jbsr _C_LABEL(isrdispatch_vectored) | call dispatcher - lea %sp@(12),%sp | pop value args - INTERRUPT_RESTOREREG - jra _ASM_LABEL(rei) | all done - #if 1 /* XXX wild timer -- how can I disable/enable the interrupt? */ ENTRY_NOPROFILE(lev5intr) addql #1,_C_LABEL(idepth) diff --git a/sys/arch/luna68k/luna68k/vectors.s b/sys/arch/luna68k/luna68k/vectors.s deleted file mode 100644 index 4c32a66ed624..000000000000 --- a/sys/arch/luna68k/luna68k/vectors.s +++ /dev/null @@ -1,138 +0,0 @@ -| $NetBSD: vectors.s,v 1.4 2013/09/23 17:02:18 tsutsui Exp $ - -| Copyright (c) 1997 Jason R. Thorpe. All rights reserved. -| Copyright (c) 1988 University of Utah -| Copyright (c) 1990, 1993 -| The Regents of the University of California. All rights reserved. -| -| Redistribution and use in source and binary forms, with or without -| modification, are permitted provided that the following conditions -| are met: -| 1. Redistributions of source code must retain the above copyright -| notice, this list of conditions and the following disclaimer. -| 2. Redistributions in binary form must reproduce the above copyright -| notice, this list of conditions and the following disclaimer in the -| documentation and/or other materials provided with the distribution. -| 3. All advertising materials mentioning features or use of this software -| must display the following acknowledgement: -| This product includes software developed by the University of -| California, Berkeley and its contributors. -| 4. Neither the name of the University nor the names of its contributors -| may be used to endorse or promote products derived from this software -| without specific prior written permission. -| -| THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND -| ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -| IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -| ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE -| FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -| DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -| OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -| HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -| LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -| OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -| SUCH DAMAGE. -| -| @(#)vectors.s 8.2 (Berkeley) 1/21/94 -| - -#define BADTRAP16 \ - VECTOR(badtrap) ; VECTOR(badtrap) ; \ - VECTOR(badtrap) ; VECTOR(badtrap) ; \ - VECTOR(badtrap) ; VECTOR(badtrap) ; \ - VECTOR(badtrap) ; VECTOR(badtrap) ; \ - VECTOR(badtrap) ; VECTOR(badtrap) ; \ - VECTOR(badtrap) ; VECTOR(badtrap) ; \ - VECTOR(badtrap) ; VECTOR(badtrap) ; \ - VECTOR(badtrap) ; VECTOR(badtrap) - - /* - * bus error and address error vectors are initialized - * in locore.s once we know our CPU type. - */ - - .data -GLOBAL(vectab) - VECTOR_UNUSED /* 0: (unused reset SSP) */ - VECTOR_UNUSED /* 1: NOT USED (reset PC) */ - VECTOR_UNUSED /* 2: bus error */ - VECTOR_UNUSED /* 3: address error */ - VECTOR(illinst) /* 4: illegal instruction */ - VECTOR(zerodiv) /* 5: zero divide */ - VECTOR(chkinst) /* 6: CHK instruction */ - VECTOR(trapvinst) /* 7: TRAPV instruction */ - VECTOR(privinst) /* 8: privilege violation */ - VECTOR(trace) /* 9: trace */ - VECTOR(illinst) /* 10: line 1010 emulator */ - VECTOR(fpfline) /* 11: line 1111 emulator */ - VECTOR(badtrap) /* 12: unassigned, reserved */ - VECTOR(coperr) /* 13: coprocessor protocol violation */ - VECTOR(fmterr) /* 14: format error */ - VECTOR(badtrap) /* 15: uninitialized interrupt vector */ - VECTOR(badtrap) /* 16: unassigned, reserved */ - VECTOR(badtrap) /* 17: unassigned, reserved */ - VECTOR(badtrap) /* 18: unassigned, reserved */ - VECTOR(badtrap) /* 19: unassigned, reserved */ - VECTOR(badtrap) /* 20: unassigned, reserved */ - VECTOR(badtrap) /* 21: unassigned, reserved */ - VECTOR(badtrap) /* 22: unassigned, reserved */ - VECTOR(badtrap) /* 23: unassigned, reserved */ - VECTOR(spurintr) /* 24: spurious interrupt */ - VECTOR(intrhand_autovec)/* 25: level 1 interrupt autovector */ - VECTOR(intrhand_autovec)/* 26: level 2 interrupt autovector */ - VECTOR(intrhand_autovec)/* 27: level 3 interrupt autovector */ - VECTOR(intrhand_autovec)/* 28: level 4 interrupt autovector */ - VECTOR(lev5intr) /* 29: level 5 interrupt hardwired */ - VECTOR(intrhand_autovec)/* 30: level 6 interrupt autovector */ - VECTOR(lev7intr) /* 31: level 7 interrupt hardwired */ - VECTOR(trap0) /* 32: syscalls */ -#ifdef COMPAT_13 - VECTOR(trap1) /* 33: compat_13_sigreturn */ -#else - VECTOR(illinst) -#endif - VECTOR(trap2) /* 34: trace */ -#ifdef COMPAT_16 - VECTOR(trap3) /* 35: compat_16_sigreturn */ -#else - VECTOR(illinst) -#endif - VECTOR(illinst) /* 36: TRAP instruction vector */ - VECTOR(illinst) /* 37: TRAP instruction vector */ - VECTOR(illinst) /* 38: TRAP instruction vector */ - VECTOR(illinst) /* 39: TRAP instruction vector */ - VECTOR(illinst) /* 40: TRAP instruction vector */ - VECTOR(illinst) /* 41: TRAP instruction vector */ - VECTOR(illinst) /* 42: TRAP instruction vector */ - VECTOR(illinst) /* 43: TRAP instruction vector */ - VECTOR(trap12) /* 44: TRAP instruction vector */ - VECTOR(illinst) /* 45: TRAP instruction vector */ - VECTOR(illinst) /* 46: TRAP instruction vector */ - VECTOR(trap15) /* 47: TRAP instruction vector */ -#ifdef FPSP - ASVECTOR(bsun) /* 48: FPCP branch/set on unordered cond */ - ASVECTOR(inex) /* 49: FPCP inexact result */ - ASVECTOR(dz) /* 50: FPCP divide by zero */ - ASVECTOR(unfl) /* 51: FPCP underflow */ - ASVECTOR(operr) /* 52: FPCP operand error */ - ASVECTOR(ovfl) /* 53: FPCP overflow */ - ASVECTOR(snan) /* 54: FPCP signalling NAN */ -#else - VECTOR(fpfault) /* 48: FPCP branch/set on unordered cond */ - VECTOR(fpfault) /* 49: FPCP inexact result */ - VECTOR(fpfault) /* 50: FPCP divide by zero */ - VECTOR(fpfault) /* 51: FPCP underflow */ - VECTOR(fpfault) /* 52: FPCP operand error */ - VECTOR(fpfault) /* 53: FPCP overflow */ - VECTOR(fpfault) /* 54: FPCP signalling NAN */ -#endif - - VECTOR(fpunsupp) /* 55: FPCP unimplemented data type */ - VECTOR(badtrap) /* 56: unassigned, reserved */ - VECTOR(badtrap) /* 57: unassigned, reserved */ - VECTOR(badtrap) /* 58: unassigned, reserved */ - VECTOR(badtrap) /* 59: unassigned, reserved */ - VECTOR(badtrap) /* 60: unassigned, reserved */ - VECTOR(badtrap) /* 61: unassigned, reserved */ - VECTOR(badtrap) /* 62: unassigned, reserved */ - VECTOR(badtrap) /* 63: unassigned, reserved */