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Major step in creation of arch/acorn32 : remove acorn RiscPC compatibles

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and RC7500 from the old arch/arm32 that is gonna be deleted in its whole
soon.

IMPORTANT for RC7500 ... this also removes all RC7500 support .... its a
big pitty but was virtually unsupported allready for a few years and noone
had one... if someone wants to make RC7500 or decendants support undo this
removal and start from here.
This commit is contained in:
reinoud 2001-10-17 23:53:29 +00:00
parent 9b2f51421c
commit 9bb6db7a85
147 changed files with 0 additions and 47661 deletions
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275
sys/arch/arm32/conf/A7000
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@ -1,275 +0,0 @@
# $NetBSD: A7000,v 1.46 2001/07/10 20:43:58 bjh21 Exp $
#
# A7000 - Full A7000 configuration
#
include "arch/arm32/conf/std.arm32"
# estimated number of users
maxusers 32
# Standard system options
options RTC_OFFSET=0 # hardware clock is this many mins. west of GMT
#options NTP # NTP phase/frequency locked loop
# CPU options
#options CPU_SA110 # Support the SA110 core
#options CPU_ARM6 # Support the ARM6 core
options CPU_ARM7 # Support the ARM7 core
#options CPU_ARM8 # Support the ARM8 core
#options ARM6_LATE_ABORT # ARM6XX late abort support
# Architecture options
options RISCPC # We are a RiscPC
#options RC7500 # We are a RC7500
# FPA options
#options ARMFPE # ARM Ltd FPE
# File systems
file-system FFS # UFS
#file-system LFS # log-structured file system
file-system MFS # memory file system
file-system NFS # Network file system
file-system ADOSFS # AmigaDOS-compatible file system
file-system EXT2FS # second extended file system (linux)
file-system CD9660 # ISO 9660 + Rock Ridge file system
file-system MSDOSFS # MS-DOS file system
file-system FDESC # /dev/fd
file-system FILECORE # Acorn filecore file system
file-system KERNFS # /kern
file-system NULLFS # loopback file system
file-system PORTAL # portal filesystem (still experimental)
file-system PROCFS # /proc
file-system UMAPFS # NULLFS + uid and gid remapping
file-system UNION # union file system
# File system options
options QUOTA # UFS quotas
options NFSSERVER
# Networking options
options GATEWAY # packet forwarding
options INET # IP + ICMP + TCP + UDP
options INET6 # IPV6
#options IPSEC # IP security
#options IPSEC_ESP # IP security (encryption part; define w/ IPSEC)
#options IPSEC_DEBUG # debug for IP security
#options MROUTING # IP multicast routing
#options NS # XNS
#options NSIP # XNS tunneling over IP
#options ISO,TPIP # OSI
#options EON # OSI tunneling over IP
#options CCITT,LLC,HDLC # X.25
options NETATALK # AppleTalk networking
#options PFIL_HOOKS # pfil(9) packet filter hooks
#options PPP_BSDCOMP # BSD-Compress compression support for PPP
#options PPP_DEFLATE # Deflate compression support for PPP
#options PPP_FILTER # Active filter support for PPP (requires bpf)
#options TCP_DEBUG # Record last TCP_NDEBUG packets with SO_DEBUG
# Compatibility options
#options TCP_COMPAT_42 # 4.2BSD TCP/IP bug compat. Not recommended.
options COMPAT_43 # 4.3BSD compatibility.
options COMPAT_14 # NetBSD 1.4 compatibility.
options COMPAT_13 # NetBSD 1.3 compatibility.
options COMPAT_12 # NetBSD 1.2 compatibility.
#options COMPAT_11 # NetBSD 1.1 compatibility.
#options COMPAT_10 # NetBSD 1.0 compatibility.
#options COMPAT_09 # NetBSD 0.9 compatibility.
# Bootloader options
options COMPAT_OLD_BOOTLOADER
# Shared memory options
options SYSVMSG # System V-like message queues
options SYSVSEM # System V-like semaphores
options SYSVSHM # System V-like memory sharing
options SHMMAXPGS=1024 # 1024 pages is the default
# Device options
options MEMORY_DISK_HOOKS # boottime setup of ramdisk
#options MEMORY_DISK_SIZE=0 # Size in blocks
#options MINIROOTSIZE=3400 # Size in blocks
#options MEMORY_DISK_IS_ROOT # use memory disk as root
# Miscellaneous kernel options
options KTRACE # system call tracing, a la ktrace(1)
options IRQSTATS # manage IRQ statistics
options LKM # loadable kernel modules
options KMEMSTATS # kernel memory statistics
# Development and Debugging options
#options ARM700BUGTRACK # track the ARM700 swi bug
#options PORTMASTER # Enable PortMaster only options
options DIAGNOSTIC # internally consistency checks
#options PMAP_DEBUG # Enable pmap_debug_level code
#options IPKDB # remote kernel debugging
options DDB # in-kernel debugger
#options DDB_HISTORY_SIZE=100 # Enable history editing in DDB
#makeoptions DEBUG="-g" # compile full symbol table
config netbsd root on ? type ?
# serial console ... the conaddr is hardcoded as the pioc address + 4*com offset
# this really be fixed some day
#options COMCONSOLE,CONADDR="0x210000+4*0x3f8",CONUNIT=0,CONSPEED=9600
# The main bus device
mainbus0 at root
# The boot cpu
cpu0 at mainbus?
# The IOMD
iomd0 at mainbus?
# system clock via IOMD
clock* at iomd?
# kbd via IOMD
kbd* at iomd?
# quadrature mouse via IOMD
#qms* at iomd?
# PS2 mouse via IOMD
opms* at iomd?
# IIC bus device
iic* at iomd?
# RTC device via IIC bus
rtc* at iic? addr 0xa0
# time-of-day device via rtc device
todclock0 at rtc?
# VIDC device
vidc0 at mainbus?
# The vidc
vidcconsole0 at vidc?
# generic VT console device
vt0 at vidc?
vt1 at vidc?
vt2 at vidc?
vt3 at vidc?
vt4 at vidc?
vt5 at vidc?
# Peripheral IO Controller
pioc0 at mainbus? base 0x00210000
# IDE disk controller
wdc0 at pioc? offset 0x01f0 irq 9
#wdc* at pioc? offset 0x0170 irq -1
wd* at wdc? channel ? drive ?
atapibus* at wdc? channel ?
cd* at atapibus? drive ?
sd* at atapibus? drive ?
# Floppy disk controller
fdc* at pioc? offset 0x03f0 irq 12 dack 0x2000
fdc* at pioc? offset 0x0370 irq -1 dack 0x2000
fd0 at fdc? drive ?
# Serial ports
com* at pioc? offset 0x03f8 irq 10
#com* at pioc? offset 0x02f8 irq -1
#com* at pioc? offset 0x0338 irq -1
#com* at pioc? offset 0x0238 irq -1
# Parallel ports
lpt* at pioc? offset 0x0278 irq 0
#lpt* at pioc? offset 0x0378 irq -1
#lpt* at pioc? offset 0x03bc irq -1
# Crude sound device
beep0 at vidc?
# Audio device
vidcaudio0 at vidc?
audio* at vidcaudio0
# System beep
sysbeep0 at vidc?
# Podule bus device
podulebus0 at root
asc* at podulebus? # Acorn SCSI card
scsibus* at asc?
cosc* at podulebus? # MCS Connect32 SCSI II card
scsibus* at cosc?
ptsc* at podulebus? # Power-Tec SCSI II card
scsibus* at ptsc?
csc* at podulebus? # Cumana SCSI II card
scsibus* at csc?
oak* at podulebus? # Oak SCSI I card
scsibus* at oak?
csa* at podulebus? # Cumana SCSI I adpater
scsibus* at csa?
hcsc* at podulebus0 slot ? # HCCS 8-bit SCSI interface
scsibus* at hcsc?
sd* at scsibus? target ? lun ? # SCSI disk drives
st* at scsibus? target ? lun ? # SCSI tape drives
cd* at scsibus? target ? lun ? # SCSI CD-ROM drives
ch* at scsibus? target ? lun ? # SCSI auto-changers
uk* at scsibus? target ? lun ? # SCSI unknown device
ss* at scsibus? target ? lun ? # SCSI scanner
icside* at podulebus? # ICS IDE card
wd* at icside? channel ? drive ?
atapibus* at icside? channel ?
rapide* at podulebus? # Yellowstone RapIDE card
wd* at rapide? channel ? drive ?
atapibus* at rapide? channel ?
simide* at podulebus? # Simtec IDE card
wd* at simide? channel ? drive ?
atapibus* at simide? channel ?
amps* at podulebus? # Atomwide Multi-Port Serial card
com* at amps?
ie* at podulebus? # Ether1 podules
ea* at podulebus? # Ether3 podules
eb0 at podulebus? # EtherB network slot cards
ne* at podulebus? # NE2000 clone cards
pseudo-device loop 1 # network loopback
pseudo-device bpfilter 8 # packet filter
pseudo-device sl 2 # CSLIP
pseudo-device ppp 2 # PPP
pseudo-device tun 2 # network tunneling over tty
#pseudo-device ipfilter 1 # ip filter
#pseudo-device strip 4 # STRIP
pseudo-device pty # pseudo-terminals
pseudo-device tb 1 # tablet line discipline
pseudo-device vnd 4 # disk-like interface to files
pseudo-device ccd 2 # concatenated disk devices
pseudo-device md 1 # Ramdisk driver
pseudo-device rnd # /dev/random and /dev/urandom
makeoptions MONITOR="Taxan875+LR"
#makeoptions MONITOR="AKF60"
makeoptions MODES="1024,768,60 1024,768,70 800,600,60 640,480,60 1280,1024 1152,900"

268
sys/arch/arm32/conf/A7INST
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@ -1,268 +0,0 @@
# $NetBSD: A7INST,v 1.35 2001/07/10 20:43:58 bjh21 Exp $
#
# A7INST - A7000 install configuration
#
include "arch/arm32/conf/std.arm32"
# estimated number of users
maxusers 32
# Standard system options
options RTC_OFFSET=0 # hardware clock is this many mins. west of GMT
#options NTP # NTP phase/frequency locked loop
# CPU options
#options CPU_SA110 # Support the SA110 core
#options CPU_ARM6 # Support the ARM6 core
options CPU_ARM7 # Support the ARM7 core
#options CPU_ARM8 # Support the ARM8 core
#options ARM6_LATE_ABORT # ARM6XX late abort support
# Architecture options
options RISCPC # We are a RiscPC
#options RC7500 # We are a RC7500
# FPA options
#options ARMFPE # ARM Ltd FPE
# File systems
file-system FFS # UFS
#file-system LFS # log-structured file system
#file-system MFS # memory file system
file-system NFS # Network file system
#file-system ADOSFS # AmigaDOS-compatible file system
#file-system EXT2FS # second extended file system (linux)
file-system CD9660 # ISO 9660 + Rock Ridge file system
file-system MSDOSFS # MS-DOS file system
#file-system FDESC # /dev/fd
file-system FILECORE # Acorn filecore file system
file-system KERNFS # /kern
#file-system NULLFS # loopback file system
#file-system PORTAL # portal filesystem (still experimental)
#file-system PROCFS # /proc
#file-system UMAPFS # NULLFS + uid and gid remapping
#file-system UNION # union file system
# File system options
#options QUOTA # UFS quotas
#options NFSSERVER
# Networking options
#options GATEWAY # packet forwarding
options INET # IP + ICMP + TCP + UDP
#options MROUTING # IP multicast routing
#options NS # XNS
#options NSIP # XNS tunneling over IP
#options ISO,TPIP # OSI
#options EON # OSI tunneling over IP
#options CCITT,LLC,HDLC # X.25
#options NETATALK # AppleTalk networking
#options PFIL_HOOKS # pfil(9) packet filter hooks
#options PPP_BSDCOMP # BSD-Compress compression support for PPP
#options PPP_DEFLATE # Deflate compression support for PPP
#options PPP_FILTER # Active filter support for PPP (requires bpf)
#options TCP_DEBUG # Record last TCP_NDEBUG packets with SO_DEBUG
# Compatibility options
#options TCP_COMPAT_42 # 4.2BSD TCP/IP bug compat. Not recommended.
#options COMPAT_43 # 4.3BSD compatibility.
options COMPAT_14 # NetBSD 1.4 compatibility.
options COMPAT_13 # NetBSD 1.3 compatibility.
options COMPAT_12 # NetBSD 1.2 compatibility.
#options COMPAT_11 # NetBSD 1.1 compatibility.
#options COMPAT_10 # NetBSD 1.0 compatibility.
#options COMPAT_09 # NetBSD 0.9 compatibility.
# Bootloader options
options COMPAT_OLD_BOOTLOADER
# Shared memory options
#options SYSVMSG # System V-like message queues
#options SYSVSEM # System V-like semaphores
#options SYSVSHM # System V-like memory sharing
#options SHMMAXPGS=1024 # 1024 pages is the default
# Device options
options MEMORY_DISK_HOOKS # boottime setup of ramdisk
#options MEMORY_DISK_SIZE=0 # Size in blocks
options MINIROOTSIZE=3800 # Size in blocks
options MEMORY_DISK_IS_ROOT # use memory disk as root
# Miscellaneous kernel options
#options KTRACE # system call tracing, a la ktrace(1)
#options IRQSTATS # manage IRQ statistics
#options LKM # loadable kernel modules
options KMEMSTATS # kernel memory statistics
# Development and Debugging options
#options ARM700BUGTRACK # track the ARM700 swi bug
#options PORTMASTER # Enable PortMaster only options
options DIAGNOSTIC # internally consistency checks
#options PMAP_DEBUG # Enable pmap_debug_level code
#options IPKDB # remote kernel debugging
options DDB # in-kernel debugger
#options DDB_HISTORY_SIZE=100 # Enable history editing in DDB
#makeoptions DEBUG="-g" # compile full symbol table
config netbsd root on ? type ffs
# serial console ... the conaddr is hardcoded as the pioc address + 4*com offset
# this really be fixed some day
#options COMCONSOLE,CONADDR="0x210000+4*0x3f8",CONUNIT=0,CONSPEED=9600
# The main bus device
mainbus0 at root
# The boot cpu
cpu0 at mainbus?
# The IOMD
iomd0 at mainbus?
# system clock via IOMD
clock* at iomd?
# kbd via IOMD
kbd* at iomd?
# quadrature mouse via IOMD
#qms* at iomd?
# PS2 mouse via IOMD
opms* at iomd?
# IIC bus device
iic* at iomd?
# RTC device via IIC bus
rtc* at iic? addr 0xa0
# time-of-day device via rtc device
todclock0 at rtc?
# VIDC device
vidc0 at mainbus?
# The vidc
vidcconsole0 at vidc?
# generic VT console device
vt0 at vidc?
vt1 at vidc?
vt2 at vidc?
vt3 at vidc?
vt4 at vidc?
vt5 at vidc?
# Peripheral IO Controller
pioc0 at mainbus? base 0x00210000
# IDE disk controller
wdc0 at pioc? offset 0x01f0 irq 9
#wdc* at pioc? offset 0x0170 irq -1
wd* at wdc? channel ? drive ?
atapibus* at wdc? channel ?
cd* at atapibus? drive ?
sd* at atapibus? drive ?
# Floppy disk controller
fdc* at pioc? offset 0x03f0 irq 12 dack 0x2000
fdc* at pioc? offset 0x0370 irq -1 dack 0x2000
fd0 at fdc? drive ?
# Serial ports
com* at pioc? offset 0x03f8 irq 10
#com* at pioc? offset 0x02f8 irq -1
#com* at pioc? offset 0x0338 irq -1
#com* at pioc? offset 0x0238 irq -1
# Parallel ports
lpt* at pioc? offset 0x0278 irq 0
#lpt* at pioc? offset 0x0378 irq -1
#lpt* at pioc? offset 0x03bc irq -1
# Crude sound device
beep0 at vidc?
# Audio device
#vidcaudio0 at vidc?
#audio* at vidcaudio0
# System beep
sysbeep0 at vidc?
# Podule bus device
podulebus0 at root
asc* at podulebus? # Acorn SCSI card
scsibus* at asc?
cosc* at podulebus? # MCS Connect32 SCSI II card
scsibus* at cosc?
ptsc* at podulebus? # Power-Tec SCSI II card
scsibus* at ptsc?
csc* at podulebus? # Cumana SCSI II card
scsibus* at csc?
oak* at podulebus? # Oak SCSI I card
scsibus* at oak?
csa* at podulebus? # Cumana SCSI I adpater
scsibus* at csa?
hcsc* at podulebus0 slot ? # HCCS 8-bit SCSI interface
scsibus* at hcsc?
sd* at scsibus? target ? lun ? # SCSI disk drives
st* at scsibus? target ? lun ? # SCSI tape drives
cd* at scsibus? target ? lun ? # SCSI CD-ROM drives
#ch* at scsibus? target ? lun ? # SCSI auto-changers
#uk* at scsibus? target ? lun ? # SCSI unknown device
#ss* at scsibus? target ? lun ? # SCSI scanner
icside* at podulebus? # ICS IDE card
wd* at icside? channel ? drive ?
atapibus* at icside? channel ?
rapide* at podulebus? # Yellowstone RapIDE card
wd* at rapide? channel ? drive ?
atapibus* at rapide? channel ?
simide* at podulebus? # Simtec IDE card
wd* at simide? channel ? drive ?
atapibus* at simide? channel ?
ie* at podulebus? # Ether1 podules
ea* at podulebus? # Ether3 podules
eb0 at podulebus? # EtherB network slot cards
ne* at podulebus? # NE2000 clone cards
pseudo-device loop 1 # network loopback
#pseudo-device bpfilter 8 # packet filter
#pseudo-device sl 2 # CSLIP
#pseudo-device ppp 2 # PPP
#pseudo-device tun 2 # network tunneling over tty
#pseudo-device ipfilter 1 # ip filter
#pseudo-device strip 4 # STRIP
pseudo-device pty # pseudo-terminals
#pseudo-device tb 1 # tablet line discipline
pseudo-device vnd 4 # disk-like interface to files
pseudo-device ccd 2 # concatenated disk devices
pseudo-device md 1 # Ramdisk driver
#pseudo-device rnd # /dev/random and /dev/urandom
makeoptions MONITOR="Taxan875+LR"
#makeoptions MONITOR="AKF60"
makeoptions MODES="1024,768,60 1024,768,70 800,600,60 640,480,60 1280,1024 1152,900"

300
sys/arch/arm32/conf/GENERIC
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@ -1,300 +0,0 @@
# $NetBSD: GENERIC,v 1.86 2001/09/01 23:08:41 atatat Exp $
#
# GENERIC -- everything that's currently supported
#
include "arch/arm32/conf/std.arm32"
#ident "GENERIC-$Revision: 1.86 $"
# estimated number of users
maxusers 32
# Standard system options
options RTC_OFFSET=0 # hardware clock is this many mins. west of GMT
#options NTP # NTP phase/frequency locked loop
# CPU options
options CPU_SA110 # Support the SA110 core
options CPU_ARM6 # Support the ARM6 core
options CPU_ARM7 # Support the ARM7 core
options CPU_ARM8 # Support the ARM8 core
#options ARM6_LATE_ABORT # ARM6XX late abort support
# Architecture options
options RISCPC # We are a RiscPC
#options RC7500 # We are a RC7500
# FPA options
#options ARMFPE # ARM Ltd FPE
# File systems
file-system FFS # UFS
#file-system LFS # log-structured file system
file-system MFS # memory file system
file-system NFS # Network file system
file-system ADOSFS # AmigaDOS-compatible file system
file-system EXT2FS # second extended file system (linux)
file-system CD9660 # ISO 9660 + Rock Ridge file system
file-system MSDOSFS # MS-DOS file system
file-system FDESC # /dev/fd
file-system FILECORE # Acorn filecore file system
file-system KERNFS # /kern
file-system NULLFS # loopback file system
file-system OVERLAY # overlay filesystem
file-system PORTAL # portal filesystem (still experimental)
file-system PROCFS # /proc
file-system UMAPFS # NULLFS + uid and gid remapping
file-system UNION # union file system
# File system options
options QUOTA # UFS quotas
#options FFS_EI # FFS Endian Independant support
options SOFTDEP # FFS soft updates support.
options NFSSERVER
# Networking options
options GATEWAY # packet forwarding
options INET # IP + ICMP + TCP + UDP
options INET6 # IPV6
#options IPSEC # IP security
#options IPSEC_ESP # IP security (encryption part; define w/IPSEC)
#options IPSEC_DEBUG # debug for IP security
#options MROUTING # IP multicast routing
options NS # XNS
#options NSIP # XNS tunneling over IP
options ISO,TPIP # OSI
#options EON # OSI tunneling over IP
options CCITT,LLC,HDLC # X.25
options NETATALK # AppleTalk networking
options PFIL_HOOKS # pfil(9) packet filter hooks
options PPP_BSDCOMP # BSD-Compress compression support for PPP
options PPP_DEFLATE # Deflate compression support for PPP
options PPP_FILTER # Active filter support for PPP (requires bpf)
#options TCP_DEBUG # Record last TCP_NDEBUG packets with SO_DEBUG
# Compatibility options
#options TCP_COMPAT_42 # 4.2BSD TCP/IP bug compat. Not recommended.
options COMPAT_43 # 4.3BSD compatibility.
options COMPAT_14 # NetBSD 1.4 compatibility.
options COMPAT_13 # NetBSD 1.3 compatibility.
options COMPAT_12 # NetBSD 1.2 compatibility.
#options COMPAT_11 # NetBSD 1.1 compatibility.
#options COMPAT_10 # NetBSD 1.0 compatibility.
#options COMPAT_09 # NetBSD 0.9 compatibility.
# Bootloader options
options COMPAT_OLD_BOOTLOADER
# Shared memory options
options SYSVMSG # System V-like message queues
options SYSVSEM # System V-like semaphores
#options SEMMNI=10 # number of semaphore identifiers
#options SEMMNS=60 # number of semaphores in system
#options SEMUME=10 # max number of undo entries per process
#options SEMMNU=30 # number of undo structures in system
options SYSVSHM # System V-like memory sharing
options SHMMAXPGS=1024 # 1024 pages is the default
# Device options
options MEMORY_DISK_HOOKS # boottime setup of ramdisk
#options MEMORY_DISK_SIZE=0 # Size in blocks
#options MINIROOTSIZE=3400 # Size in blocks
#options MEMORY_DISK_IS_ROOT # use memory disk as root
# Miscellaneous kernel options
options KTRACE # system call tracing, a la ktrace(1)
options IRQSTATS # manage IRQ statistics
options LKM # loadable kernel modules
options KMEMSTATS # kernel memory statistics
#options SCSIVERBOSE # Verbose SCSI errors
# Development and Debugging options
#options ARM700BUGTRACK # track the ARM700 swi bug
#options PORTMASTER # Enable PortMaster only options
options DIAGNOSTIC # internal consistency checks
#options PMAP_DEBUG # Enable pmap_debug_level code
#options IPKDB # remote kernel debugging
options DDB # in-kernel debugger
#options DDB_HISTORY_SIZE=100 # Enable history editing in DDB
#makeoptions DEBUG="-g" # compile full symbol table
config netbsd root on ? type ?
# serial console ... the conaddr is hardcoded as the pioc address + 4*com offset
# this really be fixed some day
#options COMCONSOLE,CONADDR="0x210000+4*0x3f8",CONUNIT=0,CONSPEED=9600
# The main bus device
mainbus0 at root
# The boot cpu
cpu0 at mainbus?
# The IOMD
iomd0 at mainbus?
# system clock via IOMD
clock* at iomd?
# kbd via IOMD
kbd* at iomd?
# quadrature mouse via IOMD
qms* at iomd?
# PS2 mouse via IOMD
opms* at iomd?
# IIC bus device
iic* at iomd?
# RTC device via IIC bus
rtc* at iic? addr 0xa0
# time-of-day device via rtc device
todclock0 at rtc?
# VIDC device
vidc0 at mainbus?
# The vidc
vidcconsole0 at vidc?
# generic VT console device
vt0 at vidc?
vt1 at vidc?
vt2 at vidc?
vt3 at vidc?
vt4 at vidc?
vt5 at vidc?
# Peripheral IO Controller
pioc0 at mainbus? base 0x00210000
# IDE disk controller
wdc0 at pioc? offset 0x01f0 irq 9
#wdc* at pioc? offset 0x0170 irq -1
wd* at wdc? channel ? drive ?
atapibus* at wdc? channel ?
cd* at atapibus? drive ?
sd* at atapibus? drive ?
# Floppy disk controller
fdc* at pioc? offset 0x03f0 irq 12 dack 0x2000
fdc* at pioc? offset 0x0370 irq -1 dack 0x2000
fd0 at fdc? drive ?
# Serial ports
com* at pioc? offset 0x03f8 irq 10
#com* at pioc? offset 0x02f8 irq -1
#com* at pioc? offset 0x0338 irq -1
#com* at pioc? offset 0x0238 irq -1
# Parallel ports
lpt* at pioc? offset 0x0278 irq 0
#lpt* at pioc? offset 0x0378 irq -1
#lpt* at pioc? offset 0x03bc irq -1
# Crude sound device
beep0 at vidc?
# Audio device
vidcaudio0 at vidc?
audio* at vidcaudio0
# System beep
sysbeep0 at vidc?
# Podule bus device
podulebus0 at root
asc* at podulebus? # Acorn SCSI card
scsibus* at asc?
cosc* at podulebus? # MCS Connect32 SCSI II card
scsibus* at cosc?
ptsc* at podulebus? # Power-Tec SCSI II card
scsibus* at ptsc?
csc* at podulebus? # Cumana SCSI II card
scsibus* at csc?
oak* at podulebus? # Oak SCSI I card
scsibus* at oak?
csa* at podulebus? # Cumana SCSI I adpater
scsibus* at csa?
hcsc* at podulebus0 slot ? # HCCS 8-bit SCSI interface
scsibus* at hcsc?
sd* at scsibus? target ? lun ? # SCSI disk drives
st* at scsibus? target ? lun ? # SCSI tape drives
cd* at scsibus? target ? lun ? # SCSI CD-ROM drives
ch* at scsibus? target ? lun ? # SCSI auto-changers
uk* at scsibus? target ? lun ? # SCSI unknown device
ss* at scsibus? target ? lun ? # SCSI scanner
dtide* at podulebus? # D.T. Software IDE card
wd* at dtide? channel ? drive ?
atapibus* at dtide? channel ?
hcide* at podulebus? # HCCS IDE card
wd* at hcide? channel ? drive ?
atapibus* at hcide? channel ?
icside* at podulebus? # ICS IDE card
wd* at icside? channel ? drive ?
atapibus* at icside? channel ?
rapide* at podulebus? # Yellowstone RapIDE card
wd* at rapide? channel ? drive ?
atapibus* at rapide? channel ?
simide* at podulebus? # Simtec IDE card
wd* at simide? channel ? drive ?
atapibus* at simide? channel ?
amps* at podulebus? # Atomwide Multi-Port Serial card
com* at amps?
ie* at podulebus? # Ether1 podules
ea* at podulebus? # Ether3 podules
eb0 at podulebus? # EtherB network slot cards
ne* at podulebus? # NE2000 clone cards
pseudo-device loop 1 # network loopback
pseudo-device bpfilter 8 # packet filter
pseudo-device sl 2 # CSLIP
pseudo-device ppp 2 # PPP
pseudo-device tun 2 # network tunneling over tty
#pseudo-device gre 2 # generic L3 over IP tunnel
#pseudo-device ipfilter 1 # ip filter
pseudo-device gif 4 # IPv[46] over IPv[46] tunnel (RFC1933)
#pseudo-device faith 1 # IPv[46] tcp relay translation i/f
#pseudo-device stf 1 # 6to4 IPv6 over IPv4 encapsulation
#pseudo-device strip 4 # STarmode Radio IP (Metricon Ricochet)
pseudo-device vlan # IEEE 802.1q encapsulation
#pseudo-device bridge # simple inter-network bridging
pseudo-device pty # pseudo-terminals
pseudo-device tb 1 # tablet line discipline
pseudo-device vnd 4 # disk-like interface to files
pseudo-device ccd 2 # concatenated disk devices
#pseudo-device raid 4 # RAIDframe disk driver
#options RAID_AUTOCONFIG # auto-configuration of RAID components
pseudo-device md 1 # Ramdisk driver
pseudo-device rnd # /dev/random and in-kernel generator
makeoptions MONITOR="Taxan875+LR"
#makeoptions MONITOR="AKF60"
makeoptions MODES="1024,768,60 1024,768,70 800,600,60 640,480,60 1280,1024 1152,900"

283
sys/arch/arm32/conf/NC
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@ -1,283 +0,0 @@
# $NetBSD: NC,v 1.6 2001/07/10 20:43:58 bjh21 Exp $
#
# NC - with vidcconsole
#
include "arch/arm32/conf/std.arm32"
# estimated number of users
maxusers 16
# Standard system options
options RTC_OFFSET=0 # hardware clock is this many mins. west of GMT
#options NTP # NTP phase/frequency locked loop
# CPU options
#options CPU_SA110 # Support the SA110 core
#options CPU_ARM6 # Support the ARM6 core
options CPU_ARM7 # Support the ARM7 core
#options CPU_ARM8 # Support the ARM8 core
#options ARM6_LATE_ABORT # ARM6XX late abort support
# Architecture options
options RISCPC # We are a RiscPC
#options RC7500 # We are a RC7500
options NC
# FPA options
#options ARMFPE # ARM Ltd FPE
# File systems
#file-system FFS # UFS
#file-system LFS # log-structured file system
file-system MFS # memory file system
file-system NFS # Network file system
#file-system ADOSFS # AmigaDOS-compatible file system
#file-system EXT2FS # second extended file system (linux)
#file-system CD9660 # ISO 9660 + Rock Ridge file system
#file-system MSDOSFS # MS-DOS file system
#file-system FDESC # /dev/fd
#file-system FILECORE # Acorn filecore file system
file-system KERNFS # /kern
#file-system NULLFS # loopback file system
#file-system PORTAL # portal filesystem (still experimental)
file-system PROCFS # /proc
#file-system UMAPFS # NULLFS + uid and gid remapping
#file-system UNION # union file system
# File system options
#options QUOTA # UFS quotas
#options NFSSERVER
# Networking options
#options GATEWAY # packet forwarding
#options INET6 # IPV6
#options IPSEC # IP security
#options IPSEC_ESP # IP security (encryption part; define w/ IPSEC)
#options IPSEC_DEBUG # debug for IP security
options INET # IP + ICMP + TCP + UDP
#options MROUTING # IP multicast routing
#options NS # XNS
#options NSIP # XNS tunneling over IP
#options ISO,TPIP # OSI
#options EON # OSI tunneling over IP
#options CCITT,LLC,HDLC # X.25
#options NETATALK # AppleTalk networking
#options PFIL_HOOKS # pfil(9) packet filter hooks
#options PPP_BSDCOMP # BSD-Compress compression support for PPP
#options PPP_DEFLATE # Deflate compression support for PPP
#options PPP_FILTER # Active filter support for PPP (requires bpf)
#options TCP_DEBUG # Record last TCP_NDEBUG packets with SO_DEBUG
# Compatibility options
options COMPAT_43 # 4.3BSD compatibility.
options COMPAT_14 # NetBSD 1.4 compatibility.
#options COMPAT_13 # NetBSD 1.3 compatibility.
#options COMPAT_12 # NetBSD 1.2 compatibility.
#options COMPAT_11 # NetBSD 1.1 compatibility.
#options COMPAT_10 # NetBSD 1.0 compatibility.
#options COMPAT_09 # NetBSD 0.9 compatibility.
#options TCP_COMPAT_42 # 4.2BSD TCP/IP bug compat. Not recommended.
# Bootloader options
#options COMPAT_OLD_BOOTLOADER
# Shared memory options
options SYSVMSG # System V-like message queues
options SYSVSEM # System V-like semaphores
options SYSVSHM # System V-like memory sharing
options SHMMAXPGS=1024 # 1024 pages is the default
# Device options
options MEMORY_DISK_HOOKS # boottime setup of ramdisk
#options MEMORY_DISK_SIZE=0 # Size in blocks
#options MINIROOTSIZE=3400 # Size in blocks
#options MEMORY_DISK_IS_ROOT # use memory disk as root
# Miscellaneous kernel options
options KTRACE # system call tracing, a la ktrace(1)
options IRQSTATS # manage IRQ statistics
#options LKM # loadable kernel modules
options KMEMSTATS # kernel memory statistics
# Development and Debugging options
#options ARM700BUGTRACK # track the ARM700 swi bug
#options PORTMASTER # Enable PortMaster only options
options DIAGNOSTIC # internally consistency checks
#options PMAP_DEBUG # Enable pmap_debug_level code
#options IPKDB # remote kernel debugging
#options DDB # in-kernel debugger
#options DDB_HISTORY_SIZE=100 # Enable history editing in DDB
#makeoptions DEBUG="-g" # compile full symbol table
config netbsd root on ne0 type nfs
options NFS_BOOT_DHCP
#options NFS_BOOTPARAM
# serial console ... the conaddr is hardcoded as the pioc address + 4*com offset
# this really be fixed some day
#options COMCONSOLE,CONADDR="0x210000+4*0x3f8",CONUNIT=0,CONSPEED=9600
# The main bus device
mainbus0 at root
# The boot cpu
cpu0 at mainbus?
# The IOMD
iomd0 at mainbus?
# system clock via IOMD
clock* at iomd?
# kbd via IOMD
kbd* at iomd?
# quadrature mouse via IOMD
#qms* at iomd?
# PS2 mouse via IOMD
opms* at iomd?
# IIC bus device
iic* at iomd?
# RTC device via IIC bus
rtc* at iic? addr 0xa0
# time-of-day device via rtc device
todclock0 at rtc?
# VIDC device
vidc0 at mainbus?
# The vidc
vidcconsole0 at vidc?
# generic VT console device
vt0 at vidc?
vt1 at vidc?
#vt2 at vidc?
#vt3 at vidc?
#vt4 at vidc?
#vt5 at vidc?
# Peripheral IO Controller
pioc0 at mainbus? base 0x00210000
# IDE disk controller
#wdc0 at pioc? offset 0x01f0 irq 9
#wdc* at pioc? offset 0x0170 irq -1
#wd* at wdc? channel ? drive ?
#atapibus* at wdc? channel ?
#cd* at atapibus? drive ?
#sd* at atapibus? drive ?
# Floppy disk controller
#fdc* at pioc? offset 0x03f0 irq 12 dack 0x2000
#fdc* at pioc? offset 0x0370 irq -1 dack 0x2000
#fd0 at fdc? drive ?
# Serial ports
#com* at pioc? offset 0x03f8 irq 10
#com* at pioc? offset 0x02f8 irq -1
#com* at pioc? offset 0x0338 irq -1
#com* at pioc? offset 0x0238 irq -1
# Parallel ports
lpt* at pioc? offset 0x0278 irq 0
#lpt* at pioc? offset 0x0378 irq -1
#lpt* at pioc? offset 0x03bc irq -1
# Crude sound device
beep0 at vidc?
# Audio device
vidcaudio0 at vidc?
audio* at vidcaudio0
# System beep
sysbeep0 at vidc?
# Podule bus device
podulebus0 at root
#asc* at podulebus? # Acorn SCSI card
#scsibus* at asc?
#cosc* at podulebus? # MCS Connect32 SCSI II card
#scsibus* at cosc?
#ptsc* at podulebus? # Power-Tec SCSI II card
#scsibus* at ptsc?
#csc* at podulebus? # Cumana SCSI II card
#scsibus* at csc?
#oak* at podulebus? # Oak SCSI I card
#scsibus* at oak?
#csa* at podulebus? # Cumana SCSI I adpater
#scsibus* at csa?
#hcsc* at podulebus0 slot ? # HCCS 8-bit SCSI interface
#scsibus* at hcsc?
#sd* at scsibus? target ? lun ? # SCSI disk drives
#st* at scsibus? target ? lun ? # SCSI tape drives
#cd* at scsibus? target ? lun ? # SCSI CD-ROM drives
#ch* at scsibus? target ? lun ? # SCSI auto-changers
#uk* at scsibus? target ? lun ? # SCSI unknown device
#ss* at scsibus? target ? lun ? # SCSI scanner
#icside* at podulebus? # ICS IDE card
#wd* at icside? channel ? drive ?
#atapibus* at icside? channel ?
#rapide* at podulebus? # Yellowstone RapIDE card
#wd* at rapide? channel ? drive ?
#atapibus* at rapide? channel ?
#simide* at podulebus? # Simtec IDE card
#wd* at simide? channel ? drive ?
#atapibus* at simide? channel ?
#amps* at podulebus? # Atomwide Multi-Port Serial card
#com* at amps?
#ie* at podulebus? # Ether1 podules
#ea* at podulebus? # Ether3 podules
#eb0 at podulebus? # EtherB network slot cards
ne* at podulebus? # NE2000 clone cards
pseudo-device loop 1 # network loopback
#pseudo-device bpfilter 8 # packet filter
#pseudo-device sl 2 # CSLIP
#pseudo-device ppp 2 # PPP
#pseudo-device tun 2 # network tunneling over tty
#pseudo-device ipfilter 1 # ip filter
#pseudo-device strip 4 # STRIP
pseudo-device pty # pseudo-terminals
#pseudo-device tb 1 # tablet line discipline
pseudo-device vnd 4 # disk-like interface to files
#pseudo-device ccd 2 # concatenated disk devices
pseudo-device md 1 # Ramdisk driver
pseudo-device rnd # /dev/random and /dev/urandom
#makeoptions MONITOR="Taxan875+LR"
makeoptions MONITOR="AKF85"
makeoptions MODES="640,480,70"
#makeoptions MODES="800,600,60"
#makeoptions MONITOR="PALTV"
#makeoptions MODES="640,256,60 640,480,60 1024,768,60 1024,768,70 800,600,60 1280,1024 1152,900"

309
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@ -1,309 +0,0 @@
# $NetBSD: NC_WSCONS,v 1.7 2001/07/10 20:43:58 bjh21 Exp $
#
# NC - with wscons
#
include "arch/arm32/conf/std.arm32"
# estimated number of users
maxusers 16
# Standard system options
options RTC_OFFSET=0 # hardware clock is this many mins. west of GMT
#options NTP # NTP phase/frequency locked loop
# CPU options
#options CPU_SA110 # Support the SA110 core
#options CPU_ARM6 # Support the ARM6 core
options CPU_ARM7 # Support the ARM7 core
#options CPU_ARM8 # Support the ARM8 core
#options ARM6_LATE_ABORT # ARM6XX late abort support
# Architecture options
options RISCPC # We are a RiscPC
#options RC7500 # We are a RC7500
options NC
# FPA options
#options ARMFPE # ARM Ltd FPE
# File systems
#file-system FFS # UFS
#file-system LFS # log-structured file system
file-system MFS # memory file system
file-system NFS # Network file system
#file-system ADOSFS # AmigaDOS-compatible file system
#file-system EXT2FS # second extended file system (linux)
#file-system CD9660 # ISO 9660 + Rock Ridge file system
#file-system MSDOSFS # MS-DOS file system
#file-system FDESC # /dev/fd
#file-system FILECORE # Acorn filecore file system
file-system KERNFS # /kern
#file-system NULLFS # loopback file system
#file-system PORTAL # portal filesystem (still experimental)
file-system PROCFS # /proc
#file-system UMAPFS # NULLFS + uid and gid remapping
#file-system UNION # union file system
# File system options
#options QUOTA # UFS quotas
#options NFSSERVER
# Networking options
#options GATEWAY # packet forwarding
#options INET6 # IPV6
#options IPSEC # IP security
#options IPSEC_ESP # IP security (encryption part; define w/ IPSEC)
#options IPSEC_DEBUG # debug for IP security
options INET # IP + ICMP + TCP + UDP
#options MROUTING # IP multicast routing
#options NS # XNS
#options NSIP # XNS tunneling over IP
#options ISO,TPIP # OSI
#options EON # OSI tunneling over IP
#options CCITT,LLC,HDLC # X.25
#options NETATALK # AppleTalk networking
#options PFIL_HOOKS # pfil(9) packet filter hooks
#options PPP_BSDCOMP # BSD-Compress compression support for PPP
#options PPP_DEFLATE # Deflate compression support for PPP
#options PPP_FILTER # Active filter support for PPP (requires bpf)
#options TCP_DEBUG # Record last TCP_NDEBUG packets with SO_DEBUG
# Compatibility options
options COMPAT_43 # 4.3BSD compatibility.
options COMPAT_14 # NetBSD 1.4 compatibility.
#options COMPAT_13 # NetBSD 1.3 compatibility.
#options COMPAT_12 # NetBSD 1.2 compatibility.
#options COMPAT_11 # NetBSD 1.1 compatibility.
#options COMPAT_10 # NetBSD 1.0 compatibility.
#options COMPAT_09 # NetBSD 0.9 compatibility.
#options TCP_COMPAT_42 # 4.2BSD TCP/IP bug compat. Not recommended.
# Bootloader options
#options COMPAT_OLD_BOOTLOADER
# Shared memory options
options SYSVMSG # System V-like message queues
options SYSVSEM # System V-like semaphores
options SYSVSHM # System V-like memory sharing
options SHMMAXPGS=1024 # 1024 pages is the default
# Device options
options MEMORY_DISK_HOOKS # boottime setup of ramdisk
#options MEMORY_DISK_SIZE=0 # Size in blocks
#options MINIROOTSIZE=3400 # Size in blocks
#options MEMORY_DISK_IS_ROOT # use memory disk as root
# Miscellaneous kernel options
options KTRACE # system call tracing, a la ktrace(1)
options IRQSTATS # manage IRQ statistics
#options LKM # loadable kernel modules
options KMEMSTATS # kernel memory statistics
# Development and Debugging options
#options ARM700BUGTRACK # track the ARM700 swi bug
#options PORTMASTER # Enable PortMaster only options
options DIAGNOSTIC # internally consistency checks
#options PMAP_DEBUG # Enable pmap_debug_level code
#options IPKDB # remote kernel debugging
#options DDB # in-kernel debugger
#options DDB_HISTORY_SIZE=100 # Enable history editing in DDB
#makeoptions DEBUG="-g" # compile full symbol table
config netbsd root on ne0 type nfs
options NFS_BOOT_DHCP
#options NFS_BOOTPARAM
# serial console ... the conaddr is hardcoded as the pioc address + 4*com offset
# this really be fixed some day
#options COMCONSOLE,CONADDR="0x210000+4*0x3f8",CONUNIT=0,CONSPEED=9600
# The main bus device
mainbus0 at root
# The boot cpu
cpu0 at mainbus?
# The IOMD
iomd0 at mainbus?
# system clock via IOMD
clock* at iomd?
# quadrature mouse via IOMD
#qms* at iomd?
# IIC bus device
iic* at iomd?
# RTC device via IIC bus
rtc* at iic? addr 0xa0
# time-of-day device via rtc device
todclock0 at rtc?
# VIDC device
vidc0 at mainbus?
# WSCONS
# ws console uses DUMB, SUN or VT100 terminal emulation
#options WSEMUL_NODUMB
#options WSEMUL_SUN
options WSEMUL_VT100
#options FONT_BOLD8x16
#options FONT_GALLANT12x22 # Very nice font
#options FONT_LUCIDA16x29
#options FONT_OMRON12x20 # looks funny
#options FONT_QVSS8x15 # broken ?
#options FONT_SONY12x25 # looks like VT220 font
#options FONT_SONY8x16 # not tested
options FONT_VT220L8x8 # 8x8 font as in Arch. cons
#options FONT_VT220L8x16 # 8x(2x8) font as in Arch. cons
#options FONT_VT220L8x10 # not tested
#options FONT_VT220L8x20 # not tested
vidcvideo0 at vidc? # wscons driver for VIDC
wsdisplay* at vidcvideo? console ? # display itself
rpckbd* at iomd? # based on old `kbd' driver
wskbd* at rpckbd? # wskbd on RiscPC keyboard
pseudo-device wsmux 2 # why 2 ?
# The origional vidcconsole :
# vidcconsole kbd at IOMD
# vidcconsole PS2 mouse at IOMD
#vidcconsole0 at vidc? # display + vt100 emulation
#kbd* at iomd? # PS/2 keyboard for vidcconsole
#opms* at iomd? # RiscPC mouse for vidcconsole
# generic VT console device
#vt0 at vidc?
#vt1 at vidc?
#vt2 at vidc?
#vt3 at vidc?
#vt4 at vidc?
#vt5 at vidc?
# Peripheral IO Controller
pioc0 at mainbus? base 0x00210000
# IDE disk controller
#wdc0 at pioc? offset 0x01f0 irq 9
#wdc* at pioc? offset 0x0170 irq -1
#wd* at wdc? channel ? drive ?
#atapibus* at wdc? channel ?
#cd* at atapibus? drive ?
#sd* at atapibus? drive ?
# Floppy disk controller
#fdc* at pioc? offset 0x03f0 irq 12 dack 0x2000
#fdc* at pioc? offset 0x0370 irq -1 dack 0x2000
#fd0 at fdc? drive ?
# Serial ports
#com* at pioc? offset 0x03f8 irq 10
#com* at pioc? offset 0x02f8 irq -1
#com* at pioc? offset 0x0338 irq -1
#com* at pioc? offset 0x0238 irq -1
# Parallel ports
lpt* at pioc? offset 0x0278 irq 0
#lpt* at pioc? offset 0x0378 irq -1
#lpt* at pioc? offset 0x03bc irq -1
# Crude sound device
beep0 at vidc?
# Audio device
vidcaudio0 at vidc?
audio* at vidcaudio0
# System beep
sysbeep0 at vidc?
# Podule bus device
podulebus0 at root
#asc* at podulebus? # Acorn SCSI card
#scsibus* at asc?
#cosc* at podulebus? # MCS Connect32 SCSI II card
#scsibus* at cosc?
#ptsc* at podulebus? # Power-Tec SCSI II card
#scsibus* at ptsc?
#csc* at podulebus? # Cumana SCSI II card
#scsibus* at csc?
#oak* at podulebus? # Oak SCSI I card
#scsibus* at oak?
#csa* at podulebus? # Cumana SCSI I adpater
#scsibus* at csa?
#hcsc* at podulebus0 slot ? # HCCS 8-bit SCSI interface
#scsibus* at hcsc?
#sd* at scsibus? target ? lun ? # SCSI disk drives
#st* at scsibus? target ? lun ? # SCSI tape drives
#cd* at scsibus? target ? lun ? # SCSI CD-ROM drives
#ch* at scsibus? target ? lun ? # SCSI auto-changers
#uk* at scsibus? target ? lun ? # SCSI unknown device
#ss* at scsibus? target ? lun ? # SCSI scanner
#icside* at podulebus? # ICS IDE card
#wd* at icside? channel ? drive ?
#atapibus* at icside? channel ?
#rapide* at podulebus? # Yellowstone RapIDE card
#wd* at rapide? channel ? drive ?
#atapibus* at rapide? channel ?
#simide* at podulebus? # Simtec IDE card
#wd* at simide? channel ? drive ?
#atapibus* at simide? channel ?
#amps* at podulebus? # Atomwide Multi-Port Serial card
#com* at amps?
#ie* at podulebus? # Ether1 podules
#ea* at podulebus? # Ether3 podules
#eb0 at podulebus? # EtherB network slot cards
ne* at podulebus? # NE2000 clone cards
pseudo-device loop 1 # network loopback
#pseudo-device bpfilter 8 # packet filter
#pseudo-device sl 2 # CSLIP
#pseudo-device ppp 2 # PPP
#pseudo-device tun 2 # network tunneling over tty
#pseudo-device ipfilter 1 # ip filter
#pseudo-device strip 4 # STRIP
pseudo-device pty # pseudo-terminals
#pseudo-device tb 1 # tablet line discipline
pseudo-device vnd 4 # disk-like interface to files
#pseudo-device ccd 2 # concatenated disk devices
pseudo-device md 1 # Ramdisk driver
pseudo-device rnd # /dev/random and /dev/urandom
#makeoptions MONITOR="Taxan875+LR"
makeoptions MONITOR="AKF85"
makeoptions MODES="640,480,70"
#makeoptions MODES="800,600,60"
#makeoptions MONITOR="PALTV"
#makeoptions MODES="640,256,60 640,480,60 1024,768,60 1024,768,70 800,600,60 1280,1024 1152,900"

219
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@ -1,219 +0,0 @@
# $NetBSD: RC7500,v 1.36 2001/07/10 20:43:59 bjh21 Exp $
#
# RC7500 - Config for the VLSI RC7500 board
#
# THIS CONFIG IS CURRENTLY BROKEN AND IS LIKELY TO REMAIN
# SO UNTIL A RC7500 IS OBTAINED
#
include "arch/arm32/conf/std.arm32"
# estimated number of users
maxusers 32
# Standard system options
options RTC_OFFSET=0 # hardware clock is this many mins. west of GMT
#options NTP # NTP phase/frequency locked loop
# CPU options
#options CPU_SA110 # Support the SA110 core
#options CPU_ARM6 # Support the ARM6 core
options CPU_ARM7 # Support the ARM7 core
#options CPU_ARM8 # Support the ARM8 core
#options ARM6_LATE_ABORT # ARM6XX late abort support
# Architecture options
options IOMD # We have an IOMD
#options RISCPC # We are a RiscPC
options RC7500 # ARM7500
# FPA options
#options ARMFPE # ARM Ltd FPE
# File system options
file-system FFS # UFS
#file-system LFS # log-structured file system
#file-system MFS # memory file system
file-system NFS # Network file system
#file-system ADOSFS # AmigaDOS-compatible file system
#file-system EXT2FS # second extended file system (linux)
file-system CD9660 # ISO 9660 + Rock Ridge file system
file-system MSDOSFS # MS-DOS file system
file-system FDESC # /dev/fd
file-system FILECORE # Acorn filecore file system
file-system KERNFS # /kern
#file-system NULLFS # loopback file system
#file-system PORTAL # ?
#file-system PROCFS # /proc
#file-system UMAPFS # NULLFS + uid and gid remapping
#file-system UNION # union file system
# File system options
#options QUOTA # UFS quotas
options NFSSERVER
# Networking options
#options GATEWAY # packet forwarding
options INET # IP + ICMP + TCP + UDP
options INET6 # IPV6
#options IPSEC # IP security
#options IPSEC_ESP # IP security (encryption part; define w/ IPSEC)
#options IPSEC_DEBUG # debug for IP security
#options MROUTING # IP multicast routing
#options NS # XNS
#options NSIP # XNS tunneling over IP
#options ISO,TPIP # OSI
#options EON # OSI tunneling over IP
#options CCITT,LLC,HDLC # X.25
#options NETATALK # AppleTalk networking
#options PFIL_HOOKS # pfil(9) packet filter hooks
#options PPP_BSDCOMP # BSD-Compress compression support for PPP
#options PPP_DEFLATE # Deflate compression support for PPP
#options PPP_FILTER # Active filter support for PPP (requires bpf)
#options TCP_DEBUG # Record last TCP_NDEBUG packets with SO_DEBUG
# Compatibility options
options COMPAT_43 # 4.3BSD compatibility.
options COMPAT_14 # NetBSD 1.4 compatibility.
options COMPAT_13 # NetBSD 1.3 compatibility.
options COMPAT_12 # NetBSD 1.2 compatibility.
#options COMPAT_11 # NetBSD 1.1 compatibility.
#options COMPAT_10 # NetBSD 1.0 compatibility.
#options COMPAT_09 # NetBSD 0.9 compatibility.
#options TCP_COMPAT_42 # 4.2BSD TCP/IP bug compat. Not recommended.
# Shared memory options
options SYSVMSG # System V-like message queues
options SYSVSEM # System V-like semaphores
options SYSVSHM # System V-like memory sharing
options SHMMAXPGS=1024 # 1024 pages is the default
# Device options
options MEMORY_DISK_HOOKS # boottime setup of ramdisk
#options MEMORY_DISK_SIZE=0 # Size in blocks
#options MINIROOTSIZE=3400 # Size in blocks
#options MEMORY_DISK_IS_ROOT # use memory disk as root
# Miscellaneous kernel options
options KTRACE # system call tracing, a la ktrace(1)
#options IRQSTATS # manage IRQ statistics
options LKM # loadable kernel modules
options KMEMSTATS # kernel memory statistics
# Development and Debugging options
#options ARM700BUGTRACK # track the ARM700 swi bug
#options PORTMASTER # Enable PortMaster only options
#options DIAGNOSTIC # internally consistency checks
#options PMAP_DEBUG # Enable pmap_debug_level code
#options IPKDB # remote kernel debugging
options DDB # in-kernel debugger
#options DDB_HISTORY_SIZE=100 # Enable history editing in DDB
#makeoptions DEBUG="-g" # compile full symbol table
#options PROM_DEBUG # Used for bootstrap debugging the RC7500
config netbsd root on ? type ?
# The main bus device
mainbus0 at root
# The boot cpu
cpu0 at mainbus?
# The IOMD
iomd0 at mainbus?
# VIDC device
vidc0 at mainbus?
# The vidc
vidcconsole0 at vidc?
# generic VT console device
vt0 at vidc?
vt1 at vidc?
vt2 at vidc?
vt3 at vidc?
vt4 at vidc?
vt5 at vidc?
# IDE disk controller
#wdc0 at mainbus? base 0x002107c0 irq 9
#wdc0 at mainbus? base 0x0022B000 irq 23
#wd* at wdc? channel ? drive ?
#atapibus* at wdc? channel ?
#cd* at atapibus? drive ?
#sd* at atapibus? drive ?
# Floppy disk controller
#fdc0 at mainbus? base 0x00210fc0 irq 12 dack 0x00002000
#fd0 at fdc? drive ?
#fd1 at fdc? drive ?
# kbd via IOMD
kbd* at iomd?
# pms mouse
opms* at iomd?
# quadrature mouse
#qms* at iomd?
# Serial ports
#com0 at mainbus? base 0x00210fe0 irq 13
#com1 at mainbus? base 0x00210be0
# Parallel ports; requires INET
#lpt0 at mainbus? base 0x002109e0 irq 0
#
# RC7500 companded audio device
#
#vidcaudio0 at vidc?
#audio* at vidcaudio0
# Crude sound device
#beep0 at vidc? irq 31
# System beep
sysbeep0 at vidc?
# IIC bus device
iic* at iomd?
# RTC device
rtc0 at iic? addr 0xa0
# time-of-day device
todclock0 at rtc?
es0 at mainbus? base 0x0022B800 irq 11 # On board SMC 91C92 ethernet controller
pseudo-device loop 1 # network loopback
pseudo-device bpfilter 8 # packet filter
#pseudo-device sl 2 # CSLIP
#pseudo-device ppp 2 # PPP
#pseudo-device tun 2 # network tunneling over tty
#pseudo-device ipfilter 1 # ip filter
#pseudo-device strip 4 # STRIP
pseudo-device pty # pseudo-terminals
#pseudo-device tb 1 # tablet line discipline
pseudo-device vnd 4 # disk-like interface to files
#pseudo-device ccd 2 # concatenated disk devices
pseudo-device md 1 # Memory disk driver
pseudo-device rnd # /dev/random and /dev/urandom
#options HARDCODEDMODES
makeoptions MONITOR="Taxan875+LR"
#makeoptions MONITOR="AKF60"
#makeoptions MODES="1024,768,60 1024,768,70 800,600,60 640,480,60 1280,1024 1152,900"
makeoptions MODES="640,480,60 800,600,60 1024,768,60 1024,768,70 1152,900"

278
sys/arch/arm32/conf/RISCPC
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@ -1,278 +0,0 @@
# $NetBSD: RISCPC,v 1.37 2001/07/10 20:43:59 bjh21 Exp $
#
# RISCPC -- Full RiscPC config
#
include "arch/arm32/conf/std.arm32"
# estimated number of users
maxusers 32
# Standard system options
options RTC_OFFSET=0 # hardware clock is this many mins. west of GMT
#options NTP # NTP phase/frequency locked loop
# CPU options
options CPU_SA110 # Support the SA110 core
options CPU_ARM6 # Support the ARM6 core
options CPU_ARM7 # Support the ARM7 core
#options CPU_ARM8 # Support the ARM8 core
#options ARM6_LATE_ABORT # ARM6XX late abort support
# For StrongARM only kernels
#makeoptions COPTS="-O2 -march=armv3m -mtune=strongarm"
# Architecture options
options RISCPC # We are a RiscPC
#options RC7500 # We are a RC7500
# FPA options
#options ARMFPE # ARM Ltd FPE
# File systems
file-system FFS # UFS
#file-system LFS # log-structured file system
file-system MFS # memory file system
file-system NFS # Network file system
file-system ADOSFS # AmigaDOS-compatible file system
file-system EXT2FS # second extended file system (linux)
file-system CD9660 # ISO 9660 + Rock Ridge file system
file-system MSDOSFS # MS-DOS file system
file-system FDESC # /dev/fd
file-system FILECORE # Acorn filecore file system
file-system KERNFS # /kern
file-system NULLFS # loopback file system
file-system PORTAL # portal filesystem (still experimental)
file-system PROCFS # /proc
file-system UMAPFS # NULLFS + uid and gid remapping
file-system UNION # union file system
# File system options
options QUOTA # UFS quotas
options NFSSERVER
# Networking options
options GATEWAY # packet forwarding
options INET # IP + ICMP + TCP + UDP
options INET6 # IPV6
#options IPSEC # IP security
#options IPSEC_ESP # IP security (encryption part; define w/ IPSEC)
#options IPSEC_DEBUG # debug for IP security
#options MROUTING # IP multicast routing
#options NS # XNS
#options NSIP # XNS tunneling over IP
#options ISO,TPIP # OSI
#options EON # OSI tunneling over IP
#options CCITT,LLC,HDLC # X.25
options NETATALK # AppleTalk networking
#options PFIL_HOOKS # pfil(9) packet filter hooks
#options PPP_BSDCOMP # BSD-Compress compression support for PPP
#options PPP_DEFLATE # Deflate compression support for PPP
#options PPP_FILTER # Active filter support for PPP (requires bpf)
#options TCP_DEBUG # Record last TCP_NDEBUG packets with SO_DEBUG
# Compatibility options
options COMPAT_43 # 4.3BSD compatibility.
options COMPAT_14 # NetBSD 1.4 compatibility.
options COMPAT_13 # NetBSD 1.3 compatibility.
options COMPAT_12 # NetBSD 1.2 compatibility.
#options COMPAT_11 # NetBSD 1.1 compatibility.
#options COMPAT_10 # NetBSD 1.0 compatibility.
#options COMPAT_09 # NetBSD 0.9 compatibility.
#options TCP_COMPAT_42 # 4.2BSD TCP/IP bug compat. Not recommended.
# Bootloader options
options COMPAT_OLD_BOOTLOADER
# Shared memory options
options SYSVMSG # System V-like message queues
options SYSVSEM # System V-like semaphores
options SYSVSHM # System V-like memory sharing
options SHMMAXPGS=1024 # 1024 pages is the default
# Device options
options MEMORY_DISK_HOOKS # boottime setup of ramdisk
#options MEMORY_DISK_SIZE=0 # Size in blocks
#options MINIROOTSIZE=3400 # Size in blocks
#options MEMORY_DISK_IS_ROOT # use memory disk as root
# Miscellaneous kernel options
options KTRACE # system call tracing, a la ktrace(1)
options IRQSTATS # manage IRQ statistics
options LKM # loadable kernel modules
options KMEMSTATS # kernel memory statistics
# Development and Debugging options
#options ARM700BUGTRACK # track the ARM700 swi bug
#options PORTMASTER # Enable PortMaster only options
options DIAGNOSTIC # internally consistency checks
#options PMAP_DEBUG # Enable pmap_debug_level code
#options IPKDB # remote kernel debugging
options DDB # in-kernel debugger
#options DDB_HISTORY_SIZE=100 # Enable history editing in DDB
#makeoptions DEBUG="-g" # compile full symbol table
config netbsd root on ? type ?
# serial console ... the conaddr is hardcoded as the pioc address + 4*com offset
# this really be fixed some day
#options COMCONSOLE,CONADDR="0x210000+4*0x3f8",CONUNIT=0,CONSPEED=9600
# The main bus device
mainbus0 at root
# The boot cpu
cpu0 at mainbus?
# The IOMD
iomd0 at mainbus?
# system clock via IOMD
clock* at iomd?
# kbd via IOMD
kbd* at iomd?
# quadrature mouse via IOMD
qms* at iomd?
# PS2 mouse via IOMD
opms* at iomd?
# IIC bus device
iic* at iomd?
# RTC device via IIC bus
rtc* at iic? addr 0xa0
# time-of-day device via rtc device
todclock0 at rtc?
# VIDC device
vidc0 at mainbus?
# The vidc
vidcconsole0 at vidc?
# generic VT console device
vt0 at vidc?
vt1 at vidc?
vt2 at vidc?
vt3 at vidc?
vt4 at vidc?
vt5 at vidc?
# Peripheral IO Controller
pioc0 at mainbus? base 0x00210000
# IDE disk controller
wdc0 at pioc? offset 0x01f0 irq 9
#wdc* at pioc? offset 0x0170 irq -1
wd* at wdc? channel ? drive ?
atapibus* at wdc? channel ?
cd* at atapibus? drive ?
sd* at atapibus? drive ?
# Floppy disk controller
fdc* at pioc? offset 0x03f0 irq 12 dack 0x2000
fdc* at pioc? offset 0x0370 irq -1 dack 0x2000
fd0 at fdc? drive ?
# Serial ports
com* at pioc? offset 0x03f8 irq 10
#com* at pioc? offset 0x02f8 irq -1
#com* at pioc? offset 0x0338 irq -1
#com* at pioc? offset 0x0238 irq -1
# Parallel ports
lpt* at pioc? offset 0x0278 irq 0
#lpt* at pioc? offset 0x0378 irq -1
#lpt* at pioc? offset 0x03bc irq -1
# Crude sound device
beep0 at vidc?
# Audio device
vidcaudio0 at vidc?
audio* at vidcaudio0
# System beep
sysbeep0 at vidc?
# Podule bus device
podulebus0 at root
asc* at podulebus? # Acorn SCSI card
scsibus* at asc?
cosc* at podulebus? # MCS Connect32 SCSI II card
scsibus* at cosc?
ptsc* at podulebus? # Power-Tec SCSI II card
scsibus* at ptsc?
csc* at podulebus? # Cumana SCSI II card
scsibus* at csc?
oak* at podulebus? # Oak SCSI I card
scsibus* at oak?
csa* at podulebus? # Cumana SCSI I adpater
scsibus* at csa?
hcsc* at podulebus0 slot ? # HCCS 8-bit SCSI interface
scsibus* at hcsc?
sd* at scsibus? target ? lun ? # SCSI disk drives
st* at scsibus? target ? lun ? # SCSI tape drives
cd* at scsibus? target ? lun ? # SCSI CD-ROM drives
ch* at scsibus? target ? lun ? # SCSI auto-changers
uk* at scsibus? target ? lun ? # SCSI unknown device
ss* at scsibus? target ? lun ? # SCSI scanner
icside* at podulebus? # ICS IDE card
wd* at icside? channel ? drive ?
atapibus* at icside? channel ?
rapide* at podulebus? # Yellowstone RapIDE card
wd* at rapide? channel ? drive ?
atapibus* at rapide? channel ?
simide* at podulebus? # Simtec IDE card
wd* at simide? channel ? drive ?
atapibus* at simide? channel ?
amps* at podulebus? # Atomwide Multi-Port Serial card
com* at amps?
ie* at podulebus? # Ether1 podules
ea* at podulebus? # Ether3 podules
eb0 at podulebus? # EtherB network slot cards
ne* at podulebus? # NE2000 clone cards
pseudo-device loop 1 # network loopback
pseudo-device bpfilter 8 # packet filter
pseudo-device sl 2 # CSLIP
pseudo-device ppp 2 # PPP
pseudo-device tun 2 # network tunneling over tty
#pseudo-device ipfilter 1 # ip filter
#pseudo-device strip 4 # STRIP
pseudo-device pty # pseudo-terminals
pseudo-device tb 1 # tablet line discipline
pseudo-device vnd 4 # disk-like interface to files
pseudo-device ccd 2 # concatenated disk devices
pseudo-device md 1 # Ramdisk driver
pseudo-device rnd # /dev/random and /dev/urandom
makeoptions MONITOR="Taxan875+LR"
#makeoptions MONITOR="AKF60"
makeoptions MODES="1024,768,60 1024,768,70 800,600,60 640,480,60 1280,1024 1152,900"

268
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@ -1,268 +0,0 @@
# $NetBSD: RPCINST,v 1.34 2001/07/10 20:43:59 bjh21 Exp $
#
# RPCINST -- RiscPC install configuration
#
include "arch/arm32/conf/std.arm32"
# estimated number of users
maxusers 32
# Standard system options
options RTC_OFFSET=0 # hardware clock is this many mins. west of GMT
#options NTP # NTP phase/frequency locked loop
# CPU options
options CPU_SA110 # Support the SA110 core
options CPU_ARM6 # Support the ARM6 core
options CPU_ARM7 # Support the ARM7 core
#options CPU_ARM8 # Support the ARM8 core
#options ARM6_LATE_ABORT # ARM6XX late abort support
# Architecture options
options RISCPC # We are a RiscPC
#options RC7500 # We are a RC7500
# FPA options
#options ARMFPE # ARM Ltd FPE
# File systems
file-system FFS # UFS
#file-system LFS # log-structured file system
#file-system MFS # memory file system
file-system NFS # Network file system
#file-system ADOSFS # AmigaDOS-compatible file system
#file-system EXT2FS # second extended file system (linux)
file-system CD9660 # ISO 9660 + Rock Ridge file system
file-system MSDOSFS # MS-DOS file system
#file-system FDESC # /dev/fd
file-system FILECORE # Acorn filecore file system
file-system KERNFS # /kern
#file-system NULLFS # loopback file system
#file-system PORTAL # portal filesystem (still experimental)
#file-system PROCFS # /proc
#file-system UMAPFS # NULLFS + uid and gid remapping
#file-system UNION # union file system
# File system options
#options QUOTA # UFS quotas
#options NFSSERVER
# Networking options
#options GATEWAY # packet forwarding
options INET # IP + ICMP + TCP + UDP
#options MROUTING # IP multicast routing
#options NS # XNS
#options NSIP # XNS tunneling over IP
#options ISO,TPIP # OSI
#options EON # OSI tunneling over IP
#options CCITT,LLC,HDLC # X.25
#options NETATALK # AppleTalk networking
#options PFIL_HOOKS # pfil(9) packet filter hooks
#options PPP_BSDCOMP # BSD-Compress compression support for PPP
#options PPP_DEFLATE # Deflate compression support for PPP
#options PPP_FILTER # Active filter support for PPP (requires bpf)
#options TCP_DEBUG # Record last TCP_NDEBUG packets with SO_DEBUG
# Compatibility options
#options COMPAT_43 # 4.3BSD compatibility.
options COMPAT_14 # NetBSD 1.4 compatibility.
options COMPAT_13 # NetBSD 1.3 compatibility.
options COMPAT_12 # NetBSD 1.2 compatibility.
#options COMPAT_11 # NetBSD 1.1 compatibility.
#options COMPAT_10 # NetBSD 1.0 compatibility.
#options COMPAT_09 # NetBSD 0.9 compatibility.
#options TCP_COMPAT_42 # 4.2BSD TCP/IP bug compat. Not recommended.
# Bootloader options
options COMPAT_OLD_BOOTLOADER
# Shared memory options
#options SYSVMSG # System V-like message queues
#options SYSVSEM # System V-like semaphores
#options SYSVSHM # System V-like memory sharing
#options SHMMAXPGS=1024 # 1024 pages is the default
# Device options
options MEMORY_DISK_HOOKS # boottime setup of ramdisk
#options MEMORY_DISK_SIZE=0 # Size in blocks
options MINIROOTSIZE=3800 # Size in blocks
options MEMORY_DISK_IS_ROOT # use memory disk as root
# Miscellaneous kernel options
#options KTRACE # system call tracing, a la ktrace(1)
#options IRQSTATS # manage IRQ statistics
#options LKM # loadable kernel modules
options KMEMSTATS # kernel memory statistics
# Development and Debugging options
#options ARM700BUGTRACK # track the ARM700 swi bug
#options PORTMASTER # Enable PortMaster only options
options DIAGNOSTIC # internally consistency checks
#options PMAP_DEBUG # Enable pmap_debug_level code
#options IPKDB # remote kernel debugging
options DDB # in-kernel debugger
#options DDB_HISTORY_SIZE=100 # Enable history editing in DDB
#makeoptions DEBUG="-g" # compile full symbol table
config netbsd root on ? type ffs
# serial console ... the conaddr is hardcoded as the pioc address + 4*com offset
# this really be fixed some day
#options COMCONSOLE,CONADDR="0x210000+4*0x3f8",CONUNIT=0,CONSPEED=9600
# The main bus device
mainbus0 at root
# The boot cpu
cpu0 at mainbus?
# The IOMD
iomd0 at mainbus?
# system clock via IOMD
clock* at iomd?
# kbd via IOMD
kbd* at iomd?
# quadrature mouse via IOMD
qms* at iomd?
# PS2 mouse via IOMD
opms* at iomd?
# IIC bus device
iic* at iomd?
# RTC device via IIC bus
rtc* at iic? addr 0xa0
# time-of-day device via rtc device
todclock0 at rtc?
# VIDC device
vidc0 at mainbus?
# The vidc
vidcconsole0 at vidc?
# generic VT console device
vt0 at vidc?
vt1 at vidc?
vt2 at vidc?
vt3 at vidc?
vt4 at vidc?
vt5 at vidc?
# Peripheral IO Controller
pioc0 at mainbus? base 0x00210000
# IDE disk controller
wdc0 at pioc? offset 0x01f0 irq 9
#wdc* at pioc? offset 0x0170 irq -1
wd* at wdc? channel ? drive ?
atapibus* at wdc? channel ?
cd* at atapibus? drive ?
sd* at atapibus? drive ?
# Floppy disk controller
fdc* at pioc? offset 0x03f0 irq 12 dack 0x2000
fdc* at pioc? offset 0x0370 irq -1 dack 0x2000
fd0 at fdc? drive ?
# Serial ports
com* at pioc? offset 0x03f8 irq 10
#com* at pioc? offset 0x02f8 irq -1
#com* at pioc? offset 0x0338 irq -1
#com* at pioc? offset 0x0238 irq -1
# Parallel ports
lpt* at pioc? offset 0x0278 irq 0
#lpt* at pioc? offset 0x0378 irq -1
#lpt* at pioc? offset 0x03bc irq -1
# Crude sound device
beep0 at vidc?
# Audio device
#vidcaudio0 at vidc?
#audio* at vidcaudio0
# System beep
sysbeep0 at vidc?
# Podule bus device
podulebus0 at root
asc* at podulebus? # Acorn SCSI card
scsibus* at asc?
cosc* at podulebus? # MCS Connect32 SCSI II card
scsibus* at cosc?
ptsc* at podulebus? # Power-Tec SCSI II card
scsibus* at ptsc?
csc* at podulebus? # Cumana SCSI II card
scsibus* at csc?
oak* at podulebus? # Oak SCSI I card
scsibus* at oak?
csa* at podulebus? # Cumana SCSI I adpater
scsibus* at csa?
hcsc* at podulebus0 slot ? # HCCS 8-bit SCSI interface
scsibus* at hcsc?
sd* at scsibus? target ? lun ? # SCSI disk drives
st* at scsibus? target ? lun ? # SCSI tape drives
cd* at scsibus? target ? lun ? # SCSI CD-ROM drives
#ch* at scsibus? target ? lun ? # SCSI auto-changers
#uk* at scsibus? target ? lun ? # SCSI unknown device
#ss* at scsibus? target ? lun ? # SCSI scanner
icside* at podulebus? # ICS IDE card
wd* at icside? channel ? drive ?
atapibus* at icside? channel ?
rapide* at podulebus? # Yellowstone RapIDE card
wd* at rapide? channel ? drive ?
atapibus* at rapide? channel ?
simide* at podulebus? # Simtec IDE card
wd* at simide? channel ? drive ?
atapibus* at simide? channel ?
ie* at podulebus? # Ether1 podules
ea* at podulebus? # Ether3 podules
eb0 at podulebus? # EtherB network slot cards
ne* at podulebus? # NE2000 clone cards
pseudo-device loop 1 # network loopback
#pseudo-device bpfilter 8 # packet filter
#pseudo-device sl 2 # CSLIP
#pseudo-device ppp 2 # PPP
#pseudo-device tun 2 # network tunneling over tty
#pseudo-device ipfilter 1 # ip filter
#pseudo-device strip 4 # STRIP
pseudo-device pty # pseudo-terminals
#pseudo-device tb 1 # tablet line discipline
pseudo-device vnd 4 # disk-like interface to files
pseudo-device ccd 2 # concatenated disk devices
pseudo-device md 1 # Ramdisk driver
#pseudo-device rnd # /dev/random and /dev/urandom
makeoptions MONITOR="Taxan875+LR"
#makeoptions MONITOR="AKF60"
makeoptions MODES="1024,768,60 1024,768,70 800,600,60 640,480,60 1280,1024 1152,900"

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@ -1,305 +0,0 @@
# $NetBSD: RPC_WSCONS,v 1.8 2001/07/10 20:43:59 bjh21 Exp $
#
# RPC_WSCONS -- Full RiscPC config with wscons
#
include "arch/arm32/conf/std.arm32"
# estimated number of users
maxusers 32
# Standard system options
options RTC_OFFSET=0 # hardware clock is this many mins. west of GMT
#options NTP # NTP phase/frequency locked loop
# CPU options
options CPU_SA110 # Support the SA110 core
options CPU_ARM6 # Support the ARM6 core
options CPU_ARM7 # Support the ARM7 core
#options CPU_ARM8 # Support the ARM8 core
#options ARM6_LATE_ABORT # ARM6XX late abort support
# For StrongARM only kernels
#makeoptions COPTS="-O2 -march=armv3m -mtune=strongarm"
# Architecture options
options RISCPC # We are a RiscPC
#options RC7500 # We are a RC7500
# FPA options
#options ARMFPE # ARM Ltd FPE
# File systems
file-system FFS # UFS
#file-system LFS # log-structured file system
file-system MFS # memory file system
file-system NFS # Network file system
file-system ADOSFS # AmigaDOS-compatible file system
file-system EXT2FS # second extended file system (linux)
file-system CD9660 # ISO 9660 + Rock Ridge file system
file-system MSDOSFS # MS-DOS file system
file-system FDESC # /dev/fd
file-system FILECORE # Acorn filecore file system
file-system KERNFS # /kern
file-system NULLFS # loopback file system
file-system PORTAL # portal filesystem (still experimental)
file-system PROCFS # /proc
file-system UMAPFS # NULLFS + uid and gid remapping
file-system UNION # union file system
# File system options
options QUOTA # UFS quotas
options NFSSERVER
# Networking options
options GATEWAY # packet forwarding
options INET # IP + ICMP + TCP + UDP
options INET6 # IPV6
#options IPSEC # IP security
#options IPSEC_ESP # IP security (encryption part; define w/ IPSEC)
#options IPSEC_DEBUG # debug for IP security
#options MROUTING # IP multicast routing
#options NS # XNS
#options NSIP # XNS tunneling over IP
#options ISO,TPIP # OSI
#options EON # OSI tunneling over IP
#options CCITT,LLC,HDLC # X.25
options NETATALK # AppleTalk networking
#options PFIL_HOOKS # pfil(9) packet filter hooks
#options PPP_BSDCOMP # BSD-Compress compression support for PPP
#options PPP_DEFLATE # Deflate compression support for PPP
#options PPP_FILTER # Active filter support for PPP (requires bpf)
#options TCP_DEBUG # Record last TCP_NDEBUG packets with SO_DEBUG
# Compatibility options
options COMPAT_43 # 4.3BSD compatibility.
options COMPAT_14 # NetBSD 1.4 compatibility.
options COMPAT_13 # NetBSD 1.3 compatibility.
options COMPAT_12 # NetBSD 1.2 compatibility.
#options COMPAT_11 # NetBSD 1.1 compatibility.
#options COMPAT_10 # NetBSD 1.0 compatibility.
#options COMPAT_09 # NetBSD 0.9 compatibility.
#options TCP_COMPAT_42 # 4.2BSD TCP/IP bug compat. Not recommended.
# Bootloader options
#options COMPAT_OLD_BOOTLOADER
# Shared memory options
options SYSVMSG # System V-like message queues
options SYSVSEM # System V-like semaphores
options SYSVSHM # System V-like memory sharing
options SHMMAXPGS=1024 # 1024 pages is the default
# Device options
options MEMORY_DISK_HOOKS # boottime setup of ramdisk
#options MEMORY_DISK_SIZE=0 # Size in blocks
#options MINIROOTSIZE=3400 # Size in blocks
#options MEMORY_DISK_IS_ROOT # use memory disk as root
# Miscellaneous kernel options
options KTRACE # system call tracing, a la ktrace(1)
options IRQSTATS # manage IRQ statistics
options LKM # loadable kernel modules
options KMEMSTATS # kernel memory statistics
# Development and Debugging options
#options ARM700BUGTRACK # track the ARM700 swi bug
#options PORTMASTER # Enable PortMaster only options
#options DIAGNOSTIC # internally consistency checks
#options PMAP_DEBUG # Enable pmap_debug_level code
#options IPKDB # remote kernel debugging
options DDB # in-kernel debugger
#options DDB_HISTORY_SIZE=100 # Enable history editing in DDB
#makeoptions DEBUG="-g" # compile full symbol table
config netbsd root on ? type ?
# serial console ... the conaddr is hardcoded as the pioc address + 4*com offset
# this really be fixed some day
#options COMCONSOLE,CONADDR="0x210000+4*0x3f8",CONUNIT=0,CONSPEED=9600
# The main bus device
mainbus0 at root
# The boot cpu
cpu0 at mainbus?
# The IOMD
iomd0 at mainbus?
# system clock via IOMD
clock* at iomd?
# IIC bus device
iic* at iomd?
# RTC device via IIC bus
rtc* at iic? addr 0xa0
# time-of-day device via rtc device
todclock0 at rtc?
# VIDC device
vidc0 at mainbus?
# WSCONS
# ws console uses DUMB, SUN or VT100 terminal emulation
#options WSEMUL_NODUMB
#options WSEMUL_SUN
options WSEMUL_VT100
#options FONT_BOLD8x16
#options FONT_GALLANT12x22 # Very nice font
#options FONT_LUCIDA16x29
#options FONT_OMRON12x20 # looks funny
#options FONT_QVSS8x15 # broken ?
options FONT_SONY12x25 # looks like VT220 font
options FONT_SONY8x16 # not tested
#options FONT_VT220L8x8 # 8x8 font as in Arch. cons
#options FONT_VT220L8x16 # 8x(2x8) font as in Arch. cons
#options FONT_VT220L8x10 # not tested
#options FONT_VT220L8x20 # not tested
vidcvideo0 at vidc? # wscons driver for VIDC
wsdisplay* at vidcvideo? console ? # display itself
rpckbd* at iomd? # based on old `kbd' driver
wskbd* at rpckbd? # wskbd on RiscPC keyboard
wsqms* at iomd? # ws quadmouse driver
wsmouse* at wsqms? # wsmouse on ws quadmouse
pseudo-device wsmux 2 # why 2 ?
# The origional vidcconsole :
# vidcconsole kbd at IOMD
# vidcconsole PS2 mouse at IOMD
#vidcconsole0 at vidc? # display + vt100 emulation
#kbd* at iomd? # PS/2 keyboard for vidcconsole
#qms* at iomd? # RiscPC mouse for vidcconsole
#opms* at iomd? # A7000/NC? mouse for vidcconsole
# generic VT console device
#vt0 at vidc?
#vt1 at vidc?
#vt2 at vidc?
#vt3 at vidc?
#vt4 at vidc?
#vt5 at vidc?
# Peripheral IO Controller
pioc0 at mainbus? base 0x00210000
# IDE disk controller
wdc0 at pioc? offset 0x01f0 irq 9
#wdc* at pioc? offset 0x0170 irq -1
wd* at wdc? channel ? drive ?
atapibus* at wdc? channel ?
cd* at atapibus? drive ?
sd* at atapibus? drive ?
# Floppy disk controller
fdc* at pioc? offset 0x03f0 irq 12 dack 0x2000
fdc* at pioc? offset 0x0370 irq -1 dack 0x2000
fd0 at fdc? drive ?
# Serial ports
com* at pioc? offset 0x03f8 irq 10
#com* at pioc? offset 0x02f8 irq -1
#com* at pioc? offset 0x0338 irq -1
#com* at pioc? offset 0x0238 irq -1
# Parallel ports
lpt* at pioc? offset 0x0278 irq 0
#lpt* at pioc? offset 0x0378 irq -1
#lpt* at pioc? offset 0x03bc irq -1
# Crude sound device
beep0 at vidc?
# Audio device
vidcaudio0 at vidc?
audio* at vidcaudio0
# System beep
sysbeep0 at vidc?
# Podule bus device
podulebus0 at root
asc* at podulebus? # Acorn SCSI card
scsibus* at asc?
cosc* at podulebus? # MCS Connect32 SCSI II card
scsibus* at cosc?
ptsc* at podulebus? # Power-Tec SCSI II card
scsibus* at ptsc?
csc* at podulebus? # Cumana SCSI II card
scsibus* at csc?
oak* at podulebus? # Oak SCSI I card
scsibus* at oak?
csa* at podulebus? # Cumana SCSI I adpater
scsibus* at csa?
hcsc* at podulebus0 slot ? # HCCS 8-bit SCSI interface
scsibus* at hcsc?
sd* at scsibus? target ? lun ? # SCSI disk drives
st* at scsibus? target ? lun ? # SCSI tape drives
cd* at scsibus? target ? lun ? # SCSI CD-ROM drives
ch* at scsibus? target ? lun ? # SCSI auto-changers
uk* at scsibus? target ? lun ? # SCSI unknown device
ss* at scsibus? target ? lun ? # SCSI scanner
icside* at podulebus? # ICS IDE card
wd* at icside? channel ? drive ?
atapibus* at icside? channel ?
rapide* at podulebus? # Yellowstone RapIDE card
wd* at rapide? channel ? drive ?
atapibus* at rapide? channel ?
simide* at podulebus? # Simtec IDE card
wd* at simide? channel ? drive ?
atapibus* at simide? channel ?
amps* at podulebus? # Atomwide Multi-Port Serial card
com* at amps?
ie* at podulebus? # Ether1 podules
ea* at podulebus? # Ether3 podules
eb0 at podulebus? # EtherB network slot cards
ne* at podulebus? # NE2000 clone cards
pseudo-device loop 1 # network loopback
pseudo-device bpfilter 8 # packet filter
pseudo-device sl 2 # CSLIP
pseudo-device ppp 2 # PPP
pseudo-device tun 2 # network tunneling over tty
#pseudo-device ipfilter 1 # ip filter
#pseudo-device strip 4 # STRIP
pseudo-device pty # pseudo-terminals
pseudo-device tb 1 # tablet line discipline
pseudo-device vnd 4 # disk-like interface to files
pseudo-device ccd 2 # concatenated disk devices
pseudo-device md 1 # Ramdisk driver
pseudo-device rnd # /dev/random and /dev/urandom
makeoptions MONITOR="Taxan875+LR"
#makeoptions MONITOR="AKF60"
makeoptions MODES="1024,768,60 1024,768,70 800,600,60 640,480,60 1280,1024 1152,900"

274
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@ -1,274 +0,0 @@
# $NetBSD: VOYAGER,v 1.56 2001/07/10 20:43:59 bjh21 Exp $
#
# VOYAGER - Mark's development kernel
#
include "arch/arm32/conf/std.arm32"
# estimated number of users
maxusers 32
# Standard system options
options RTC_OFFSET=0 # hardware clock is this many mins. west of GMT
#options NTP # NTP phase/frequency locked loop
# CPU options
options CPU_SA110 # Support the SA110 core
options CPU_ARM6 # Support the ARM6 core
options CPU_ARM7 # Support the ARM7 core
options CPU_ARM8 # Support the ARM8 core
#options ARM6_LATE_ABORT # ARM6XX late abort support
# Architecture options
options RISCPC # We are a RiscPC
#options RC7500 # We are a RC7500
# FPA options
#options ARMFPE # ARM Ltd FPE
# File systems
file-system FFS # UFS
#file-system LFS # log-structured file system
file-system MFS # memory file system
file-system NFS # Network file system
#file-system ADOSFS # AmigaDOS-compatible file system
file-system EXT2FS # second extended file system (linux)
file-system CD9660 # ISO 9660 + Rock Ridge file system
file-system MSDOSFS # MS-DOS file system
file-system FDESC # /dev/fd
file-system FILECORE # Acorn filecore file system
file-system KERNFS # /kern
#file-system NULLFS # loopback file system
#file-system PORTAL # portal filesystem (still experimental)
file-system PROCFS # /proc
#file-system UMAPFS # NULLFS + uid and gid remapping
file-system UNION # union file system
# File system options
#options QUOTA # UFS quotas
options NFSSERVER
# Networking options
options GATEWAY # packet forwarding
options INET # IP + ICMP + TCP + UDP
#options INET6 # IPV6
#options IPSEC # IP security
#options IPSEC_ESP # IP security (encryption part; define w/ IPSEC)
#options IPSEC_DEBUG # debug for IP security
#options MROUTING # IP multicast routing
#options NS # XNS
#options NSIP # XNS tunneling over IP
#options ISO,TPIP # OSI
#options EON # OSI tunneling over IP
#options CCITT,LLC,HDLC # X.25
#options NETATALK # AppleTalk networking
#options PFIL_HOOKS # pfil(9) packet filter hooks
#options PPP_BSDCOMP # BSD-Compress compression support for PPP
#options PPP_DEFLATE # Deflate compression support for PPP
#options PPP_FILTER # Active filter support for PPP (requires bpf)
#options TCP_DEBUG # Record last TCP_NDEBUG packets with SO_DEBUG
# Compatibility options
options COMPAT_43 # 4.3BSD compatibility.
options COMPAT_14 # NetBSD 1.4 compatibility.
options COMPAT_13 # NetBSD 1.3 compatibility.
options COMPAT_12 # NetBSD 1.2 compatibility.
#options COMPAT_11 # NetBSD 1.1 compatibility.
#options COMPAT_10 # NetBSD 1.0 compatibility.
#options COMPAT_09 # NetBSD 0.9 compatibility.
#options TCP_COMPAT_42 # 4.2BSD TCP/IP bug compat. Not recommended.
# Bootloader options
options COMPAT_OLD_BOOTLOADER
# Shared memory options
options SYSVMSG # System V-like message queues
options SYSVSEM # System V-like semaphores
options SYSVSHM # System V-like memory sharing
options SHMMAXPGS=1024 # 1024 pages is the default
# Device options
options MEMORY_DISK_HOOKS # boottime setup of ramdisk
#options MEMORY_DISK_SIZE=0 # Size in blocks
#options MINIROOTSIZE=3400 # Size in blocks
#options MEMORY_DISK_IS_ROOT # use memory disk as root
# Miscellaneous kernel options
options KTRACE # system call tracing, a la ktrace(1)
options IRQSTATS # manage IRQ statistics
options LKM # loadable kernel modules
options KMEMSTATS # kernel memory statistics
# Development and Debugging options
#options ARM700BUGTRACK # track the ARM700 swi bug
options PORTMASTER # Enable PortMaster only options
options DIAGNOSTIC # internally consistency checks
options PMAP_DEBUG # Enable pmap_debug_level code
#options IPKDB # remote kernel debugging
options DDB # in-kernel debugger
#options DDB_HISTORY_SIZE=100 # Enable history editing in DDB
#makeoptions DEBUG="-g" # compile full symbol table
config netbsd root on ? type ?
# serial console ... the conaddr is hardcoded as the pioc address + 4*com offset
# this really be fixed some day
#options COMCONSOLE,CONADDR="0x210000+4*0x3f8",CONUNIT=0,CONSPEED=9600
# The main bus device
mainbus0 at root
# The boot cpu
cpu0 at mainbus?
# The IOMD
iomd0 at mainbus?
# system clock via IOMD
clock* at iomd?
# kbd via IOMD
kbd* at iomd?
# quadrature mouse via IOMD
qms* at iomd?
# PS2 mouse via IOMD
opms* at iomd?
# IIC bus device
iic* at iomd?
# RTC device via IIC bus
rtc* at iic? addr 0xa0
# time-of-day device via rtc device
todclock0 at rtc?
# VIDC device
vidc0 at mainbus?
# The vidc
vidcconsole0 at vidc?
# generic VT console device
vt0 at vidc?
vt1 at vidc?
vt2 at vidc?
vt3 at vidc?
vt4 at vidc?
vt5 at vidc?
vt6 at vidc?
vt7 at vidc?
# Peripheral IO Controller
pioc0 at mainbus? base 0x00210000
# IDE disk controller
wdc0 at pioc? offset 0x01f0 irq 9
#wdc* at pioc? offset 0x0170 irq -1
wd* at wdc? channel ? drive ?
atapibus* at wdc? channel ?
cd* at atapibus? drive ?
sd* at atapibus? drive ?
# Floppy disk controller
fdc* at pioc? offset 0x03f0 irq 12 dack 0x2000
fdc* at pioc? offset 0x0370 irq -1 dack 0x2000
fd0 at fdc? drive ?
# Serial ports
com* at pioc? offset 0x03f8 irq 10
#com* at pioc? offset 0x02f8 irq -1
#com* at pioc? offset 0x0338 irq -1
#com* at pioc? offset 0x0238 irq -1
# Parallel ports
lpt* at pioc? offset 0x0278 irq 0
#lpt* at pioc? offset 0x0378 irq -1
#lpt* at pioc? offset 0x03bc irq -1
# Crude sound device
beep0 at vidc?
# Audio device
vidcaudio0 at vidc?
audio* at vidcaudio0
# System beep
sysbeep0 at vidc?
# Podule bus device
podulebus0 at root
asc* at podulebus? # Acorn SCSI card
scsibus* at asc?
cosc* at podulebus? # MCS Connect32 SCSI II card
scsibus* at cosc?
ptsc* at podulebus? # Power-Tec SCSI II card
scsibus* at ptsc?
csc* at podulebus? # Cumana SCSI II card
scsibus* at csc?
oak* at podulebus? # Oak SCSI I card
scsibus* at oak?
csa* at podulebus? # Cumana SCSI I adpater
scsibus* at csa?
sd* at scsibus? target ? lun ? # SCSI disk drives
st* at scsibus? target ? lun ? # SCSI tape drives
cd* at scsibus? target ? lun ? # SCSI CD-ROM drives
ch* at scsibus? target ? lun ? # SCSI auto-changers
uk* at scsibus? target ? lun ? # SCSI unknown device
ss* at scsibus? target ? lun ? # SCSI scanner
icside* at podulebus? # ICS IDE card
wd* at icside? channel ? drive ?
atapibus* at icside? channel ?
rapide* at podulebus? # Yellowstone RapIDE card
wd* at rapide? channel ? drive ?
atapibus* at rapide? channel ?
simide* at podulebus? # Simtec IDE card
wd* at simide? channel ? drive ?
atapibus* at simide? channel ?
amps* at podulebus? # Atomwide Multi-Port Serial card
com* at amps?
ie* at podulebus? # Ether1 podules
ea* at podulebus? # Ether3 podules
eb0 at podulebus? # EtherB network slot cards
ne* at podulebus? # NE2000 clone cards
pseudo-device loop 1 # network loopback
pseudo-device bpfilter 8 # packet filter
pseudo-device sl 2 # CSLIP
pseudo-device ppp 2 # PPP
pseudo-device tun 2 # network tunneling over tty
#pseudo-device ipfilter 1 # ip filter
#pseudo-device strip 4 # STRIP
pseudo-device pty # pseudo-terminals
pseudo-device tb 1 # tablet line discipline
pseudo-device vnd 4 # disk-like interface to files
pseudo-device ccd 2 # concatenated disk devices
pseudo-device md 1 # Ramdisk driver
pseudo-device rnd # /dev/random and /dev/urandom
makeoptions MONITOR="Taxan875+LR"
#makeoptions MONITOR="AKF60"
makeoptions MODES="1024,768,60 1024,768,70 800,600,60 640,480,60 1280,1024 1152,900"

362
sys/arch/arm32/conf/monitors/AKF60
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@ -1,362 +0,0 @@
# $NetBSD: AKF60,v 1.2 1998/01/05 20:51:33 perry Exp $
#
# Modefile written by !MakeModes version 0.19 (22-Aug-1994)
# Monitor description file for Acorn AKF60 monitor
# Line rate: 30 - 50 kHz
file_format:1
monitor_title:Acorn AKF60
DPMS_state:1
# Letterbox modes
# 240 x 352 (70Hz)
startmode
mode_name:
x_res:240
y_res:352
pixel_rate:9440
h_timings:18,16,8,240,8,10
v_timings:2,58,0,352,0,37
sync_pol:2
endmode
# 320 x 250 (70Hz - Modes 6,7)
# Low band
startmode
mode_name:
x_res:320
y_res:250
pixel_rate:12587
h_timings:36,14,12,320,12,6
v_timings:2,109,0,250,0,88
sync_pol:2
endmode
# 320 x 256 (70Hz - Modes 1,2,5,9,10,13)
# Low band
startmode
mode_name:
x_res:320
y_res:256
pixel_rate:12587
h_timings:36,14,12,320,12,6
v_timings:2,106,0,256,0,85
sync_pol:2
endmode
# 384 x 288 (70Hz)
# Low band
startmode
mode_name:
x_res:384
y_res:288
pixel_rate:18881
h_timings:64,16,66,384,66,4
v_timings:2,58,32,288,32,37
sync_pol:2
endmode
# 480 x 352 (70Hz)
# Low band
startmode
mode_name:480 x 352
x_res:480
y_res:352
pixel_rate:18881
h_timings:64,16,18,480,18,4
v_timings:2,58,0,352,0,37
sync_pol:2
endmode
# 640 x 200 (70Hz - Modes 44,45,46)
# Low band
startmode
mode_name:
x_res:640
y_res:200
pixel_rate:25175
h_timings:88,22,22,640,22,6
v_timings:2,134,0,200,0,113
sync_pol:2
endmode
# 640 x 250 (70Hz - Modes 3,11,14)
# Low band
startmode
mode_name:
x_res:640
y_res:250
pixel_rate:25175
h_timings:88,22,22,640,22,6
v_timings:2,109,0,250,0,88
sync_pol:2
endmode
# 640 x 256 (70Hz - Modes 0,4,8,12,15)
# Low band
startmode
mode_name:
x_res:640
y_res:256
pixel_rate:25175
h_timings:88,22,22,640,22,6
v_timings:2,106,0,256,0,85
sync_pol:2
endmode
# 640 x 352 (70Hz - Modes 41,42,43)
# Low band
startmode
mode_name:
x_res:640
y_res:352
pixel_rate:25175
h_timings:88,22,22,640,22,6
v_timings:2,58,0,352,0,37
sync_pol:2
endmode
# Other modes (some also numbered)
# 320 x 480 (60Hz - Games modes 48,49)
# Low band
startmode
mode_name:
x_res:320
y_res:480
pixel_rate:12587
h_timings:36,14,12,320,12,6
v_timings:2,32,0,480,0,11
sync_pol:3
endmode
# 320 x 480 (72Hz)
# Mid band
startmode
mode_name:
x_res:320
y_res:480
pixel_rate:15750
h_timings:28,30,16,320,16,6
v_timings:3,28,0,480,0,9
sync_pol:3
endmode
# 320 x 480 (75Hz)
# Mid band
startmode
mode_name:
x_res:320
y_res:480
pixel_rate:15750
h_timings:26,34,16,320,16,8
v_timings:3,16,0,480,0,1
sync_pol:3
endmode
# 360 x 480 (60Hz - PCSoft mode 47)
# Low band
startmode
mode_name:
x_res:360
y_res:480
pixel_rate:16783
h_timings:62,44,16,360,16,34
v_timings:2,32,0,480,0,11
sync_pol:3
endmode
# 640 x 480 (60Hz - Modes 25,26,27,28)
# Low band
startmode
mode_name:640 x 480
x_res:640
y_res:480
pixel_rate:25175
h_timings:88,22,22,640,22,6
v_timings:2,32,0,480,0,11
sync_pol:3
endmode
# 640 x 480 (72Hz)
# Mid band
startmode
mode_name:640 x 480
x_res:640
y_res:480
pixel_rate:31500
h_timings:52,64,30,640,30,14
# VESA:40,128,0,640,0,24
v_timings:3,28,0,480,0,9
sync_pol:3
endmode
# 640 x 480 (75Hz)
# Mid band
startmode
mode_name:640 x 480
x_res:640
y_res:480
pixel_rate:31500
h_timings:62,64,30,640,30,14
# VESA:64,120,0,640,0,16
v_timings:3,16,0,480,0,1
sync_pol:3
endmode
# 800 x 600 (56Hz - Modes 29,30,31)
# Mid band
startmode
mode_name:800 x 600
x_res:800
y_res:600
pixel_rate:36000
h_timings:70,74,34,800,34,12
# VESA:72,128,0,800,0,24
v_timings:2,22,0,600,0,1
sync_pol:0
endmode
# 800 x 600 (60Hz)
# Mid band
startmode
mode_name:800 x 600
x_res:800
y_res:600
pixel_rate:40000
h_timings:112,64,40,800,40,0
# VESA:128,88, 0,800,0,40
v_timings:4,23,0,600,0,1
sync_pol:0
endmode
# 800 x 600 (72Hz)
# High band
startmode
mode_name:800 x 600
x_res:800
y_res:600
pixel_rate:50000
h_timings:88,34,42,800,42,34
# VESA:120,64, 0,800,0,56
v_timings:6,23,0,600,0,37
sync_pol:0
endmode
# 800 x 600 (75Hz)
# High band
startmode
mode_name:800 x 600
x_res:800
y_res:600
pixel_rate:49500
h_timings:80,46,42,800,42,46
# VESA:80,160,0,800,0,16
v_timings:3,21,0,600,0,1
sync_pol:0
endmode
# 1024 x 768 (60Hz)
# High band
startmode
mode_name:1024 x 768
x_res:1024
y_res:768
pixel_rate:65000
h_timings:128,36,60,1024,60,36
# VESA:136,160,0,1024,0,24
v_timings:6,29,0,768,0,3
sync_pol:0
endmode
# Pixel-doubled modes
# 1280 x 480 (60Hz)
# Low band
startmode
mode_name:1280 x 480
x_res:1280
y_res:480
pixel_rate:50350
h_timings:176,44,44,1280,44,12
v_timings:2,32,0,480,0,11
sync_pol:3
endmode
# 1280 x 480 (72Hz)
# Mid band
startmode
mode_name:1280 x 480
x_res:1280
y_res:480
pixel_rate:63000
h_timings:104,128,60,1280,60,28
# VESA:80,256,0,1280,0,48
v_timings:3,28,0,480,0,9
sync_pol:3
endmode
# 1280 x 480 (75Hz)
# Mid band
startmode
mode_name:1280 x 480
x_res:1280
y_res:480
pixel_rate:63000
h_timings:124,128,60,1280,60,28
# VESA:128,240,0,1280,0,32
v_timings:3,16,0,480,0,1
sync_pol:3
endmode
# 1600 x 600 (56Hz)
# Mid band
startmode
mode_name:1600 x 600
x_res:1600
y_res:600
pixel_rate:72000
h_timings:140,148,68,1600,68,24
v_timings:2,22,0,600,0,1
sync_pol:0
endmode
# 1600 x 600 (60Hz)
# Mid band
startmode
mode_name:1600 x 600
x_res:1600
y_res:600
pixel_rate:80000
h_timings:224,128,80,1600,80,0
# VESA:256,176, 0,1600,0,80
v_timings:4,23,0,600,0,1
sync_pol:0
endmode
# 1600 x 600 (72Hz)
# High band
startmode
mode_name:1600 x 600
x_res:1600
y_res:600
pixel_rate:100000
h_timings:176,68,84,1600,84,68
# VESA:240,128, 0,1600,0,112
v_timings:6,23,0,600,0,37
sync_pol:0
endmode
# 1600 x 600 (75Hz)
# High band
startmode
mode_name:1600 x 600
x_res:1600
y_res:600
pixel_rate:99000
h_timings:160,92,84,1600,84,92
# VESA:160,320,0,1600,0,32
v_timings:3,21,0,600,0,1
sync_pol:0
endmode

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sys/arch/arm32/conf/monitors/AKF85
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@ -1,399 +0,0 @@
# $NetBSD: AKF85,v 1.2 1998/01/05 20:51:34 perry Exp $
#
# Modefile written by !MakeModes version 0.19 (22-Aug-1994)
# Monitor description file for Acorn AKF85 monitor
# Line rate: 30 - 82 kHz
# Frame rate: 50 - 120 Hz
# Dot rate: Up to 135 MHz
file_format:1
monitor_title:Acorn AKF85
DPMS_state:0
# 240 x 352 (70Hz)
startmode
mode_name:
x_res:240
y_res:352
pixel_rate:9440
h_timings:20,16,8,240,8,8
v_timings:2,58,0,352,0,37
sync_pol:2
endmode
# 320 x 250 (70Hz)
startmode
mode_name:
x_res:320
y_res:250
pixel_rate:12587
h_timings:42,14,12,320,12,0
v_timings:2,109,0,250,0,88
sync_pol:2
endmode
# 320 x 256 (70Hz)
startmode
mode_name:
x_res:320
y_res:256
pixel_rate:12587
h_timings:42,14,12,320,12,0
v_timings:2,106,0,256,0,85
sync_pol:2
endmode
# 320 x 480 (60Hz)
startmode
mode_name:
x_res:320
y_res:480
pixel_rate:12587
h_timings:42,14,12,320,12,0
v_timings:2,32,0,480,0,11
sync_pol:3
endmode
# 320 x 480 (73Hz)
startmode
mode_name:
x_res:320
y_res:480
pixel_rate:15750
h_timings:24,40,16,320,16,0
v_timings:3,28,0,480,0,9
sync_pol:3
endmode
# 320 x 480 (75Hz)
startmode
mode_name:
x_res:320
y_res:480
pixel_rate:15750
h_timings:24,44,16,320,16,0
v_timings:3,16,0,480,0,1
sync_pol:3
endmode
# 360 x 480 (60Hz)
startmode
mode_name:
x_res:360
y_res:480
pixel_rate:16783
h_timings:64,46,16,360,16,30
v_timings:2,32,0,480,0,11
sync_pol:3
endmode
# 384 x 288 (70Hz)
startmode
mode_name:
x_res:384
y_res:288
pixel_rate:18881
h_timings:68,16,66,384,66,0
v_timings:2,58,32,288,32,37
sync_pol:2
endmode
# 480 x 352 (70Hz)
startmode
mode_name:480 x 352
x_res:480
y_res:352
pixel_rate:18881
h_timings:68,16,18,480,18,0
v_timings:2,58,0,352,0,37
sync_pol:2
endmode
# 640 x 200 (70Hz)
startmode
mode_name:
x_res:640
y_res:200
pixel_rate:25175
h_timings:92,24,22,640,22,0
v_timings:2,134,0,200,0,113
sync_pol:2
endmode
# 640 x 250 (70Hz)
startmode
mode_name:
x_res:640
y_res:250
pixel_rate:25175
h_timings:92,24,22,640,22,0
v_timings:2,109,0,250,0,88
sync_pol:2
endmode
# 640 x 256 (70Hz)
startmode
mode_name:
x_res:640
y_res:256
pixel_rate:25175
h_timings:92,24,22,640,22,0
v_timings:2,106,0,256,0,85
sync_pol:2
endmode
# 640 x 352 (70Hz)
startmode
mode_name:
x_res:640
y_res:352
pixel_rate:25175
h_timings:92,24,22,640,22,0
v_timings:2,58,0,352,0,37
sync_pol:2
endmode
# 640 x 480 (60Hz)
startmode
mode_name:640 x 480
x_res:640
y_res:480
pixel_rate:25175
h_timings:94,22,22,640,22,0
v_timings:2,32,0,480,0,11
sync_pol:3
endmode
# 640 x 480 (73Hz)
startmode
mode_name:640 x 480
x_res:640
y_res:480
pixel_rate:31500
h_timings:48,84,30,640,30,0
v_timings:3,28,0,480,0,9
sync_pol:3
endmode
# 640 x 480 (75Hz)
startmode
mode_name:640 x 480
x_res:640
y_res:480
pixel_rate:31500
h_timings:64,76,30,640,30,0
v_timings:3,16,0,480,0,1
sync_pol:3
endmode
# 640 x 480 (120Hz)
startmode
mode_name:640 x 480
x_res:640
y_res:480
pixel_rate:52600
h_timings:64,76,30,640,46,18
v_timings:3,16,0,480,0,1
sync_pol:3
endmode
# 800 x 600 (60Hz)
startmode
mode_name:800 x 600
x_res:800
y_res:600
pixel_rate:40000
h_timings:128,48,40,800,40,0
v_timings:4,23,0,600,0,1
sync_pol:0
endmode
# 800 x 600 (75Hz)
startmode
mode_name:800 x 600
x_res:800
y_res:600
pixel_rate:49500
h_timings:80,92,42,800,42,0
v_timings:3,21,0,600,0,1
sync_pol:0
endmode
# 800 x 600 (100Hz)
startmode
mode_name:800 x 600
x_res:800
y_res:600
pixel_rate:69350
h_timings:100,104,0,800,66,42
v_timings:3,21,0,600,0,1
sync_pol:0
endmode
# 1024 x 768 (60Hz)
startmode
mode_name:1024 x 768
x_res:1024
y_res:768
pixel_rate:65000
h_timings:136,64,60,1024,60,0
v_timings:6,29,0,768,0,3
sync_pol:0
endmode
# 1024 x 768 (70Hz)
startmode
mode_name:1024 x 768
x_res:1024
y_res:768
pixel_rate:75000
h_timings:124,36,72,1024,72,0
v_timings:6,29,0,768,0,3
sync_pol:0
endmode
# 1024 x 768 (75Hz)
startmode
mode_name:1024 x 768
x_res:1024
y_res:768
pixel_rate:80310
h_timings:122,86,30,1024,76,0
v_timings:3,28,0,768,0,1
sync_pol:0
endmode
# 1024 x 768 (102Hz)
startmode
mode_name:1024 x 768
x_res:1024
y_res:768
pixel_rate:119000
h_timings:130,96,46,1024,106,50
v_timings:3,28,0,768,0,1
sync_pol:0
endmode
# 1152 x 900 (55Hz)
startmode
mode_name:1152 x 900
x_res:1152
y_res:900
pixel_rate:80000
h_timings:156,40,98,1152,124,0
v_timings:1,28,0,900,0,3
sync_pol:0
endmode
# 1152 x 900 (86Hz)
startmode
mode_name:1152 x 900
x_res:1152
y_res:900
pixel_rate:134480
h_timings:132,70,124,1152,124,70
v_timings:1,28,0,900,0,3
sync_pol:0
endmode
# 1280 x 480 (60Hz)
startmode
mode_name:1280 x 480
x_res:1280
y_res:480
pixel_rate:50350
h_timings:188,44,44,1280,44,0
v_timings:2,32,0,480,0,11
sync_pol:3
endmode
# 1280 x 480 (73Hz)
startmode
mode_name:1280 x 480
x_res:1280
y_res:480
pixel_rate:63000
h_timings:96,172,58,1280,58,0
v_timings:3,28,0,480,0,9
sync_pol:3
endmode
# 1280 x 480 (75Hz)
startmode
mode_name:1280 x 480
x_res:1280
y_res:480
pixel_rate:63000
h_timings:128,156,58,1280,58,0
v_timings:3,16,0,480,0,1
sync_pol:3
endmode
# 1280 x 1024 (76Hz)
startmode
mode_name:1280 x 1024
x_res:1280
y_res:1024
pixel_rate:139000
h_timings:166,90,96,1280,96,0
v_timings:3,32,0,1024,0,3
sync_pol:0
endmode
# 1600 x 600 (56Hz)
startmode
mode_name:1600 x 600
x_res:1600
y_res:600
pixel_rate:72000
h_timings:144,168,68,1600,68,0
v_timings:2,22,0,600,0,1
sync_pol:0
endmode
# 1600 x 600 (60Hz)
startmode
mode_name:1600 x 600
x_res:1600
y_res:600
pixel_rate:80000
h_timings:256,98,78,1600,78,2
v_timings:4,23,0,600,0,1
sync_pol:0
endmode
# 1600 x 600 (72Hz)
startmode
mode_name:1600 x 600
x_res:1600
y_res:600
pixel_rate:100000
h_timings:226,58,84,1600,84,28
v_timings:6,23,0,600,0,37
sync_pol:0
endmode
# 1600 x 600 (75Hz)
startmode
mode_name:1600 x 600
x_res:1600
y_res:600
pixel_rate:99000
h_timings:160,188,82,1600,82,0
v_timings:3,21,0,600,0,1
sync_pol:0
endmode
# 1600 x 1200 (50Hz)
startmode
mode_name:1600 x 1200
x_res:1600
y_res:1200
pixel_rate:131000
h_timings:166,90,96,1600,128,44
v_timings:3,32,0,1200,0,3
sync_pol:0
endmode
# End

496
sys/arch/arm32/conf/monitors/AKF85B
View File

@ -1,496 +0,0 @@
# Modefile written by !MakeModes version 0.19 (22-Aug-1994)
# Monitor description file for Acorn AKF85 monitor
# Line rate: 30 - 82 kHz
# Frame rate: 50 - 120 Hz
# Dot rate: Up to 135 MHz
file_format:1
monitor_title:Acorn AKF85
DPMS_state:0
# 256 x 192 (101Hz)
startmode
mode_name:SegaMod
x_res:256
y_res:192
pixel_rate:10000
h_timings:36,40,16,256,38,14
v_timings:3,19,16,192,16,2
sync_pol:0
endmode
# 256 x 192 (111Hz)
startmode
mode_name:256 x 192
x_res:256
y_res:192
pixel_rate:12500
h_timings:50,46,6,256,36,14
v_timings:30,21,16,192,16,0
sync_pol:0
endmode
# 256 x 256 (85Hz)
startmode
mode_name:256 x 256
x_res:256
y_res:256
pixel_rate:9500
h_timings:20,16,8,256,8,8
v_timings:2,58,0,256,0,37
sync_pol:2
endmode
# 320 x 250 (70Hz)
startmode
mode_name:320 x 250
x_res:320
y_res:250
pixel_rate:12587
h_timings:42,14,12,320,12,0
v_timings:2,109,0,250,0,88
sync_pol:2
endmode
# 320 x 256 (60Hz)
startmode
mode_name:320 x 256
x_res:320
y_res:256
pixel_rate:12000
h_timings:42,14,12,320,12,0
v_timings:2,106,0,256,0,133
sync_pol:2
endmode
# 320 x 256 (70Hz)
startmode
mode_name: 320 x 256
x_res:320
y_res:256
pixel_rate:12587
h_timings:42,14,12,320,12,0
v_timings:2,106,0,256,0,85
sync_pol:2
endmode
# 320 x 400 (71Hz)
startmode
mode_name:320 x 400
x_res:320
y_res:400
pixel_rate:12750
h_timings:24,32,2,320,28,0
v_timings:3,28,0,400,0,9
sync_pol:3
endmode
# 320 x 480 (60Hz)
startmode
mode_name:320 x 480
x_res:320
y_res:480
pixel_rate:12587
h_timings:42,14,12,320,12,0
v_timings:2,32,0,480,0,11
sync_pol:3
endmode
# 320 x 480 (73Hz)
startmode
mode_name:320 x 480
x_res:320
y_res:480
pixel_rate:15750
h_timings:24,40,16,320,16,0
v_timings:3,28,0,480,0,9
sync_pol:3
endmode
# 320 x 480 (75Hz)
startmode
mode_name:320 x 480
x_res:320
y_res:480
pixel_rate:15750
h_timings:24,44,16,320,16,0
v_timings:3,16,0,480,0,1
sync_pol:3
endmode
# 320 x 512 (56Hz)
startmode
mode_name:320 x 512
x_res:320
y_res:512
pixel_rate:12587
h_timings:36,14,12,320,12,6
v_timings:2,32,0,512,0,11
sync_pol:3
endmode
# 360 x 480 (60Hz)
startmode
mode_name:360 x 480
x_res:360
y_res:480
pixel_rate:16783
h_timings:64,46,16,360,16,30
v_timings:2,32,0,480,0,11
sync_pol:3
endmode
# 384 x 192 (50Hz)
startmode
mode_name:384 x 192
x_res:384
y_res:192
pixel_rate:8000
h_timings:36,30,12,384,12,38
v_timings:3,16,49,192,49,3
sync_pol:0
endmode
# 384 x 192 (89Hz)
startmode
mode_name:384 x 192
x_res:384
y_res:192
pixel_rate:18881
h_timings:68,16,66,384,66,0
v_timings:2,58,32,192,32,37
sync_pol:2
endmode
# 384 x 288 (70Hz)
startmode
mode_name:384 x 288
x_res:384
y_res:288
pixel_rate:18881
h_timings:68,16,66,384,66,0
v_timings:2,58,32,288,32,37
sync_pol:2
endmode
# 448 x 288 (86Hz)
startmode
mode_name:448 x 288
x_res:448
y_res:288
pixel_rate:18881
h_timings:68,16,18,448,18,0
v_timings:2,58,0,288,0,37
sync_pol:2
endmode
# 480 x 352 (70Hz)
startmode
mode_name:480 x 352
x_res:480
y_res:352
pixel_rate:18881
h_timings:68,16,18,480,18,0
v_timings:2,58,0,352,0,37
sync_pol:2
endmode
# 512 x 384 (60Hz)
startmode
mode_name:512 x 384
x_res:512
y_res:384
pixel_rate:19860
h_timings:88,32,0,512,22,8
v_timings:70,7,8,384,0,30
sync_pol:3
endmode
# 640 x 200 (70Hz)
startmode
mode_name:640 x 200
x_res:640
y_res:200
pixel_rate:25175
h_timings:92,24,22,640,22,0
v_timings:2,134,0,200,0,113
sync_pol:2
endmode
# 640 x 250 (70Hz)
startmode
mode_name:640 x 250
x_res:640
y_res:250
pixel_rate:25175
h_timings:92,24,22,640,22,0
v_timings:2,109,0,250,0,88
sync_pol:2
endmode
# 640 x 256 (70Hz)
startmode
mode_name:640 x 256
x_res:640
y_res:256
pixel_rate:25175
h_timings:92,24,22,640,22,0
v_timings:2,106,0,256,0,85
sync_pol:2
endmode
# 640 x 352 (70Hz)
startmode
mode_name:640 x 352
x_res:640
y_res:352
pixel_rate:25175
h_timings:92,24,22,640,22,0
v_timings:2,58,0,352,0,37
sync_pol:2
endmode
# 640 x 480 (60Hz)
startmode
mode_name:640 x 480
x_res:640
y_res:480
pixel_rate:25175
h_timings:94,22,22,640,22,0
v_timings:2,32,0,480,0,11
sync_pol:3
endmode
# 640 x 480 (73Hz)
startmode
mode_name:640 x 480
x_res:640
y_res:480
pixel_rate:31500
h_timings:48,84,30,640,30,0
v_timings:3,28,0,480,0,9
sync_pol:3
endmode
# 640 x 480 (75Hz)
startmode
mode_name:640 x 480
x_res:640
y_res:480
pixel_rate:31500
h_timings:64,76,30,640,30,0
v_timings:3,16,0,480,0,1
sync_pol:3
endmode
# 640 x 512 (75Hz)
startmode
mode_name: 640 x 512
x_res:640
y_res:512
pixel_rate:33516
h_timings:64,76,30,640,30,0
v_timings:3,16,0,512,0,1
sync_pol:3
endmode
# 768 x 288 (82Hz)
startmode
mode_name:768 x 288
x_res:768
y_res:288
pixel_rate:25000
h_timings:20,16,8,768,8,8
v_timings:2,58,0,288,0,20
sync_pol:2
endmode
# 800 x 600 (56Hz)
startmode
mode_name:800 x 600
x_res:800
y_res:600
pixel_rate:36000
h_timings:72,84,34,800,34,0
v_timings:2,22,0,600,0,1
sync_pol:0
endmode
# 800 x 600 (60Hz)
startmode
mode_name:800 x 600
x_res:800
y_res:600
pixel_rate:40000
h_timings:128,48,40,800,40,0
v_timings:4,23,0,600,0,1
sync_pol:0
endmode
# 800 x 600 (72Hz)
startmode
mode_name:800 x 600
x_res:800
y_res:600
pixel_rate:50000
h_timings:100,42,42,800,42,14
v_timings:6,23,0,600,0,37
sync_pol:0
endmode
# 800 x 600 (75Hz)
startmode
mode_name:800 x 600
x_res:800
y_res:600
pixel_rate:49500
h_timings:80,92,42,800,42,0
v_timings:3,21,0,600,0,1
sync_pol:0
endmode
# 1024 x 768 (60Hz)
startmode
mode_name:1024 x 768
x_res:1024
y_res:768
pixel_rate:65000
h_timings:136,64,60,1024,60,0
v_timings:6,29,0,768,0,3
sync_pol:0
endmode
# 1024 x 768 (70Hz)
startmode
mode_name:1024 x 768
x_res:1024
y_res:768
pixel_rate:75000
h_timings:124,36,72,1024,72,0
v_timings:6,29,0,768,0,3
sync_pol:0
endmode
# 1024 x 768 (75Hz)
startmode
mode_name:1024 x 768
x_res:1024
y_res:768
pixel_rate:80310
h_timings:122,86,30,1024,76,0
v_timings:3,28,0,768,0,1
sync_pol:0
endmode
# 1280 x 480 (60Hz)
startmode
mode_name:1280 x 480
x_res:1280
y_res:480
pixel_rate:50350
h_timings:188,44,44,1280,44,0
v_timings:2,32,0,480,0,11
sync_pol:3
endmode
# 1280 x 480 (73Hz)
startmode
mode_name:1280 x 480
x_res:1280
y_res:480
pixel_rate:63000
h_timings:96,172,58,1280,58,0
v_timings:3,28,0,480,0,9
sync_pol:3
endmode
# 1280 x 480 (75Hz)
startmode
mode_name:1280 x 480
x_res:1280
y_res:480
pixel_rate:63000
h_timings:128,156,58,1280,58,0
v_timings:3,16,0,480,0,1
sync_pol:3
endmode
# 1280 x 1024 (70Hz)
startmode
mode_name:1280 x 1024
x_res:1280
y_res:1024
pixel_rate:132000
h_timings:182,72,106,1280,120,18
v_timings:3,32,0,1024,0,3
sync_pol:0
endmode
# 1600 x 600 (56Hz)
startmode
mode_name:1600 x 600
x_res:1600
y_res:600
pixel_rate:72000
h_timings:144,168,68,1600,68,0
v_timings:2,22,0,600,0,1
sync_pol:0
endmode
# 1600 x 600 (60Hz)
startmode
mode_name:1600 x 600
x_res:1600
y_res:600
pixel_rate:80000
h_timings:256,98,78,1600,78,2
v_timings:4,23,0,600,0,1
sync_pol:0
endmode
# 1600 x 600 (72Hz)
startmode
mode_name:1600 x 600
x_res:1600
y_res:600
pixel_rate:100000
h_timings:226,58,84,1600,84,28
v_timings:6,23,0,600,0,37
sync_pol:0
endmode
# 1600 x 600 (75Hz)
startmode
mode_name:1600 x 600
x_res:1600
y_res:600
pixel_rate:99000
h_timings:160,188,82,1600,82,0
v_timings:3,21,0,600,0,1
sync_pol:0
endmode
# 1600 x 1200 (57Hz)
startmode
mode_name:1600 × 1200
x_res:1600
y_res:1200
pixel_rate:152000
h_timings:160,116,62,1600,144,70
v_timings:3,30,0,1200,0,0
sync_pol:0
endmode
# 1696 x 1236 (54Hz)
startmode
mode_name:1696 × 1236
x_res:1696
y_res:1236
pixel_rate:145000
h_timings:176,170,32,1696,62,0
v_timings:3,21,8,1236,0,0
sync_pol:0
endmode
# End

414
sys/arch/arm32/conf/monitors/Taxan875+LR
View File

@ -1,414 +0,0 @@
# $NetBSD: Taxan875+LR,v 1.2 1998/01/05 20:51:35 perry Exp $
#
# Modefile written by !MakeModes version 0.19 (22-Aug-1994)
# Monitor description file for Taxan 875+LR monitor
# Line rate: 30 - 82 kHz
# Frame rate: 50 - 120 Hz
# Dot rate: Up to 135 MHz
file_format:1
monitor_title:Taxan 875+LR
DPMS_state:0
# Letterbox modes
# 240 x 352 (70Hz)
startmode
mode_name:
x_res:240
y_res:352
pixel_rate:9440
h_timings:20,16,8,240,8,8
v_timings:2,58,0,352,0,37
sync_pol:2
endmode
# 320 x 250 (70Hz - Modes 6,7)
startmode
mode_name:
x_res:320
y_res:250
pixel_rate:12587
h_timings:42,14,12,320,12,0
v_timings:2,109,0,250,0,88
sync_pol:2
endmode
# 320 x 256 (70Hz - Modes 1,2,5,9,10,13)
startmode
mode_name:
x_res:320
y_res:256
pixel_rate:12587
h_timings:42,14,12,320,12,0
v_timings:2,106,0,256,0,85
sync_pol:2
endmode
# 384 x 288 (70Hz)
startmode
mode_name:
x_res:384
y_res:288
pixel_rate:18881
h_timings: 68,16,66,384,66,0
v_timings: 2,58,32,288,32,37
sync_pol:2
endmode
# 480 x 352 (70Hz)
startmode
mode_name:480 x 352
x_res:480
y_res:352
pixel_rate:18881
h_timings: 68,16,18,480,18,0
v_timings: 2,58,0,352,0,37
sync_pol:2
endmode
# 640 x 200 (70Hz - Modes 44,45,46)
startmode
mode_name:
x_res:640
y_res:200
pixel_rate:25175
h_timings:92,24,22,640,22,0
v_timings:2,134,0,200,0,113
sync_pol:2
endmode
# 640 x 250 (70Hz - Modes 3,11,14)
startmode
mode_name:
x_res:640
y_res:250
pixel_rate:25175
h_timings:92,24,22,640,22,0
v_timings:2,109,0,250,0,88
sync_pol:2
endmode
# 640 x 256 (70Hz - Modes 0,4,8,12,15)
startmode
mode_name:
x_res:640
y_res:256
pixel_rate:25175
h_timings:92,24,22,640,22,0
v_timings:2,106,0,256,0,85
sync_pol:2
endmode
# 640 x 352 (70Hz - Modes 41,42,43)
startmode
mode_name:
x_res:640
y_res:352
pixel_rate:25175
h_timings:92,24,22,640,22,0
v_timings:2,58,0,352,0,37
sync_pol:2
endmode
# Other modes (some also numbered)
# 320 x 480 (60Hz - Games modes 48,49)
startmode
mode_name:
x_res:320
y_res:480
pixel_rate:12587
h_timings:42,14,12,320,12,0
v_timings:2,32,0,480,0,11
sync_pol:3
endmode
# 320 x 480 (72Hz)
startmode
mode_name:
x_res:320
y_res:480
pixel_rate:15750
h_timings:24,40,16,320,16,0
v_timings:3,28,0,480,0,9
sync_pol:3
endmode
# 320 x 480 (75Hz)
startmode
mode_name:
x_res:320
y_res:480
pixel_rate:15750
h_timings:24,44,16,320,16,0
v_timings:3,16,0,480,0,1
sync_pol:3
endmode
# 360 x 480 (60Hz - PCSoft mode 47)
startmode
mode_name:
x_res:360
y_res:480
pixel_rate:16783
h_timings:64,46,16,360,16,30
v_timings:2,32,0,480,0,11
sync_pol:3
endmode
# 640 x 480 (60Hz - Modes 25,26,27,28)
startmode
mode_name:640 x 480
x_res:640
y_res:480
pixel_rate:25175
h_timings:94,22,22,640,22,0
v_timings:2,32,0,480,0,11
sync_pol:3
endmode
# 640 x 480 (72Hz)
startmode
mode_name:640 x 480
x_res:640
y_res:480
pixel_rate:31500
h_timings:48,84,30,640,30,0
# VESA:40,128,0,640,0,24
v_timings:3,28,0,480,0,9
sync_pol:3
endmode
# 640 x 480 (75Hz)
startmode
mode_name:640 x 480
x_res:640
y_res:480
pixel_rate:31500
h_timings:64,76,30,640,30,0
# VESA:64,120,0,640,0,16
v_timings:3,16,0,480,0,1
sync_pol:3
endmode
# 800 x 600 (56Hz - Modes 29,30,31)
startmode
mode_name:800 x 600
x_res:800
y_res:600
pixel_rate:36000
h_timings:72,84,34,800,34,0
# VESA:72,128,0,800,0,24
v_timings:2,22,0,600,0,1
sync_pol:0
endmode
# 800 x 600 (60Hz)
startmode
mode_name:800 x 600
x_res:800
y_res:600
pixel_rate:40000
h_timings:128,48,40,800,40,0
# VESA:128,88, 0,800,0,40
v_timings:4,23,0,600,0,1
sync_pol:0
endmode
# 800 x 600 (72Hz)
startmode
mode_name:800 x 600
x_res:800
y_res:600
pixel_rate:50000
h_timings:100,42,42,800,42,14
# VESA:120,64, 0,800,0,56
v_timings:6,23,0,600,0,37
sync_pol:0
endmode
# Stick with just the 72Hz mode as this is a factory default
# 800 x 600 (75Hz)
#startmode
#mode_name:800 x 600
#x_res:800
#y_res:600
#pixel_rate:49500
#h_timings:80,92,42,800,42,0
# VESA:80,160,0,800,0,16
#v_timings:3,21,0,600,0,1
#sync_pol:0
#endmode
# 1024 x 768 (60Hz)
startmode
mode_name:1024 x 768
x_res:1024
y_res:768
pixel_rate:65000
h_timings:136,64,60,1024,60,0
# VESA:136,160,0,1024,0,24
v_timings:6,29,0,768,0,3
sync_pol:0
endmode
# 1024 x 768 (70Hz)
startmode
mode_name:1024 x 768
x_res:1024
y_res:768
pixel_rate:75000
h_timings:124,36,72,1024,72,0
# VESA:136,144,0,1024,0,24
v_timings:6,29,0,768,0,3
sync_pol:0
endmode
# this has been removed so that it does not get selected for the 16 colour
# version. 70Hz 1024x768 is a build in setting, 75Hz ain't !
# 1024 x 768 (75Hz)
#startmode
#mode_name:1024 x 768
#x_res:1024
#y_res:768
#pixel_rate:80310
# VESA:78750
#h_timings:122,86,30,1024,76,0
# VESA: 96,176,0,1024,0,16
#v_timings:3,28,0,768,0,1
#sync_pol:0
#endmode
# 1152 x 900 (53Hz)
startmode
mode_name:1152 x 900
x_res:1152
y_res:900
pixel_rate:76000
h_timings:152,64,60,1152,100,0
v_timings:6,29,0,900,0,3
sync_pol:3
endmode
# 1152 x 900 (76Hz)
startmode
mode_name:1152 x 900
x_res:1152
y_res:900
pixel_rate:117000
h_timings:170,96,96,1152,104,12
v_timings:3,33,0,900,0,3
sync_pol:3
endmode
# 1280 x 1024 (60Hz)
startmode
mode_name:1280 x 1024
x_res:1280
y_res:1024
pixel_rate:110000
h_timings:166,90,96,1280,96,0
#h_timings:128,256,0,1280,0,64
v_timings:3,32,0,1024,0,3
sync_pol:0
endmode
# The taxan has a 70Hz 1280 x 768 build in just got to find it.
# 1280 x 1024 (70Hz)
startmode
mode_name:1280 x 1024
x_res:1280
y_res:1024
pixel_rate:128000
h_timings:160,88,96,1280,96,0
#h_timings:166,90,96,1280,96,0
#h_timings:128,256,0,1280,0,64
v_timings:3,32,0,1024,0,3
sync_pol:0
endmode
# Pixel-doubled modes
# 1280 x 480 (60Hz)
startmode
mode_name:1280 x 480
x_res:1280
y_res:480
pixel_rate:50350
h_timings:188,44,44,1280,44,0
v_timings:2,32,0,480,0,11
sync_pol:3
endmode
# 1280 x 480 (72Hz)
startmode
mode_name:1280 x 480
x_res:1280
y_res:480
pixel_rate:63000
h_timings:96,172,58,1280,58,0
# VESA:80,256,0,1280,0,48
v_timings:3,28,0,480,0,9
sync_pol:3
endmode
# 1280 x 480 (75Hz)
startmode
mode_name:1280 x 480
x_res:1280
y_res:480
pixel_rate:63000
h_timings:128,156,58,1280,58,0
# VESA:128,240,0,1280,0,32
v_timings:3,16,0,480,0,1
sync_pol:3
endmode
# 1600 x 600 (56Hz)
startmode
mode_name:1600 x 600
x_res:1600
y_res:600
pixel_rate:72000
h_timings:144,168,68,1600,68,0
v_timings:2,22,0,600,0,1
sync_pol:0
endmode
# 1600 x 600 (60Hz)
startmode
mode_name:1600 x 600
x_res:1600
y_res:600
pixel_rate:80000
h_timings:256,98,78,1600,78,2
# VESA:256,176, 0,1600,0,80
v_timings:4,23,0,600,0,1
sync_pol:0
endmode
# 1600 x 600 (72Hz)
startmode
mode_name:1600 x 600
x_res:1600
y_res:600
pixel_rate:100000
h_timings:226,58,84,1600,84,28
# VESA:240,128, 0,1600,0,112
v_timings:6,23,0,600,0,37
sync_pol:0
endmode
# 1600 x 600 (75Hz)
startmode
mode_name:1600 x 600
x_res:1600
y_res:600
pixel_rate:99000
h_timings:160,188,82,1600,82,0
# VESA:160,320,0,1600,0,32
v_timings:3,21,0,600,0,1
sync_pol:0
endmode

108
sys/arch/arm32/iomd/iic_iomd.c
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@ -1,108 +0,0 @@
/* $NetBSD: iic_iomd.c,v 1.1 1997/10/14 11:16:35 mark Exp $ */
/*
* Copyright (c) 1994-1996 Mark Brinicombe.
* Copyright (c) 1994 Brini.
* All rights reserved.
*
* This code is derived from software written for Brini by Mark Brinicombe
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Mark Brinicombe.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RiscBSD kernel project
*
* iic.c
*
* Routines to communicate with IIC devices
*
* Created : 13/10/94
*
* Based of kate/display/iiccontrol.c
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/device.h>
#include <machine/bus.h>
#include <machine/irqhandler.h>
#include <arm32/dev/iicvar.h>
#include <arm32/iomd/iomdvar.h>
static int iic_iomd_probe __P((struct device *, struct cfdata *, void *));
static void iic_iomd_attach __P((struct device *, struct device *, void *));
struct cfattach iic_iomd_ca = {
sizeof(struct iic_softc), iic_iomd_probe, iic_iomd_attach
};
/*
* iic device probe function
*
* just validate the attach args
*/
static int
iic_iomd_probe(parent, cf, aux)
struct device *parent;
struct cfdata *cf;
void *aux;
{
struct iic_attach_args *ia = aux;
if (strcmp(ia->ia_name, "iic") == 0)
return(1);
return(0);
}
/*
* iic device attach function
*
* Initialise the softc structure and do a search for children
*/
static void
iic_iomd_attach(parent, self, aux)
struct device *parent;
struct device *self;
void *aux;
{
struct iic_softc *sc = (void *)self;
struct iic_attach_args *ia = aux;
sc->sc_iot = ia->ia_iot;
sc->sc_ioh = ia->ia_ioh;
printf("\n");
config_search(iicsearch, self, NULL);
}
/* End of iic_iomd.c */

316
sys/arch/arm32/iomd/iomd.c
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@ -1,316 +0,0 @@
/* $NetBSD: iomd.c,v 1.15 2001/07/10 21:31:59 bjh21 Exp $ */
/*
* Copyright (c) 1996-1997 Mark Brinicombe.
* Copyright (c) 1997 Causality Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Mark Brinicombe.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RiscBSD kernel project
*
* iomd.c
*
* Probing and configuration for the IOMD
*
* Created : 10/10/95
* Updated : 18/03/01 for rpckbd as part of the wscons project
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/conf.h>
#include <sys/malloc.h>
#include <sys/device.h>
#include <machine/bus.h>
#include <machine/cpu.h>
#include <machine/irqhandler.h>
#include <arm32/iomd/iomdreg.h>
#include <arm32/iomd/iomdvar.h>
#include "iomd.h"
/*
* IOMD device.
*
* This probes and attaches the top level IOMD device.
* It then configures any children of the IOMD device.
*/
/*
* IOMD softc structure.
*
* Contains the device node, bus space tag, handle and address
* and the IOMD id.
*/
struct iomd_softc {
struct device sc_dev; /* device node */
bus_space_tag_t sc_iot; /* bus tag */
bus_space_handle_t sc_ioh; /* bus handle */
int sc_id; /* IOMD id */
};
static int iomdmatch __P((struct device *parent, struct cfdata *cf,
void *aux));
static void iomdattach __P((struct device *parent, struct device *self,
void *aux));
static int iomdprint __P((void *aux, const char *iomdbus));
struct cfattach iomd_ca = {
sizeof(struct iomd_softc), iomdmatch, iomdattach
};
extern struct bus_space iomd_bs_tag;
int iomd_found;
u_int32_t iomd_base = IOMD_BASE;
/* following flag is used in iomd_irq.s ... has to be cleaned up one day ! */
u_int32_t arm7500_ioc_found = 0;
/* Declare prototypes */
/*
* int iomdprint(void *aux, const char *name)
*
* print configuration info for children
*/
static int
iomdprint(aux, name)
void *aux;
const char *name;
{
/* union iomd_attach_args *ia = aux;*/
return(QUIET);
}
/*
* int iomdmatch(struct device *parent, struct cfdata *cf, void *aux)
*
* Just return ok for this if it is device 0
*/
static int
iomdmatch(parent, cf, aux)
struct device *parent;
struct cfdata *cf;
void *aux;
{
if (iomd_found)
return 0;
return 1;
}
/*
* void iomdattach(struct device *parent, struct device *dev, void *aux)
*
* Map the IOMD and identify it.
* Then configure the child devices based on the IOMD ID.
*/
static void
iomdattach(parent, self, aux)
struct device *parent;
struct device *self;
void *aux;
{
struct iomd_softc *sc = (struct iomd_softc *)self;
/* struct mainbus_attach_args *mb = aux;*/
int refresh;
#if 0
int dma_time;
int combo_time;
int loop;
#endif
union iomd_attach_args ia;
bus_space_tag_t iot;
bus_space_handle_t ioh;
/* There can be only 1 IOMD. */
iomd_found = 1;
iot = sc->sc_iot = &iomd_bs_tag;
/* Map the IOMD */
if (bus_space_map(iot, (int) iomd_base, IOMD_SIZE, 0, &ioh))
panic("%s: Cannot map registers\n", self->dv_xname);
sc->sc_ioh = ioh;
/* Get the ID */
sc->sc_id = bus_space_read_1(iot, ioh, IOMD_ID0)
| (bus_space_read_1(iot, ioh, IOMD_ID1) << 8);
printf(": ");
/* Identify it and get the DRAM refresh rate */
switch (sc->sc_id) {
case ARM7500_IOC_ID:
printf("ARM7500 IOMD ");
refresh = bus_space_read_1(iot, ioh, IOMD_REFCR) & 0x0f;
arm7500_ioc_found = 1;
break;
case ARM7500FE_IOC_ID:
printf("ARM7500FE IOMD ");
refresh = bus_space_read_1(iot, ioh, IOMD_REFCR) & 0x0f;
arm7500_ioc_found = 1;
break;
case RPC600_IOMD_ID:
printf("IOMD20 ");
refresh = bus_space_read_1(iot, ioh, IOMD_VREFCR) & 0x09;
arm7500_ioc_found = 0;
break;
default:
printf("Unknown IOMD ID=%04x ", sc->sc_id);
refresh = -1;
arm7500_ioc_found = 0; /* just in case */
break;
}
printf("version %d\n", bus_space_read_1(iot, ioh, IOMD_VERSION));
/* Report the DRAM refresh rate */
printf("%s: ", self->dv_xname);
printf("DRAM refresh=");
switch (refresh) {
case 0x0:
printf("off");
break;
case 0x1:
printf("16us");
break;
case 0x2:
printf("32us");
break;
case 0x4:
printf("64us");
break;
case 0x8:
printf("128us");
break;
default:
printf("unknown [%02x]", refresh);
break;
}
#if 0
/*
* No point in reporting this as it may get changed when devices are
* attached
*/
dma_time = ReadByte(IOMD_DMATCR);
printf(", dma cycle types=");
for (loop = 0; loop < 4; ++loop,dma_time = dma_time >> 2)
printf("%c", 'A' + (dma_time & 3));
combo_time = ReadByte(IOMD_IOTCR);
printf(", combo cycle type=%c", 'A' + ((combo_time >> 2) & 3));
#endif
printf("\n");
/* Set up the external DMA channels */
/* XXX - this should be machine dependant not IOMD dependant */
switch (sc->sc_id) {
case ARM7500_IOC_ID:
case ARM7500FE_IOC_ID:
break;
case RPC600_IOMD_ID:
/* DMA channels 2 & 3 are external */
bus_space_write_1(iot, ioh, IOMD_DMAEXT, 0x0c);
break;
}
/* Configure the child devices */
/* Attach clock device */
ia.ia_clk.ca_name = "clk";
ia.ia_clk.ca_iot = iot;
ia.ia_clk.ca_ioh = ioh;
config_found(self, &ia, iomdprint);
/* Attach kbd device when configured */
if (bus_space_subregion(iot, ioh, IOMD_KBDDAT, 8, &ia.ia_kbd.ka_ioh))
panic("%s: Cannot map kbd registers\n", self->dv_xname);
ia.ia_kbd.ka_name = "kbd";
ia.ia_kbd.ka_iot = iot;
ia.ia_kbd.ka_rxirq = IRQ_KBDRX;
ia.ia_kbd.ka_txirq = IRQ_KBDTX;
config_found(self, &ia, iomdprint);
/* Attach rpckbc device when configured */
ia.ia_kbd.ka_name = "rpckbd";
ia.ia_kbd.ka_rxirq = IRQ_KBDRX;
ia.ia_kbd.ka_txirq = IRQ_KBDTX;
config_found(self, &ia, iomdprint);
/* Attach iic device */
if (bus_space_subregion(iot, ioh, IOMD_IOCR, 4, &ia.ia_iic.ia_ioh))
panic("%s: Cannot map iic registers\n", self->dv_xname);
ia.ia_iic.ia_name = "iic";
ia.ia_iic.ia_iot = iot;
ia.ia_iic.ia_irq = -1;
config_found(self, &ia, iomdprint);
switch (sc->sc_id) {
case ARM7500_IOC_ID:
case ARM7500FE_IOC_ID:
/* Attach pms device */
if (bus_space_subregion(iot, ioh, IOMD_MSDATA, 8, &ia.ia_pms.pa_ioh))
panic("%s: Cannot map pms registers\n", self->dv_xname);
ia.ia_pms.pa_name = "pms";
ia.ia_pms.pa_iot = iot;
ia.ia_pms.pa_irq = IRQ_MSDRX;
config_found(self, &ia, iomdprint);
break;
case RPC600_IOMD_ID:
/* Attach (ws)qms device */
if (bus_space_subregion(iot, ioh, IOMD_MOUSEX, 8, &ia.ia_qms.qa_ioh))
panic("%s: Cannot map qms registers\n", self->dv_xname);
if (bus_space_map(iot, IO_MOUSE_BUTTONS, 4, 0, &ia.ia_qms.qa_ioh_but))
panic("%s: Cannot map registers\n", self->dv_xname);
ia.ia_qms.qa_name = "qms";
ia.ia_qms.qa_iot = iot;
ia.ia_qms.qa_irq = IRQ_VSYNC;
config_found(self, &ia, iomdprint);
ia.ia_qms.qa_name = "wsqms";
config_found(self, &ia, iomdprint);
break;
}
}
/* End of iomd.c */

362
sys/arch/arm32/iomd/iomd_clock.c
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@ -1,362 +0,0 @@
/* $NetBSD: iomd_clock.c,v 1.25 2001/04/10 19:08:42 bjh21 Exp $ */
/*
* Copyright (c) 1994-1997 Mark Brinicombe.
* Copyright (c) 1994 Brini.
* All rights reserved.
*
* This code is derived from software written for Brini by Mark Brinicombe
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Mark Brinicombe.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RiscBSD kernel project
*
* clock.c
*
* Timer related machine specific code
*
* Created : 29/09/94
*/
/* Include header files */
#include <sys/types.h>
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/time.h>
#include <sys/device.h>
#include <machine/irqhandler.h>
#include <machine/cpufunc.h>
#include <arm32/iomd/iomdvar.h>
#include <arm32/iomd/iomdreg.h>
struct clock_softc {
struct device sc_dev;
bus_space_tag_t sc_iot;
bus_space_handle_t sc_ioh;
};
#define TIMER_FREQUENCY 2000000 /* 2MHz clock */
#define TICKS_PER_MICROSECOND (TIMER_FREQUENCY / 1000000)
static void *clockirq;
static void *statclockirq;
static struct clock_softc *clock_sc;
static int timer0_count;
static int clockmatch __P((struct device *parent, struct cfdata *cf, void *aux));
static void clockattach __P((struct device *parent, struct device *self, void *aux));
#ifdef DIAGNOSTIC
static void checkdelay __P((void));
#endif
struct cfattach clock_ca = {
sizeof(struct clock_softc), clockmatch, clockattach
};
/*
* int clockmatch(struct device *parent, void *match, void *aux)
*
* Just return ok for this if it is device 0
*/
static int
clockmatch(parent, cf, aux)
struct device *parent;
struct cfdata *cf;
void *aux;
{
struct clk_attach_args *ca = aux;
if (strcmp(ca->ca_name, "clk") == 0)
return(1);
return(0);
}
/*
* void clockattach(struct device *parent, struct device *dev, void *aux)
*
* Map the IOMD and identify it.
* Then configure the child devices based on the IOMD ID.
*/
static void
clockattach(parent, self, aux)
struct device *parent;
struct device *self;
void *aux;
{
struct clock_softc *sc = (struct clock_softc *)self;
struct clk_attach_args *ca = aux;
sc->sc_iot = ca->ca_iot;
sc->sc_ioh = ca->ca_ioh; /* This is a handle for the whole IOMD */
clock_sc = sc;
/* Cannot do anything until cpu_initclocks() has been called */
printf("\n");
}
/*
* int clockhandler(struct clockframe *frame)
*
* Function called by timer 0 interrupts. This just calls
* hardclock(). Eventually the irqhandler can call hardclock() directly
* but for now we use this function so that we can debug IRQ's
*/
int
clockhandler(frame)
struct clockframe *frame;
{
#ifdef RC7500
extern void setleds();
static int leds = 0;
setleds(1 << leds);
leds++;
if (leds >> 3)
leds = 0;
#endif /* RC7500 */
hardclock(frame);
return(0); /* Pass the interrupt on down the chain */
}
/*
* int statclockhandler(struct clockframe *frame)
*
* Function called by timer 1 interrupts. This just calls
* statclock(). Eventually the irqhandler can call statclock() directly
* but for now we use this function so that we can debug IRQ's
*/
int
statclockhandler(frame)
struct clockframe *frame;
{
statclock(frame);
return(0); /* Pass the interrupt on down the chain */
}
/*
* void setstatclockrate(int hz)
*
* Set the stat clock rate. The stat clock uses timer1
*/
void
setstatclockrate(hz)
int hz;
{
int count;
count = TIMER_FREQUENCY / hz;
printf("Setting statclock to %dHz (%d ticks)\n", hz, count);
bus_space_write_1(clock_sc->sc_iot, clock_sc->sc_ioh,
IOMD_T1LOW, (count >> 0) & 0xff);
bus_space_write_1(clock_sc->sc_iot, clock_sc->sc_ioh,
IOMD_T1HIGH, (count >> 8) & 0xff);
/* reload the counter */
bus_space_write_1(clock_sc->sc_iot, clock_sc->sc_ioh,
IOMD_T1GO, 0);
}
#ifdef DIAGNOSTIC
static void
checkdelay()
{
struct timeval start, end, diff;
microtime(&start);
delay(10000);
microtime(&end);
timersub(&end, &start, &diff);
if (diff.tv_sec > 0)
return;
if (diff.tv_usec > 10000)
return;
printf("WARNING: delay(10000) took %ld us\n", diff.tv_usec);
}
#endif
/*
* void cpu_initclocks(void)
*
* Initialise the clocks.
* This sets up the two timers in the IOMD and installs the IRQ handlers
*
* NOTE: Currently only timer 0 is setup and the IRQ handler is not installed
*/
void
cpu_initclocks()
{
/*
* Load timer 0 with count down value
* This timer generates 100Hz interrupts for the system clock
*/
printf("clock: hz=%d stathz = %d profhz = %d\n", hz, stathz, profhz);
timer0_count = TIMER_FREQUENCY / hz;
bus_space_write_1(clock_sc->sc_iot, clock_sc->sc_ioh,
IOMD_T0LOW, (timer0_count >> 0) & 0xff);
bus_space_write_1(clock_sc->sc_iot, clock_sc->sc_ioh,
IOMD_T0HIGH, (timer0_count >> 8) & 0xff);
/* reload the counter */
bus_space_write_1(clock_sc->sc_iot, clock_sc->sc_ioh,
IOMD_T0GO, 0);
clockirq = intr_claim(IRQ_TIMER0, IPL_CLOCK, "tmr0 hard clk",
clockhandler, 0);
if (clockirq == NULL)
panic("%s: Cannot installer timer 0 IRQ handler\n",
clock_sc->sc_dev.dv_xname);
if (stathz) {
setstatclockrate(stathz);
statclockirq = intr_claim(IRQ_TIMER1, IPL_CLOCK,
"tmr1 stat clk", statclockhandler, 0);
if (statclockirq == NULL)
panic("%s: Cannot installer timer 1 IRQ handler\n",
clock_sc->sc_dev.dv_xname);
}
#ifdef DIAGNOSTIC
checkdelay();
#endif
}
/*
* void microtime(struct timeval *tvp)
*
* Fill in the specified timeval struct with the current time
* accurate to the microsecond.
*/
void
microtime(tvp)
struct timeval *tvp;
{
int s;
int tm;
int deltatm;
static struct timeval oldtv;
if (timer0_count == 0)
return;
s = splhigh();
/*
* Latch the current value of the timer and then read it.
* This garentees an atmoic reading of the time.
*/
bus_space_write_1(clock_sc->sc_iot, clock_sc->sc_ioh,
IOMD_T0LATCH, 0);
tm = bus_space_read_1(clock_sc->sc_iot, clock_sc->sc_ioh,
IOMD_T0LOW);
tm += (bus_space_read_1(clock_sc->sc_iot, clock_sc->sc_ioh,
IOMD_T0HIGH) << 8);
deltatm = timer0_count - tm;
if (deltatm < 0)
printf("opps deltatm < 0 tm=%d deltatm=%d\n",
tm, deltatm);
/* Fill in the timeval struct */
*tvp = time;
tvp->tv_usec += (deltatm / TICKS_PER_MICROSECOND);
/* Make sure the micro seconds don't overflow. */
while (tvp->tv_usec >= 1000000) {
tvp->tv_usec -= 1000000;
++tvp->tv_sec;
}
/* Make sure the time has advanced. */
if (tvp->tv_sec == oldtv.tv_sec &&
tvp->tv_usec <= oldtv.tv_usec) {
tvp->tv_usec = oldtv.tv_usec + 1;
if (tvp->tv_usec >= 1000000) {
tvp->tv_usec -= 1000000;
++tvp->tv_sec;
}
}
oldtv = *tvp;
(void)splx(s);
}
/*
* Estimated loop for n microseconds
*/
/* Need to re-write this to use the timers */
/* One day soon I will actually do this */
int delaycount = 100;
void
delay(n)
u_int n;
{
u_int i;
if (n == 0) return;
while (--n > 0) {
if (cputype == CPU_ID_SA110) /* XXX - Seriously gross hack */
for (i = delaycount; --i;);
else
for (i = 8; --i;);
}
}
/* End of iomd_clock.c */

326
sys/arch/arm32/iomd/iomd_dma.c
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@ -1,326 +0,0 @@
/* $NetBSD: iomd_dma.c,v 1.11 2001/07/28 18:12:44 chris Exp $ */
/*
* Copyright (c) 1995 Scott Stevens
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Scott Stevens.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* RiscBSD kernel project
*
* dma.c
*
* Created : 15/03/97
*/
#define DMA_DEBUG
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <uvm/uvm_extern.h>
#include <machine/irqhandler.h>
#include <machine/pmap.h>
#include <arm32/iomd/iomdreg.h>
#include <arm32/iomd/iomdvar.h>
#include <arm32/iomd/iomd_dma.h>
/*
* Only for non ARM7500 machines but the kernel could be booted on a different machine
*/
static struct dma_ctrl ctrl[6];
void dma_dumpdc __P((struct dma_ctrl *));
void
dma_go(dp)
struct dma_ctrl *dp;
{
#ifdef DMA_DEBUG
printf("dma_go()\n");
#endif
if(dp->dc_flags & DMA_FL_READY) {
dp->dc_flags = DMA_FL_ACTIVE;
enable_irq(IRQ_DMACH0 + dp->dc_channel);
}
else
panic("dma not ready");
}
int
dma_reset(dp)
struct dma_ctrl *dp;
{
#ifdef DMA_DEBUG
printf("dma_reset()\n");
dma_dumpdc(dp);
#endif
*dp->dc_cr = DMA_CR_CLEAR;
dp->dc_flags = 0;
disable_irq(IRQ_DMACH0 + dp->dc_channel);
return(0);
}
/*
* Setup dma transfer, prior to the dma_go call
*/
int
dma_setup(dp, start, len, readp)
struct dma_ctrl *dp;
int readp;
u_char *start;
int len;
{
#ifdef DMA_DEBUG
printf("dma_setup(start = %p, len = 0x%08x, readp = %d\n", start, len, readp);
#endif
if(((u_int)start & (dp->dc_dmasize - 1)) ||
(len & (dp->dc_dmasize - 1))) {
printf("dma_setup: unaligned DMA, %p (0x%08x)\n",
start, len);
}
*dp->dc_cr = DMA_CR_CLEAR | DMA_CR_ENABLE | (readp?DMA_CR_DIR:0) | dp->dc_dmasize;
*dp->dc_cr = DMA_CR_ENABLE | (readp?DMA_CR_DIR:0) | dp->dc_dmasize;
dp->dc_nextaddr = start;
dp->dc_len = len;
dp->dc_flags = DMA_FL_READY;
return(0);
}
/*
* return true if DMA is active
*/
int
dma_isactive(dp)
struct dma_ctrl *dp;
{
return(dp->dc_flags & DMA_FL_ACTIVE);
}
/*
* return true if interrupt pending
*/
int
dma_isintr(dp)
struct dma_ctrl *dp;
{
#ifdef DMA_DEBUG
/* printf("dma_isintr() returning %d\n", *dp->dc_st & DMA_ST_INT);*/
#endif
return(*dp->dc_st & DMA_ST_INT);
}
int
dma_intr(dp)
struct dma_ctrl *dp;
{
u_char status = (*dp->dc_st) & DMA_ST_MASK;
vm_offset_t cur;
int len;
int bufap = 0;
#ifdef DMA_DEBUG
printf("dma_intr() status = 0x%02x\n", status);
#endif
if(!(dp->dc_flags & DMA_FL_ACTIVE)) {
/* interrupt whilst not active */
/* ie. last buffer programmed */
dma_reset(dp);
return(0);
}
switch(status) {
case DMA_ST_OVER | DMA_ST_INT:
case DMA_ST_OVER | DMA_ST_INT | DMA_ST_CHAN:
/* idle, either first buffer or finished */
if(status & DMA_ST_CHAN) {
/* fill buffer B */
bufap = 0;
goto fill;
}
else {
/* fill buffer A */
bufap = 1;
goto fill;
}
break;
case DMA_ST_INT:
case DMA_ST_INT | DMA_ST_CHAN:
/* buffer ready */
if(status & DMA_ST_CHAN) {
/* fill buffer A */
bufap = 1;
goto fill;
}
else {
/* fill buffer B */
bufap = 0;
goto fill;
}
break;
default:
/* Shouldn't be here */
#ifdef DMA_DEBUG
printf("DMA ch %d bad status [%x]\n", dp->dc_channel, status);
dma_dumpdc(dp);
#endif
break;
}
/* return(0);*/
/* XXX */
#define PHYS(x, y) pmap_extract(pmap_kernel(), (vaddr_t)x, (paddr_t *)(y))
fill:
#ifdef DMA_DEBUG
printf("fill:\n");
#endif
if (dp->dc_len == 0) goto done;
PHYS(dp->dc_nextaddr, &cur);
len = NBPG - (cur & PGOFSET);
if (len > dp->dc_len) {
/* Last buffer */
len = dp->dc_len;
}
#ifdef DMA_DEBUG
dma_dumpdc(dp);
/* ptsc_dump_mem(dp->dc_nextaddr, len);*/
#endif
/*
* Flush the cache for this address
*/
cpu_cache_purgeD_rng((vm_offset_t)dp->dc_nextaddr, len);
dp->dc_nextaddr += len;
dp->dc_len -= len;
if(bufap) {
*dp->dc_cura = (u_int)cur;
*dp->dc_enda = ((u_int)cur + len - dp->dc_dmasize) |
(dp->dc_len == 0 ? DMA_END_STOP : 0);
if (dp->dc_len == 0) {
/* Last buffer, fill other buffer with garbage */
*dp->dc_endb = (u_int)cur;
}
}
else {
*dp->dc_curb = (u_int)cur;
*dp->dc_endb = ((u_int)cur + len - dp->dc_dmasize) |
(dp->dc_len == 0 ? DMA_END_STOP : 0);
if (dp->dc_len == 0) {
/* Last buffer, fill other buffer with garbage */
*dp->dc_enda = (u_int)cur;
}
}
#ifdef DMA_DEBUG
dma_dumpdc(dp);
/* ptsc_dump_mem(dp->dc_nextaddr - len, len);*/
printf("about to return\n");
#endif
return(1);
done:
#ifdef DMA_DEBUG
printf("done:\n");
#endif
dp->dc_flags = 0;
*dp->dc_cr = 0;
disable_irq(IRQ_DMACH0 + dp->dc_channel);
#ifdef DMA_DEBUG
printf("about to return\n");
#endif
return(1);
}
void
dma_dumpdc(dc)
struct dma_ctrl *dc;
{
printf("\ndc:\t%p\n"
"dc_channel:\t%p=0x%08x\tdc_flags:\t%p=0x%08x\n"
"dc_cura:\t%p=0x%08x\tdc_enda:\t%p=0x%08x\n"
"dc_curb:\t%p=0x%08x\tdc_endb:\t%p=0x%08x\n"
"dc_cr:\t%p=0x%02x\t\tdc_st:\t%p=0x%02x\n"
"dc_nextaddr:\t%p=0x%08x\tdc_len:\t%p=0x%08x\n",
dc,
&dc->dc_channel, (int)dc->dc_channel,
&dc->dc_flags, (int)dc->dc_flags,
dc->dc_cura, (int)*dc->dc_cura,
dc->dc_enda, (int)*dc->dc_enda,
dc->dc_curb, (int)*dc->dc_curb,
dc->dc_endb, (int)*dc->dc_endb,
dc->dc_cr, (int)*dc->dc_cr,
dc->dc_st, (int)(*dc->dc_st) & DMA_ST_MASK,
&dc->dc_nextaddr, (int)dc->dc_nextaddr,
&dc->dc_len, dc->dc_len);
}
struct dma_ctrl *
dma_init(ch, extp, dmasize, ipl)
int ch;
int extp;
int dmasize;
int ipl;
{
struct dma_ctrl *dp = &ctrl[ch];
int offset = ch * 0x20;
volatile u_char *dmaext = (volatile u_char *)(IOMD_ADDRESS(IOMD_DMAEXT));
printf("Initialising DMA channel %d\n", ch);
dp->dc_channel = ch;
dp->dc_flags = 0;
dp->dc_dmasize = dmasize;
dp->dc_cura = (volatile u_int *)(IOMD_ADDRESS(IOMD_IO0CURA) + offset);
dp->dc_enda = (volatile u_int *)(IOMD_ADDRESS(IOMD_IO0ENDA) + offset);
dp->dc_curb = (volatile u_int *)(IOMD_ADDRESS(IOMD_IO0CURB) + offset);
dp->dc_endb = (volatile u_int *)(IOMD_ADDRESS(IOMD_IO0ENDB) + offset);
dp->dc_cr = (volatile u_char *)(IOMD_ADDRESS(IOMD_IO0CR) + offset);
dp->dc_st = (volatile u_char *)(IOMD_ADDRESS(IOMD_IO0ST) + offset);
if (extp)
*dmaext |= (1 << ch);
printf("about to claim interrupt\n");
dp->dc_ih.ih_func = dma_intr;
dp->dc_ih.ih_arg = dp;
dp->dc_ih.ih_level = ipl;
dp->dc_ih.ih_name = "dma";
dp->dc_ih.ih_maskaddr = (u_int) IOMD_ADDRESS(IOMD_DMARQ);
dp->dc_ih.ih_maskbits = (1 << ch);
if (irq_claim(IRQ_DMACH0 + ch, &dp->dc_ih))
panic("Cannot install DMA IRQ handler\n");
return(dp);
}

75
sys/arch/arm32/iomd/iomd_dma.h
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@ -1,75 +0,0 @@
/* $NetBSD: iomd_dma.h,v 1.1 1997/10/14 11:06:57 mark Exp $ */
/*
* Copyright (c) 1997 Scott Stevens
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Scott Stevens.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)dmavar.h
*/
/*
* dma structures
*/
struct dma_ctrl {
int dc_flags;
int dc_channel;
int dc_dmasize;
volatile u_int *dc_cura;
volatile u_int *dc_enda;
volatile u_int *dc_curb;
volatile u_int *dc_endb;
volatile u_char *dc_cr;
volatile u_char *dc_st;
u_char *dc_nextaddr;
int dc_len;
irqhandler_t dc_ih;
};
#define DMA_FL_ACTIVE 0x01
#define DMA_FL_READY 0x02
#define DMA_CR_CLEAR 0x80
#define DMA_CR_DIR 0x40
#define DMA_CR_ENABLE 0x20
#define DMA_CR_INC 0x1f
#define DMA_ST_CHAN 0x01
#define DMA_ST_INT 0x02
#define DMA_ST_OVER 0x04
#define DMA_ST_MASK (DMA_ST_CHAN | DMA_ST_INT | DMA_ST_OVER)
#define DMA_END_STOP 0x80000000
#define DMA_END_LAST 0x40000000
/* Prototypes */
struct dma_ctrl *dma_init __P((int, int, int, int));
void dma_go __P((struct dma_ctrl *));

113
sys/arch/arm32/iomd/iomd_fiq.S
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@ -1,113 +0,0 @@
/* $NetBSD: iomd_fiq.S,v 1.6 1999/10/26 06:53:43 cgd Exp $ */
/*
* Copyright (c) 1994-1996 Mark Brinicombe.
* Copyright (c) 1994 Brini.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Mark Brinicombe.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL HTE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RiscBSD kernel project
*
* fiq.S
*
* Low level fiq handlers
*
* Created : 27/09/94
*/
#include <machine/asm.h>
#include <machine/cpu.h>
/*
* if NOFDFIQLOOPS is defined only 1 byte is transferred per
* FIQ. The new default behaviour is to keep looping
* until there are no FD FIQ's pending.
*/
/*
* These registers needs to be consistent with fd
* driver's assignment.
*
* r8 - scratch
* r9 - IOMD_FIQRQ
* r10 - transfer size
* r11 - data address
* r12 - floppy controller DACK address (+ 0x18000 for TC)
* r13 - scratch (loop counter)
*/
ENTRY_NP(floppy_read_fiq)
subs r10, r10, #0x00000001
addeq r12, r12, #0x00018000
ldrb r8, [r12]
strb r8, [r11], #0x0001
#ifndef NOFDFIQLOOPS
subeqs pc, lr, #0x00000004
ldrb r8, [r9]
tst r8, #0x01
addne r13, r13, #0x00000001
bne _C_LABEL(floppy_read_fiq)
#endif
subs pc, lr, #0x00000004
.global _C_LABEL(floppy_read_fiq_end)
_C_LABEL(floppy_read_fiq_end):
/*
* These registers needs to be consistent with fd
* driver's assignment.
*
* r8 - scratch
* r9 - IOMD_FIQRQ
* r10 - transfer size
* r11 - data address
* r12 - floppy controller DACK address (+ 0x18000 for TC)
* r13 - scratch (loop counter)
*/
ENTRY_NP(floppy_write_fiq)
subs r10, r10, #0x00000001
addeq r12, r12, #0x00018000
ldrb r8, [r11], #0x0001
strb r8, [r12]
#ifndef NOFDFIQLOOPS
subeqs pc, lr, #0x00000004
ldrb r8, [r9]
tst r8, #0x01
addne r13, r13, #0x00000001
bne _C_LABEL(floppy_write_fiq)
#endif
subs pc, lr, #0x00000004
.global _C_LABEL(floppy_write_fiq_end)
_C_LABEL(floppy_write_fiq_end):
/* End of fiq.S */

253
sys/arch/arm32/iomd/iomd_iic.S
View File

@ -1,253 +0,0 @@
/* $NetBSD: iomd_iic.S,v 1.4 2001/02/25 23:59:48 reinoud Exp $ */
/*
* Copyright (c) 1994-1996 Mark Brinicombe.
* Copyright (c) 1994 Brini.
* All rights reserved.
*
* This code is derived from software written for Brini by Mark Brinicombe
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Mark Brinicombe.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RiscBSD kernel project
*
* iic.s
*
* Low level routines to with IIC devices
*
* Created : 13/10/94
*
* Based of kate/display/iic.s
*/
#include <machine/asm.h>
#include <machine/cpu.h>
#include <arm32/iomd/iomdreg.h>
#define IIC_BITDELAY 10
Liomd_base:
.word _C_LABEL(iomd_base)
ENTRY(iic_set_state)
/*
* Parameters
* r0 - IIC data bit
* r1 - IIC clock bit
*/
/* Store temporary register */
/* stmfd sp!, {r4}*/
/*
* Mask the data and clock bits
* Since these routines are only called from iiccontrol.c this is not
* really needed
*/
and r0, r0, #0x00000001
and r1, r1, #0x00000001
/* Get address of IOMD control register */
ldr r2, Liomd_base
ldr r2, [r2]
/* Get the current CPSR */
/* mrs r4, cpsr_all
orr r3, r4, #(I32_bit | F32_bit)
msr cpsr_all, r3
*/
IRQdisable
/* Get current value of control register */
ldrb r3, [r2, #(IOMD_IOCR << 2)]
/* Preserve non-IIC bits */
bic r3, r3, #0x00000003
#ifdef RC7500
and r3, r3, #0x000000ff
#else
/* orr r3, r3, #0x000000c0*/
#endif
/* Set the IIC clock and data bits */
orr r3, r3, r0
orr r3, r3, r1, lsl #1
/* Store the new value of control register */
strb r3, [r2, #(IOMD_IOCR << 2)]
/* Restore CPSR state */
/* msr cpsr_all, r4 */
IRQenable
/* Restore temporary register */
/* ldmfd sp!, {r4} */
/* Pause a bit */
mov r0, #(IIC_BITDELAY)
/* Exit via iic_delay routine */
b _C_LABEL(iic_delay)
ENTRY(iic_set_state_and_ack)
/*
* Parameters
* r0 - IIC data bit
* r1 - IIC clock bit
*/
/* Store temporary register */
/* stmfd sp!, {r4} */
/*
* Mask the data and clock bits
* Since these routines are only called from iiccontrol.c this is not
* really needed
*/
and r0, r0, #0x00000001
and r1, r1, #0x00000001
/* Get address of IOMD control register */
ldr r2, Liomd_base
ldr r2, [r2]
/* Get the current CPSR */
/* mrs r4, cpsr_all
orr r3, r4, #(I32_bit | F32_bit)
msr cpsr_all, r3
*/
IRQdisable
/* Get current value of control register */
ldrb r3, [r2, #(IOMD_IOCR << 2)]
/* Preserve non-IIC bits */
bic r3, r3, #0x00000003
#ifdef RC7500
and r3, r3, #0x000000ff
#else
/* orr r3, r3, #0x000000c0*/
#endif
/* Set the IIC clock and data bits */
orr r3, r3, r0
orr r3, r3, r1, lsl #1
/* Store the new value of control register */
strb r3, [r2, #(IOMD_IOCR << 2)]
Liic_set_state_and_ack_loop:
ldrb r3, [r2, #(IOMD_IOCR << 2)]
tst r3, #0x00000002
beq Liic_set_state_and_ack_loop
/* Restore CPSR state */
/* msr cpsr_all, r4 */
IRQenable
/* Restore temporary register */
/* ldmfd sp!, {r4} */
/* Pause a bit */
mov r0, #(IIC_BITDELAY)
/* Exit via iic_delay routine */
b _C_LABEL(iic_delay)
ENTRY(iic_delay)
/*
* Parameters
* r0 - time to wait
*/
/* Load address of IOMD */
ldr r2, Liomd_base
ldr r2, [r2]
/* Latch current value of timer 1 */
strb r2, [r2, #(IOMD_T0LATCH << 2)]
/* Get the latched value */
ldrb r1, [r2, #(IOMD_T0LOW << 2)]
/* Loop until timer reaches end value */
Liic_delay_loop:
/* Latch the current value of timer1 */
strb r2, [r2, #(IOMD_T0LATCH << 2)]
/* Get the latched value */
ldrb r3, [r2, #(IOMD_T0LOW << 2)]
/* Loop until timer reached expected value */
teq r3, r1
movne r1, r3
beq Liic_delay_loop
subs r0, r0, #0x00000001
bne Liic_delay_loop
/* Exit */
mov pc, lr
ENTRY(iic_getstate)
/* Load address of IOMD */
ldr r2, Liomd_base
ldr r2, [r2]
/* Read IOCR */
ldrb r0, [r2, #(IOMD_IOCR << 2)]
mov pc, lr
/* End of iomd_iic.S */

205
sys/arch/arm32/iomd/iomd_io.c
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@ -1,205 +0,0 @@
/* $NetBSD: iomd_io.c,v 1.5 2001/09/10 02:20:20 reinoud Exp $ */
/*
* Copyright (c) 1997 Mark Brinicombe.
* Copyright (c) 1997 Causality Limited.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Mark Brinicombe.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* bus_space I/O functions for iomd
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <machine/bus.h>
/* Proto types for all the bus_space structure functions */
bs_protos(iomd);
bs_protos(bs_notimpl);
/* Declare the iomd bus space tag */
struct bus_space iomd_bs_tag = {
/* cookie */
NULL,
/* mapping/unmapping */
iomd_bs_map,
iomd_bs_unmap,
iomd_bs_subregion,
/* allocation/deallocation */
iomd_bs_alloc,
iomd_bs_free,
/* get kernel virtual address */
0, /* there is no linear mapping */
/* mmap bus space for userland */
bs_notimpl_bs_mmap, /* XXX correct? XXX */
/* barrier */
iomd_bs_barrier,
/* read (single) */
iomd_bs_r_1,
iomd_bs_r_2,
iomd_bs_r_4,
bs_notimpl_bs_r_8,
/* read multiple */
bs_notimpl_bs_rm_1,
iomd_bs_rm_2,
bs_notimpl_bs_rm_4,
bs_notimpl_bs_rm_8,
/* read region */
bs_notimpl_bs_rr_1,
bs_notimpl_bs_rr_2,
bs_notimpl_bs_rr_4,
bs_notimpl_bs_rr_8,
/* write (single) */
iomd_bs_w_1,
iomd_bs_w_2,
iomd_bs_w_4,
bs_notimpl_bs_w_8,
/* write multiple */
bs_notimpl_bs_wm_1,
iomd_bs_wm_2,
bs_notimpl_bs_wm_4,
bs_notimpl_bs_wm_8,
/* write region */
bs_notimpl_bs_wr_1,
bs_notimpl_bs_wr_2,
bs_notimpl_bs_wr_4,
bs_notimpl_bs_wr_8,
/* set multiple */
bs_notimpl_bs_sm_1,
bs_notimpl_bs_sm_2,
bs_notimpl_bs_sm_4,
bs_notimpl_bs_sm_8,
/* set region */
bs_notimpl_bs_sr_1,
bs_notimpl_bs_sr_2,
bs_notimpl_bs_sr_4,
bs_notimpl_bs_sr_8,
/* copy */
bs_notimpl_bs_c_1,
bs_notimpl_bs_c_2,
bs_notimpl_bs_c_4,
bs_notimpl_bs_c_8,
};
/* bus space functions */
int
iomd_bs_map(t, bpa, size, cacheable, bshp)
void *t;
bus_addr_t bpa;
bus_size_t size;
int cacheable;
bus_space_handle_t *bshp;
{
/*
* Temporary implementation as all I/O is already mapped etc.
*
* Eventually this function will do the mapping check for multiple maps
*/
*bshp = bpa;
return(0);
}
int
iomd_bs_alloc(t, rstart, rend, size, alignment, boundary, cacheable,
bpap, bshp)
void *t;
bus_addr_t rstart, rend;
bus_size_t size, alignment, boundary;
int cacheable;
bus_addr_t *bpap;
bus_space_handle_t *bshp;
{
panic("iomd_alloc(): Help!\n");
}
void
iomd_bs_unmap(t, bsh, size)
void *t;
bus_space_handle_t bsh;
bus_size_t size;
{
/*
* Temporary implementation
*/
}
void
iomd_bs_free(t, bsh, size)
void *t;
bus_space_handle_t bsh;
bus_size_t size;
{
panic("iomd_free(): Help!\n");
/* iomd_unmap() does all that we need to do. */
/* iomd_unmap(t, bsh, size);*/
}
int
iomd_bs_subregion(t, bsh, offset, size, nbshp)
void *t;
bus_space_handle_t bsh;
bus_size_t offset, size;
bus_space_handle_t *nbshp;
{
*nbshp = bsh + (offset << 2);
return (0);
}
void
iomd_bs_barrier(t, bsh, offset, len, flags)
void *t;
bus_space_handle_t bsh;
bus_size_t offset, len;
int flags;
{
}
/* End of iomd_io.c */

97
sys/arch/arm32/iomd/iomd_io_asm.S
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@ -1,97 +0,0 @@
/* $NetBSD: iomd_io_asm.S,v 1.4 1999/10/26 06:53:43 cgd Exp $ */
/*
* Copyright (c) 1997 Mark Brinicombe.
* Copyright (c) 1997 Causality Limited.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Mark Brinicombe.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <machine/asm.h>
/*
* bus_space I/O functions for iomd
*/
/*
* read single
*/
ENTRY(iomd_bs_r_1)
ldrb r0, [r1, r2, lsl #2]
mov pc, lr
ENTRY(iomd_bs_r_2)
ldr r0, [r1, r2, lsl #2]
bic r0, r0, #0xff000000
bic r0, r0, #0x00ff0000
mov pc, lr
ENTRY(iomd_bs_r_4)
ldr r0, [r1, r2, lsl #2]
mov pc, lr
/*
* write single
*/
ENTRY(iomd_bs_w_1)
strb r3, [r1, r2, lsl #2]
mov pc, lr
ENTRY(iomd_bs_w_2)
mov r3, r3, lsl #16
orr r3, r3, r3, lsr #16
str r3, [r1, r2, lsl #2]
mov pc, lr
ENTRY(iomd_bs_w_4)
str r3, [r1, r2, lsl #2]
mov pc, lr
/*
* read multiple
*/
ENTRY(iomd_bs_rm_2)
add r0, r1, r2, lsl #2
mov r1, r3
ldr r2, [sp, #0]
b _C_LABEL(insw16)
/*
* write multiple
*/
ENTRY(iomd_bs_wm_2)
add r0, r1, r2, lsl #2
mov r1, r3
ldr r2, [sp, #0]
b _C_LABEL(outsw16)

604
sys/arch/arm32/iomd/iomd_irq.S
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@ -1,604 +0,0 @@
/* $NetBSD: iomd_irq.S,v 1.26 2001/07/28 12:28:56 chris Exp $ */
/*
* Copyright (c) 1994-1998 Mark Brinicombe.
* Copyright (c) 1994 Brini.
* All rights reserved.
*
* This code is derived from software written for Brini by Mark Brinicombe
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Mark Brinicombe
* for the NetBSD Project.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Low level irq and fiq handlers
*
* Created : 27/09/94
*/
#include "opt_irqstats.h"
#include "assym.h"
#include <machine/asm.h>
#include <machine/cpu.h>
#include <machine/frame.h>
#include <arm32/iomd/iomdreg.h>
.text
.align 0
/*
* ffs table used for servicing irq's quickly must be here otherwise adr can't
* reach it
* The algorithm for ffs was devised by D. Seal and posted to
* comp.sys.arm on 16 Feb 1994.
*/
.type Lirq_ffs_table, _ASM_TYPE_OBJECT;
Lirq_ffs_table:
/* same as ffs table but all nums are -1 from that */
/* 0 1 2 3 4 5 6 7 */
.byte 0, 0, 1, 12, 2, 6, 0, 13 /* 0- 7 */
.byte 3, 0, 7, 0, 0, 0, 0, 14 /* 8-15 */
.byte 10, 4, 0, 0, 8, 0, 0, 25 /* 16-23 */
.byte 0, 0, 0, 0, 0, 21, 27, 15 /* 24-31 */
.byte 31, 11, 5, 0, 0, 0, 0, 0 /* 32-39 */
.byte 9, 0, 0, 24, 0, 0, 20, 26 /* 40-47 */
.byte 30, 0, 0, 0, 0, 23, 0, 19 /* 48-55 */
.byte 29, 0, 22, 18, 28, 17, 16, 0 /* 56-63 */
/*
*
* irq_entry
*
* Main entry point for the IRQ vector
*
* This function reads the irq request bits in the IOMD registers
* IRQRQA, IRQRQB and DMARQ
* It then calls an installed handler for each bit that is set.
* The function stray_irqhandler is called if a handler is not defined
* for a particular interrupt.
* If a interrupt handler is found then it is called with r0 containing
* the argument defined in the handler structure. If the field ih_arg
* is zero then a pointer to the IRQ frame on the stack is passed instead.
*/
Ldisabled_mask:
.word _C_LABEL(disabled_mask)
Lcurrent_spl_level:
.word _C_LABEL(current_spl_level)
Lcurrent_intr_depth:
.word _C_LABEL(current_intr_depth)
Lspl_masks:
.word _C_LABEL(spl_masks)
/*
* Register usage
*
* r5 - Address of ffs table
* r6 - Address of current handler
* r7 - Pointer to handler pointer list
* r8 - Current IRQ requests.
* r10 - Base address of IOMD
* r11 - IRQ requests still to service.
*/
Liomd_base:
.word _C_LABEL(iomd_base)
Larm7500_ioc_found:
.word _C_LABEL(arm7500_ioc_found)
ASENTRY_NP(irq_entry)
sub lr, lr, #0x00000004 /* Adjust the lr */
PUSHFRAMEINSVC /* Push an interrupt frame */
/* Load r8 with the IOMD interrupt requests */
ldr r10, Liomd_base
ldr r10, [r10] /* Point to the IOMD */
ldrb r8, [r10, #(IOMD_IRQRQA << 2)] /* Get IRQ request A */
ldrb r9, [r10, #(IOMD_IRQRQB << 2)] /* Get IRQ request B */
orr r8, r8, r9, lsl #8
ldr r9, Larm7500_ioc_found
ldr r9, [r9] /* get the flag */
cmp r9, #0
beq skip_extended_IRQs_reading
/* ARM 7500 only */
ldrb r9, [r10, #(IOMD_IRQRQC << 2)] /* Get IRQ request C */
orr r8, r8, r9, lsl #16
ldrb r9, [r10, #(IOMD_IRQRQD << 2)] /* Get IRQ request D */
orr r8, r8, r9, lsl #24
ldrb r9, [r10, #(IOMD_DMARQ << 2)] /* Get DMA Request */
tst r9, #0x10
orrne r8, r8, r9, lsl #27
b irq_entry_continue
skip_extended_IRQs_reading:
/* non ARM7500 machines */
ldrb r9, [r10, #(IOMD_DMARQ << 2)] /* Get DMA Request */
orr r8, r8, r9, lsl #16
irq_entry_continue:
and r0, r8, #0x7d /* Clear IOMD IRQA bits */
strb r0, [r10, #(IOMD_IRQRQA << 2)]
/*
* Note that we have entered the IRQ handler.
* We are in SVC mode so we cannot use the processor mode
* to determine if we are in an IRQ. Instead we will count the
* each time the interrupt handler is nested.
*/
ldr r0, Lcurrent_intr_depth
ldr r1, [r0]
add r1, r1, #1
str r1, [r0]
/* Block the current requested interrupts */
ldr r1, Ldisabled_mask
ldr r0, [r1]
stmfd sp!, {r0}
orr r0, r0, r8
/*
* Need to block all interrupts at the IPL or lower for
* all asserted interrupts.
* This basically emulates hardware interrupt priority levels.
* Means we need to go through the interrupt mask and for
* every asserted interrupt we need to mask out all other
* interrupts at the same or lower IPL.
* If only we could wait until the main loop but we need to sort
* this out first so interrupts can be re-enabled.
*
* This would benefit from a special ffs type routine
*/
mov r9, #(_SPL_LEVELS - 1)
ldr r7, Lspl_masks
Lfind_highest_ipl:
ldr r2, [r7, r9, lsl #2]
tst r8, r2
subeq r9, r9, #1
beq Lfind_highest_ipl
/* r9 = SPL level of highest priority interrupt */
add r9, r9, #1
ldr r2, [r7, r9, lsl #2]
mvn r2, r2
orr r0, r0, r2
str r0, [r1]
ldr r0, Lcurrent_spl_level
ldr r1, [r0]
str r9, [r0]
stmfd sp!, {r1}
/* Update the IOMD irq masks */
bl _C_LABEL(irq_setmasks)
mrs r0, cpsr_all /* Enable IRQ's */
bic r0, r0, #I32_bit
msr cpsr_all, r0
ldr r7, [pc, #Lirqhandlers - . - 8]
/*
* take a copy of the IRQ request so that we can strip bits out of it
* note that we only use 24 bits with iomd2 chips
*/
ldr r4, Larm7500_ioc_found
ldr r4, [r4] /* get the flag */
cmp r4, #0
movne r11, r8 /* ARM7500 -> copy all bits */
biceq r11, r8, #0xff000000 /* !ARM7500 -> only use 24 bit */
/* ffs routine to find first irq to service */
/* standard trick to isolate bottom bit in a0 or 0 if a0 = 0 on entry */
rsb r4, r11, #0
ands r10, r11, r4
/*
* now r10 has at most 1 set bit, call this X
* if X = 0, branch to exit code
*/
beq exitirq
adr r5, Lirq_ffs_table
irqloop:
/*
* at this point:
* r5 = address of ffs table
* r7 = address of irq handlers table
* r8 = irq request
* r10 = bit of irq to be serviced
* r11 = bitmask of IRQ's to service
*/
/* find the set bit */
orr r9, r10, r10, lsl #4 /* X * 0x11 */
orr r9, r9, r9, lsl #6 /* X * 0x451 */
rsb r9, r9, r9, lsl #16 /* X * 0x0450fbaf */
/* fetch the bit number */
ldrb r9, [r5, r9, lsr #26 ]
/*
* r9 = irq to service
*/
/* apologies for the dogs dinner of code here, but it's in an attempt
* to minimise stalling on SA's, hence lots of things happen here:
* - getting address of handler, if it doesn't exist we call
* stray_irqhandler this is assumed to be rare so we don't
* care about performance for it
* - statinfo is updated
* - unsetting of the irq bit in r11
* - irq stats (if enabled) also get put in the mix
*/
ldr r4, Lcnt /* Stat info A */
ldr r6, [r7, r9, lsl #2] /* Get address of first handler structure */
ldr r1, [r4, #(V_INTR)] /* Stat info B */
teq r6, #0x00000000 /* Do we have a handler */
moveq r0, r8 /* IRQ requests as arg 0 */
addeq lr, pc, #nextirq - . - 8 /* return Address */
beq _C_LABEL(stray_irqhandler) /* call special handler */
#ifdef IRQSTATS
ldr r2, Lintrcnt
ldr r3, [r6, #(IH_NUM)]
#endif
/* stat info C */
add r1, r1, #0x00000001
str r1, [r4, #(V_INTR)]
#ifdef IRQSTATS
ldr r3, [r2, r3, lsl #2]!
#endif
bic r11, r11, r10 /* clear the IRQ bit */
#ifdef IRQSTATS
add r3, r3, #0x00000001
str r3, [r2]
#endif /* IRQSTATS */
irqchainloop:
ldr r0, [r6, #(IH_ARG)] /* Get argument pointer */
add lr, pc, #nextinchain - . - 8 /* return address */
teq r0, #0x00000000 /* If arg is zero pass stack frame */
addeq r0, sp, #8 /* ... stack frame [XXX needs care] */
ldr pc, [r6, #(IH_FUNC)] /* Call handler */
nextinchain:
ldr r6, [r6, #(IH_NEXT)] /* fetch next handler */
teq r0, #0x00000001 /* Was the irq serviced ? */
/* if it was it'll just fall through this: */
teqne r6, #0x00000000
bne irqchainloop
nextirq:
/* Check for next irq */
rsb r4, r11, #0
ands r10, r11, r4
/* check if there are anymore irq's to service */
bne irqloop
exitirq:
ldmfd sp!, {r2, r3}
ldr r9, Lcurrent_spl_level
ldr r1, Ldisabled_mask
str r2, [r9]
str r3, [r1]
bl _C_LABEL(irq_setmasks)
bl _C_LABEL(dosoftints) /* Handle the soft interrupts */
/* Manage AST's. Maybe this should be done as a soft interrupt ? */
ldr r0, [sp] /* Get the SPSR from stack */
and r0, r0, #(PSR_MODE) /* Test for USR32 mode before the IRQ */
teq r0, #(PSR_USR32_MODE)
ldreq r0, Lastpending /* Do we have an AST pending ? */
ldreq r1, [r0]
teqeq r1, #0x00000001
beq irqast /* call the AST handler */
/* Kill IRQ's in preparation for exit */
mrs r0, cpsr_all
orr r0, r0, #(I32_bit)
msr cpsr_all, r0
/* Decrement the nest count */
ldr r0, Lcurrent_intr_depth
ldr r1, [r0]
sub r1, r1, #1
str r1, [r0]
PULLFRAMEFROMSVCANDEXIT
/* NOT REACHED */
b . - 8
/*
* Ok, snag with current intr depth ...
* If ast() calls mi_sleep() the current_intr_depth will not be
* decremented until the process is woken up. This can result
* in the system believing it is still in the interrupt handler.
* If we are calling ast() then correct the current_intr_depth
* before the call.
*/
irqast:
mov r1, #0x00000000 /* Clear ast_pending */
str r1, [r0]
/* Kill IRQ's so we atomically decrement current_intr_depth */
mrs r2, cpsr_all
orr r3, r2, #(I32_bit)
msr cpsr_all, r3
/* Decrement the interrupt nesting count */
ldr r0, Lcurrent_intr_depth
ldr r1, [r0]
sub r1, r1, #1
str r1, [r0]
/* Restore IRQ's */
msr cpsr_all, r2
mov r0, sp
bl _C_LABEL(ast)
/* Kill IRQ's in preparation for exit */
mrs r0, cpsr_all
orr r0, r0, #(I32_bit)
msr cpsr_all, r0
PULLFRAMEFROMSVCANDEXIT
/* NOT REACHED */
b . - 8
Lspl_mask:
.word _C_LABEL(spl_mask) /* irq's allowed at current spl level */
Lcurrent_mask:
.word _C_LABEL(current_mask) /* irq's that are usable */
ENTRY(irq_setmasks)
/* Disable interrupts */
mrs r3, cpsr_all
orr r1, r3, #(I32_bit)
msr cpsr_all, r1
/* Calculate IOMD interrupt mask */
ldr r1, Lcurrent_mask /* All the enabled interrupts */
ldr r2, Lspl_mask /* Block due to current spl level */
ldr r1, [r1]
ldr r2, [r2]
and r1, r1, r2
ldr r2, Ldisabled_mask /* Block due to active interrupts */
ldr r2, [r2]
bic r1, r1, r2
ldr r0, Liomd_base
ldr r0, [r0] /* Point to the IOMD */
strb r1, [r0, #(IOMD_IRQMSKA << 2)] /* Set IRQ mask A */
mov r1, r1, lsr #8
strb r1, [r0, #(IOMD_IRQMSKB << 2)] /* Set IRQ mask B */
mov r1, r1, lsr #8
ldr r2, Larm7500_ioc_found
ldr r2, [r2]
cmp r2, #0
beq skip_setting_extended_DMA_mask
/* only for ARM7500's */
strb r1, [r0, #(IOMD_IRQMSKC << 2)]
mov r1, r1, lsr #8
and r2, r1, #0xef
strb r2, [r0, #(IOMD_IRQMSKD << 2)]
mov r1, r1, lsr #3
and r2, r1, #0x10
strb r2, [r0, #(IOMD_DMAMSK << 2)] /* Set DMA mask */
b continue_setting_masks
skip_setting_extended_DMA_mask:
/* non ARM7500's */
strb r1, [r0, #(IOMD_DMAMSK << 2)] /* Set DMA mask */
continue_setting_masks:
/* Restore old cpsr and exit */
msr cpsr_all, r3
mov pc, lr
Lcnt:
.word _C_LABEL(uvmexp)
Lintrcnt:
.word _C_LABEL(intrcnt)
Lirqhandlers:
.word _C_LABEL(irqhandlers) /* Pointer to array of irqhandlers */
Lastpending:
.word _C_LABEL(astpending)
#ifdef IRQSTATS
/* These symbols are used by vmstat */
.text
.global _C_LABEL(_intrnames)
_C_LABEL(_intrnames):
.word _C_LABEL(intrnames)
.data
.globl _C_LABEL(intrnames), _C_LABEL(eintrnames), _C_LABEL(intrcnt), _C_LABEL(sintrcnt), _C_LABEL(eintrcnt)
_C_LABEL(intrnames):
.asciz "interrupt 0 "
.asciz "interrupt 1 " /* reserved0 */
.asciz "interrupt 2 "
.asciz "interrupt 3 "
.asciz "interrupt 4 "
.asciz "interrupt 5 "
.asciz "interrupt 6 "
.asciz "interrupt 7 " /* reserved1 */
.asciz "interrupt 8 " /* reserved2 */
.asciz "interrupt 9 "
.asciz "interrupt 10 "
.asciz "interrupt 11 "
.asciz "interrupt 12 "
.asciz "interrupt 13 "
.asciz "interrupt 14 "
.asciz "interrupt 15 "
.asciz "dma channel 0"
.asciz "dma channel 1"
.asciz "dma channel 2"
.asciz "dma channel 3"
.asciz "interrupt 20 "
.asciz "interrupt 21 "
.asciz "reserved 3 "
.asciz "reserved 4 "
.asciz "exp card 0 "
.asciz "exp card 1 "
.asciz "exp card 2 "
.asciz "exp card 3 "
.asciz "exp card 4 "
.asciz "exp card 5 "
.asciz "exp card 6 "
.asciz "exp card 7 "
_C_LABEL(sintrnames):
.asciz "softclock "
.asciz "softnet "
.asciz "softserial "
.asciz "softintr 3 "
.asciz "softintr 4 "
.asciz "softintr 5 "
.asciz "softintr 6 "
.asciz "softintr 7 "
.asciz "softintr 8 "
.asciz "softintr 9 "
.asciz "softintr 10 "
.asciz "softintr 11 "
.asciz "softintr 12 "
.asciz "softintr 13 "
.asciz "softintr 14 "
.asciz "softintr 15 "
.asciz "softintr 16 "
.asciz "softintr 17 "
.asciz "softintr 18 "
.asciz "softintr 19 "
.asciz "softintr 20 "
.asciz "softintr 21 "
.asciz "softintr 22 "
.asciz "softintr 23 "
.asciz "softintr 24 "
.asciz "softintr 25 "
.asciz "softintr 26 "
.asciz "softintr 27 "
.asciz "softintr 28 "
.asciz "softintr 29 "
.asciz "softintr 30 "
.asciz "softintr 31 "
_C_LABEL(eintrnames):
.bss
.align 0
_C_LABEL(intrcnt):
.space 32*4 /* XXX Should be linked to number of interrupts */
_C_LABEL(sintrcnt):
.space 32*4 /* XXX Should be linked to number of interrupts */
_C_LABEL(eintrcnt):
#else /* IRQSTATS */
/* Dummy entries to keep vmstat happy */
.text
.globl _C_LABEL(intrnames), _C_LABEL(eintrnames), _C_LABEL(intrcnt), _C_LABEL(eintrcnt)
_C_LABEL(intrnames):
.long 0
_C_LABEL(eintrnames):
_C_LABEL(intrcnt):
.long 0
_C_LABEL(eintrcnt):
#endif /* IRQSTATS */
/* FIQ code */
ENTRY(fiq_setregs) /* Sets up the FIQ handler */
mrs r2, cpsr_all
mov r3, r2
bic r2, r2, #(PSR_MODE)
orr r2, r2, #(PSR_FIQ32_MODE)
msr cpsr_all, r2
ldr r8, [r0, #FH_R8] /* Update FIQ registers*/
ldr r9, [r0, #FH_R9]
ldr r10, [r0, #FH_R10]
ldr r11, [r0, #FH_R11]
ldr r12, [r0, #FH_R12]
ldr r13, [r0, #FH_R13]
msr cpsr_all, r3 /* Back to old mode */
mov pc, lr /* Exit */
ENTRY(fiq_getregs) /* Gets the FIQ registers */
mrs r2, cpsr_all
mov r3, r2
bic r2, r2, #(PSR_MODE)
orr r2, r2, #(PSR_FIQ32_MODE)
msr cpsr_all, r2
str r8, [r0, #FH_R8] /* Update FIQ registers*/
str r9, [r0, #FH_R9]
str r10, [r0, #FH_R10]
str r11, [r0, #FH_R11]
str r12, [r0, #FH_R12]
str r13, [r0, #FH_R13]
msr cpsr_all, r3 /* Back to old mode */
mov pc, lr /* Exit */
/* End of irq.S */

618
sys/arch/arm32/iomd/iomd_irqhandler.c
View File

@ -1,618 +0,0 @@
/* $NetBSD: iomd_irqhandler.c,v 1.29 2001/07/10 20:10:49 bjh21 Exp $ */
/*
* Copyright (c) 1994-1998 Mark Brinicombe.
* Copyright (c) 1994 Brini.
* All rights reserved.
*
* This code is derived from software written for Brini by Mark Brinicombe
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Mark Brinicombe
* for the NetBSD Project.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* IRQ/FIQ initialisation, claim, release and handler routines
*
* from: irqhandler.c,v 1.14 1997/04/02 21:52:19 christos Exp $
*/
#include "opt_irqstats.h"
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/syslog.h>
#include <sys/malloc.h>
#include <uvm/uvm_extern.h>
#include <arm32/iomd/iomdreg.h>
#include <arm32/iomd/iomdvar.h>
#include <machine/irqhandler.h>
#include <machine/cpu.h>
#include <machine/katelib.h>
irqhandler_t *irqhandlers[NIRQS];
fiqhandler_t *fiqhandlers;
int current_intr_depth;
u_int current_mask;
u_int actual_mask;
u_int disabled_mask;
u_int spl_mask;
u_int irqmasks[IPL_LEVELS];
u_int irqblock[NIRQS];
extern u_int soft_interrupts; /* Only so we can initialise it */
extern char *_intrnames;
/* Prototypes */
extern void zero_page_readonly __P((void));
extern void zero_page_readwrite __P((void));
extern int fiq_setregs __P((fiqhandler_t *));
extern int fiq_getregs __P((fiqhandler_t *));
extern void set_spl_masks __P((void));
/*
* void irq_init(void)
*
* Initialise the IRQ/FIQ sub system
*/
void
irq_init()
{
int loop;
/* Clear all the IRQ handlers and the irq block masks */
for (loop = 0; loop < NIRQS; ++loop) {
irqhandlers[loop] = NULL;
irqblock[loop] = 0;
}
/* Clear the FIQ handler */
fiqhandlers = NULL;
/* Clear the IRQ/FIQ masks in the IOMD */
IOMD_WRITE_BYTE(IOMD_IRQMSKA, 0x00);
IOMD_WRITE_BYTE(IOMD_IRQMSKB, 0x00);
switch (IOMD_ID) {
case RPC600_IOMD_ID:
break;
case ARM7500_IOC_ID:
case ARM7500FE_IOC_ID:
IOMD_WRITE_BYTE(IOMD_IRQMSKC, 0x00);
IOMD_WRITE_BYTE(IOMD_IRQMSKD, 0x00);
break;
default:
printf("Unknown IOMD id (%d) found in irq_init()\n", IOMD_ID);
};
IOMD_WRITE_BYTE(IOMD_FIQMSK, 0x00);
IOMD_WRITE_BYTE(IOMD_DMAMSK, 0x00);
/*
* Setup the irqmasks for the different Interrupt Priority Levels
* We will start with no bits set and these will be updated as handlers
* are installed at different IPL's.
*/
for (loop = 0; loop < IPL_LEVELS; ++loop)
irqmasks[loop] = 0;
current_intr_depth = 0;
current_mask = 0x00000000;
disabled_mask = 0x00000000;
actual_mask = 0x00000000;
spl_mask = 0x00000000;
soft_interrupts = 0x00000000;
set_spl_masks();
/* Enable IRQ's and FIQ's */
enable_interrupts(I32_bit | F32_bit);
}
/*
* int irq_claim(int irq, irqhandler_t *handler)
*
* Enable an IRQ and install a handler for it.
*/
int
irq_claim(irq, handler)
int irq;
irqhandler_t *handler;
{
int level;
int loop;
#ifdef DIAGNOSTIC
/* Sanity check */
if (handler == NULL)
panic("NULL interrupt handler\n");
if (handler->ih_func == NULL)
panic("Interrupt handler does not have a function\n");
#endif /* DIAGNOSTIC */
/*
* IRQ_INSTRUCT indicates that we should get the irq number
* from the irq structure
*/
if (irq == IRQ_INSTRUCT)
irq = handler->ih_num;
/* Make sure the irq number is valid */
if (irq < 0 || irq >= NIRQS)
return(-1);
/* Make sure the level is valid */
if (handler->ih_level < 0 || handler->ih_level >= IPL_LEVELS)
return(-1);
/* Attach handler at top of chain */
handler->ih_next = irqhandlers[irq];
irqhandlers[irq] = handler;
/*
* Reset the flags for this handler.
* As the handler is now in the chain mark it as active.
*/
handler->ih_flags = 0 | IRQ_FLAG_ACTIVE;
/*
* Record the interrupt number for accounting.
* Done here as the accounting number may not be the same as the
* IRQ number though for the moment they are
*/
handler->ih_num = irq;
#ifdef IRQSTATS
/* Get the interrupt name from the head of the list */
if (handler->ih_name) {
char *ptr = _intrnames + (irq * 14);
strcpy(ptr, " ");
strncpy(ptr, handler->ih_name,
min(strlen(handler->ih_name), 13));
} else {
char *ptr = _intrnames + (irq * 14);
sprintf(ptr, "irq %2d ", irq);
}
#endif /* IRQSTATS */
/*
* Update the irq masks.
* Find the lowest interrupt priority on the irq chain.
* Interrupt is allowable at priorities lower than this.
* If ih_level is out of range then don't bother to update
* the masks.
*/
if (handler->ih_level >= 0 && handler->ih_level < IPL_LEVELS) {
irqhandler_t *ptr;
/*
* Find the lowest interrupt priority on the irq chain.
* Interrupt is allowable at priorities lower than this.
*/
ptr = irqhandlers[irq];
if (ptr) {
int max_level;
level = ptr->ih_level - 1;
max_level = ptr->ih_level - 1;
while (ptr) {
if (ptr->ih_level - 1 < level)
level = ptr->ih_level - 1;
else if (ptr->ih_level - 1 > max_level)
max_level = ptr->ih_level - 1;
ptr = ptr->ih_next;
}
/* Clear out any levels that we cannot now allow */
while (max_level >=0 && max_level > level) {
irqmasks[max_level] &= ~(1 << irq);
--max_level;
}
while (level >= 0) {
irqmasks[level] |= (1 << irq);
--level;
}
}
#include "sl.h"
#include "ppp.h"
#if NSL > 0 || NPPP > 0
/* In the presence of SLIP or PPP, splimp > spltty. */
irqmasks[IPL_NET] &= irqmasks[IPL_TTY];
#endif
}
/*
* We now need to update the irqblock array. This array indicates
* what other interrupts should be blocked when interrupt is asserted
* This basically emulates hardware interrupt priorities e.g. by
* blocking all other IPL_BIO interrupts with an IPL_BIO interrupt
* is asserted. For each interrupt we find the highest IPL and set
* the block mask to the interrupt mask for that level.
*/
for (loop = 0; loop < NIRQS; ++loop) {
irqhandler_t *ptr;
ptr = irqhandlers[loop];
if (ptr) {
/* There is at least 1 handler so scan the chain */
level = ptr->ih_level;
while (ptr) {
if (ptr->ih_level > level)
level = ptr->ih_level;
ptr = ptr->ih_next;
}
irqblock[loop] = ~irqmasks[level];
} else
/* No handlers for this irq so nothing to block */
irqblock[loop] = 0;
}
enable_irq(irq);
set_spl_masks();
return(0);
}
/*
* int irq_release(int irq, irqhandler_t *handler)
*
* Disable an IRQ and remove a handler for it.
*/
int
irq_release(irq, handler)
int irq;
irqhandler_t *handler;
{
int level;
int loop;
irqhandler_t *irqhand;
irqhandler_t **prehand;
#ifdef IRQSTATS
extern char *_intrnames;
#endif
/*
* IRQ_INSTRUCT indicates that we should get the irq number
* from the irq structure
*/
if (irq == IRQ_INSTRUCT)
irq = handler->ih_num;
/* Make sure the irq number is valid */
if (irq < 0 || irq >= NIRQS)
return(-1);
/* Locate the handler */
irqhand = irqhandlers[irq];
prehand = &irqhandlers[irq];
while (irqhand && handler != irqhand) {
prehand = &irqhand->ih_next;
irqhand = irqhand->ih_next;
}
/* Remove the handler if located */
if (irqhand)
*prehand = irqhand->ih_next;
else
return(-1);
/* Now the handler has been removed from the chain mark is as inactive */
irqhand->ih_flags &= ~IRQ_FLAG_ACTIVE;
/* Make sure the head of the handler list is active */
if (irqhandlers[irq])
irqhandlers[irq]->ih_flags |= IRQ_FLAG_ACTIVE;
#ifdef IRQSTATS
/* Get the interrupt name from the head of the list */
if (irqhandlers[irq] && irqhandlers[irq]->ih_name) {
char *ptr = _intrnames + (irq * 14);
strcpy(ptr, " ");
strncpy(ptr, irqhandlers[irq]->ih_name,
min(strlen(irqhandlers[irq]->ih_name), 13));
} else {
char *ptr = _intrnames + (irq * 14);
sprintf(ptr, "irq %2d ", irq);
}
#endif /* IRQSTATS */
/*
* Update the irq masks.
* If ih_level is out of range then don't bother to update
* the masks.
*/
if (handler->ih_level >= 0 && handler->ih_level < IPL_LEVELS) {
irqhandler_t *ptr;
/* Clean the bit from all the masks */
for (level = 0; level < IPL_LEVELS; ++level)
irqmasks[level] &= ~(1 << irq);
/*
* Find the lowest interrupt priority on the irq chain.
* Interrupt is allowable at priorities lower than this.
*/
ptr = irqhandlers[irq];
if (ptr) {
level = ptr->ih_level - 1;
while (ptr) {
if (ptr->ih_level - 1 < level)
level = ptr->ih_level - 1;
ptr = ptr->ih_next;
}
while (level >= 0) {
irqmasks[level] |= (1 << irq);
--level;
}
}
}
/*
* We now need to update the irqblock array. This array indicates
* what other interrupts should be blocked when interrupt is asserted
* This basically emulates hardware interrupt priorities e.g. by
* blocking all other IPL_BIO interrupts with an IPL_BIO interrupt
* is asserted. For each interrupt we find the highest IPL and set
* the block mask to the interrupt mask for that level.
*/
for (loop = 0; loop < NIRQS; ++loop) {
irqhandler_t *ptr;
ptr = irqhandlers[loop];
if (ptr) {
/* There is at least 1 handler so scan the chain */
level = ptr->ih_level;
while (ptr) {
if (ptr->ih_level > level)
level = ptr->ih_level;
ptr = ptr->ih_next;
}
irqblock[loop] = ~irqmasks[level];
} else
/* No handlers for this irq so nothing to block */
irqblock[loop] = 0;
}
/*
* Disable the appropriate mask bit if there are no handlers left for
* this IRQ.
*/
if (irqhandlers[irq] == NULL)
disable_irq(irq);
set_spl_masks();
return(0);
}
void *
intr_claim(irq, level, name, ih_func, ih_arg)
int irq;
int level;
const char *name;
int (*ih_func) __P((void *));
void *ih_arg;
{
irqhandler_t *ih;
ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT);
if (!ih)
panic("intr_claim(): Cannot malloc handler memory\n");
ih->ih_level = level;
ih->ih_name = name;
ih->ih_func = ih_func;
ih->ih_arg = ih_arg;
ih->ih_flags = 0;
if (irq_claim(irq, ih) != 0)
return(NULL);
return(ih);
}
int
intr_release(arg)
void *arg;
{
irqhandler_t *ih = (irqhandler_t *)arg;
if (irq_release(ih->ih_num, ih) == 0) {
free(ih, M_DEVBUF);
return(0);
}
return(1);
}
#if 0
u_int
disable_interrupts(mask)
u_int mask;
{
u_int cpsr;
cpsr = SetCPSR(mask, mask);
return(cpsr);
}
u_int
restore_interrupts(old_cpsr)
u_int old_cpsr;
{
int mask = I32_bit | F32_bit;
return(SetCPSR(mask, old_cpsr & mask));
}
u_int
enable_interrupts(mask)
u_int mask;
{
return(SetCPSR(mask, 0));
}
#endif
/*
* void disable_irq(int irq)
*
* Disables a specific irq. The irq is removed from the master irq mask
*/
void
disable_irq(irq)
int irq;
{
u_int oldirqstate;
oldirqstate = disable_interrupts(I32_bit);
current_mask &= ~(1 << irq);
irq_setmasks();
restore_interrupts(oldirqstate);
}
/*
* void enable_irq(int irq)
*
* Enables a specific irq. The irq is added to the master irq mask
* This routine should be used with caution. A handler should already
* be installed.
*/
void
enable_irq(irq)
int irq;
{
u_int oldirqstate;
oldirqstate = disable_interrupts(I32_bit);
current_mask |= (1 << irq);
irq_setmasks();
restore_interrupts(oldirqstate);
}
/*
* void stray_irqhandler(u_int mask)
*
* Handler for stray interrupts. This gets called if a handler cannot be
* found for an interrupt.
*/
void
stray_irqhandler(mask)
u_int mask;
{
static u_int stray_irqs = 0;
if (++stray_irqs <= 8)
log(LOG_ERR, "Stray interrupt %08x%s\n", mask,
stray_irqs >= 8 ? ": stopped logging" : "");
}
/*
* int fiq_claim(fiqhandler_t *handler)
*
* Claim FIQ's and install a handler for them.
*/
int
fiq_claim(handler)
fiqhandler_t *handler;
{
/* Fail if the FIQ's are already claimed */
if (fiqhandlers)
return(-1);
if (handler->fh_size > 0xc0)
return(-1);
/* Install the handler */
fiqhandlers = handler;
/* Now we have to actually install the FIQ handler */
/* Eventually we will copy this down but for the moment ... */
zero_page_readwrite();
WriteWord(0x0000003c, (u_int) handler->fh_func);
zero_page_readonly();
/* We must now set up the FIQ registers */
fiq_setregs(handler);
/* Set up the FIQ mask */
IOMD_WRITE_BYTE(IOMD_FIQMSK, handler->fh_mask);
/* Make sure that the FIQ's are enabled */
enable_interrupts(F32_bit);
return(0);
}
/*
* int fiq_release(fiqhandler_t *handler)
*
* Release FIQ's and remove a handler for them.
*/
int
fiq_release(handler)
fiqhandler_t *handler;
{
/* Fail if the handler is wrong */
if (fiqhandlers != handler)
return(-1);
/* Disable FIQ interrupts */
disable_interrupts(F32_bit);
/* Clear up the FIQ mask */
IOMD_WRITE_BYTE(IOMD_FIQMSK, 0x00);
/* Retrieve the FIQ registers */
fiq_getregs(handler);
/* Remove the handler */
fiqhandlers = NULL;
return(0);
}
/* End of irqhandler.c */

214
sys/arch/arm32/iomd/iomdreg.h
View File

@ -1,214 +0,0 @@
/* $NetBSD: iomdreg.h,v 1.12 2001/04/23 22:17:09 bjh21 Exp $ */
/*
* Copyright (c) 1994-1997 Mark Brinicombe.
* Copyright (c) 1994 Brini.
* All rights reserved.
*
* This code is derived from software written for Brini by Mark Brinicombe
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Mark Brinicombe.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RiscBSD kernel project
*
* iomd.h
*
* IOMD registers
*
* Created : 18/09/94
*
* Based on kate/display/iomd.h
*/
#define IOMD_HW_BASE 0x03200000
#define IOMD_BASE 0xf6000000
#define IOMD_IOCR 0x00000000
#define IOMD_KBDDAT 0x00000001
#define IOMD_KBDCR 0x00000002
#define IOMD_IOLINES 0x00000003 /* ARM7500FE */
#define IOMD_IRQSTA 0x00000004
#define IOMD_IRQRQA 0x00000005
#define IOMD_IRQMSKA 0x00000006
#define IOMD_SUSPEND 0x00000007 /* ARM7500 */
#define IOMD_IRQSTB 0x00000008
#define IOMD_IRQRQB 0x00000009
#define IOMD_IRQMSKB 0x0000000a
#define IOMD_STOP 0x0000000b /* ARM7500 */
#define IOMD_FIQST 0x0000000c
#define IOMD_FIQRQ 0x0000000d
#define IOMD_FIQMSK 0x0000000e
#define IOMD_CLKCTL 0x0000000f /* ARM7500 */
#define IOMD_T0LOW 0x00000010
#define IOMD_T0HIGH 0x00000011
#define IOMD_T0GO 0x00000012
#define IOMD_T0LATCH 0x00000013
#define IOMD_T1LOW 0x00000014
#define IOMD_T1HIGH 0x00000015
#define IOMD_T1GO 0x00000016
#define IOMD_T1LATCH 0x00000017
/*
* For ARM7500, it's not really a IOMD device.
*/
#define IOMD_IRQSTC 0x00000018 /* ARM7500 */
#define IOMD_IRQRQC 0x00000019 /* ARM7500 */
#define IOMD_IRQMSKC 0x0000001a /* ARM7500 */
#define IOMD_VIDMUX 0x0000001b /* ARM7500 */
#define IOMD_IRQSTD 0x0000001c /* ARM7500 */
#define IOMD_IRQRQD 0x0000001d /* ARM7500 */
#define IOMD_IRQMSKD 0x0000001e /* ARM7500 */
#define IOMD_ROMCR0 0x00000020
#define IOMD_ROMCR1 0x00000021
#define IOMD_DRAMCR 0x00000022 /* !ARM7500 */
#define IOMD_VREFCR 0x00000023 /* !ARM7500 */
#define IOMD_REFCR 0x00000023 /* ARM7500 */
#define IOMD_FSIZE 0x00000024
#define IOMD_ID0 0x00000025
#define IOMD_ID1 0x00000026
#define IOMD_VERSION 0x00000027
#define IOMD_MOUSEX 0x00000028
#define IOMD_MOUSEY 0x00000029
#define IOMD_MSDATA 0x0000002a /* ARM7500 */
#define IOMD_MSCR 0x0000002b /* ARM7500 */
#define IOMD_DMATCR 0x00000030
#define IOMD_IOTCR 0x00000031
#define IOMD_ECTCR 0x00000032
#define IOMD_DMAEXT 0x00000033 /* !ARM7500 */
#define IOMD_ASTCR 0x00000033 /* ARM7500 */
#define IOMD_DRAMWID 0x00000034 /* ARM7500 */
#define IOMD_SELFREF 0x00000035 /* ARM7500 */
#define IOMD_ATODICR 0x00000038 /* ARM7500 */
#define IOMD_ATODSR 0x00000039 /* ARM7500 */
#define IOMD_ATODCR 0x0000003a /* ARM7500 */
#define IOMD_ATODCNT1 0x0000003b /* ARM7500 */
#define IOMD_ATODCNT2 0x0000003c /* ARM7500 */
#define IOMD_ATODCNT3 0x0000003d /* ARM7500 */
#define IOMD_ATODCNT4 0x0000003e /* ARM7500 */
#define IOMD_DMA_SIZE 24
#define IOMD_DMA_SPACING 32
#define IOMD_IO0CURA 0x00000040
#define IOMD_IO0ENDA 0x00000041
#define IOMD_IO0CURB 0x00000042
#define IOMD_IO0ENDB 0x00000043
#define IOMD_IO0CR 0x00000044
#define IOMD_IO0ST 0x00000045
#define IOMD_IO1CURA 0x00000048
#define IOMD_IO1ENDA 0x00000049
#define IOMD_IO1CURB 0x0000004a
#define IOMD_IO1ENDB 0x0000004b
#define IOMD_IO1CR 0x0000004c
#define IOMD_IO1ST 0x0000004d
#define IOMD_IO2CURA 0x00000050
#define IOMD_IO2ENDA 0x00000051
#define IOMD_IO2CURB 0x00000052
#define IOMD_IO2ENDB 0x00000053
#define IOMD_IO2CR 0x00000054
#define IOMD_IO2ST 0x00000055
#define IOMD_IO3CURA 0x00000058
#define IOMD_IO3ENDA 0x00000059
#define IOMD_IO3CURB 0x0000005a
#define IOMD_IO3ENDB 0x0000005b
#define IOMD_IO3CR 0x0000005c
#define IOMD_IO3ST 0x0000005d
#define IOMD_SD0CURA 0x00000060
#define IOMD_SD0ENDA 0x00000061
#define IOMD_SD0CURB 0x00000062
#define IOMD_SD0ENDB 0x00000063
#define IOMD_SD0CR 0x00000064
#define IOMD_SD0ST 0x00000065
#define IOMD_SD1CURA 0x00000068
#define IOMD_SD1ENDA 0x00000069
#define IOMD_SD1CURB 0x0000006a
#define IOMD_SD1ENDB 0x0000006b
#define IOMD_SD1CR 0x0000006c
#define IOMD_SD1ST 0x0000006d
#define IOMD_CURSCUR 0x00000070
#define IOMD_CURSINIT 0x00000071
#define IOMD_VIDCUR 0x00000074
#define IOMD_VIDEND 0x00000075
#define IOMD_VIDSTART 0x00000076
#define IOMD_VIDINIT 0x00000077
#define IOMD_VIDCR 0x00000078
#define IOMD_DMAST 0x0000007c
#define IOMD_DMARQ 0x0000007d
#define IOMD_DMAMSK 0x0000007e
#define IOMD_SIZE 0x100 /* XXX - should be words ? */
/*
* Ok these mouse buttons are not strickly part of the iomd but
* this register is required if the IOMD supports a quadrature mouse
*/
#define IO_HW_MOUSE_BUTTONS 0x03210000
#define IO_MOUSE_BUTTONS 0xf6010000
#define MOUSE_BUTTON_RIGHT 0x10
#define MOUSE_BUTTON_MIDDLE 0x20
#define MOUSE_BUTTON_LEFT 0x40
#define FREQCON (iomd_base + 0x40000)
#define RPC600_IOMD_ID 0xd4e7
#define ARM7500_IOC_ID 0x5b98
#define ARM7500FE_IOC_ID 0xaa7c
#define IOMD_ADDRESS(reg) (iomd_base + (reg << 2))
#define IOMD_WRITE_BYTE(reg, val) \
(*((volatile unsigned char *)(IOMD_ADDRESS(reg))) = (val))
#define IOMD_WRITE_WORD(reg, val) \
(*((volatile unsigned int *)(IOMD_ADDRESS(reg))) = (val))
#define IOMD_READ_BYTE(reg) \
(*((volatile unsigned char *)(IOMD_ADDRESS(reg))))
#define IOMD_READ_WORD(reg) \
(*((volatile unsigned int *)(IOMD_ADDRESS(reg))))
#define IOMD_ID (IOMD_READ_BYTE(IOMD_ID0) | (IOMD_READ_BYTE(IOMD_ID1) << 8))
/* End of iomdreg.h */

124
sys/arch/arm32/iomd/iomdvar.h
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@ -1,124 +0,0 @@
/* $NetBSD: iomdvar.h,v 1.3 2001/03/02 01:46:57 reinoud Exp $ */
/*
* Copyright (c) 1997 Mark Brinicombe.
* Copyright (c) 1997 Causality Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Mark Brinicombe
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RiscBSD kernel project
*
* iomd_bus.h
*
* Created : 02/02/97
*/
#include <machine/bus.h>
/*
* Attach args for iomd_clock device
*/
struct clk_attach_args {
const char *ca_name; /* device name*/
bus_space_tag_t ca_iot; /* Bus tag */
bus_space_handle_t ca_ioh; /* Bus handle */
int ca_irq; /* IRQ number */
};
/*
* Attach args for iomd device
*/
/*
* Attach args for qms device
*/
struct qms_attach_args {
const char *qa_name; /* device name*/
bus_space_tag_t qa_iot; /* Bus tag */
bus_space_handle_t qa_ioh; /* Bus handle */
bus_space_handle_t qa_ioh_but; /* Bus handle */
int qa_irq; /* IRQ number */
};
/*
* Attach args for pms device
*/
struct pms_attach_args {
const char *pa_name; /* device name*/
bus_space_tag_t pa_iot; /* Bus tag */
bus_space_handle_t pa_ioh; /* Bus handle */
int pa_irq; /* IRQ number */
};
/*
* Attach args for kbd device
*/
struct kbd_attach_args {
const char *ka_name; /* device name*/
bus_space_tag_t ka_iot; /* Bus tag */
bus_space_handle_t ka_ioh; /* Bus handle */
int ka_rxirq; /* IRQ number */
int ka_txirq; /* IRQ number */
};
/*
* Attach args for iic device
*/
struct iic_attach_args {
const char *ia_name; /* device name */
bus_space_tag_t ia_iot; /* Bus tag */
bus_space_handle_t ia_ioh; /* Bus handle */
int ia_irq; /* IRQ number */
};
/*
* NOTE: All these attach structures and a const char *name as the
* first field for identification.
*/
union iomd_attach_args {
struct kbd_attach_args ia_kbd;
struct pms_attach_args ia_pms;
struct qms_attach_args ia_qms;
struct iic_attach_args ia_iic;
struct clk_attach_args ia_clk;
};
/*
* IOMD_BASE register variable
*/
extern u_int32_t iomd_base;
/* End of iomdvar.h */

118
sys/arch/arm32/iomd/kbd_iomd.c
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@ -1,118 +0,0 @@
/* $NetBSD: kbd_iomd.c,v 1.1 1997/10/14 11:16:37 mark Exp $ */
/*
* Copyright (c) 1994-1997 Mark Brinicombe.
* Copyright (c) 1994 Brini.
* All rights reserved.
*
* This code is derived from software written for Brini by Mark Brinicombe
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Mark Brinicombe.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RiscBSD kernel project
*
* kbd.c
*
* Keyboard driver functions
*
* Created : 09/10/94
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/proc.h>
#include <sys/device.h>
#include <sys/tty.h>
#include <sys/select.h>
#include <sys/poll.h>
#include <machine/bus.h>
#include <machine/irqhandler.h>
#include <machine/kbd.h>
#include <arm32/dev/kbdvar.h>
#include <arm32/iomd/iomdvar.h>
/* Local function prototypes */
static int kbd_iomd_probe __P((struct device *, struct cfdata *, void *));
static void kbd_iomd_attach __P((struct device *, struct device *, void *));
extern struct kbd_softc *console_kbd;
/* Device structures */
struct cfattach kbd_iomd_ca = {
sizeof(struct kbd_softc), kbd_iomd_probe, kbd_iomd_attach
};
static int
kbd_iomd_probe(parent, cf, aux)
struct device *parent;
struct cfdata *cf;
void *aux;
{
struct kbd_attach_args *ka = aux;
if (strcmp(ka->ka_name, "kbd") == 0)
return(1);
return(0);
}
static void
kbd_iomd_attach(parent, self, aux)
struct device *parent;
struct device *self;
void *aux;
{
struct kbd_softc *sc = (void *)self;
struct kbd_attach_args *ka = aux;
int error;
sc->sc_iot = ka->ka_iot;
sc->sc_ioh = ka->ka_ioh;
error = kbdreset(sc);
if (error == 1)
printf(": Cannot enable keyboard");
else if (error == 2)
printf(": No keyboard present");
printf("\n");
sc->sc_ih = intr_claim(ka->ka_rxirq, IPL_TTY, "kbd rx", kbdintr, sc);
if (!sc->sc_ih)
panic("%s: Cannot claim RX interrupt\n", sc->sc_device.dv_xname);
if (sc->sc_device.dv_unit == 0)
console_kbd = sc;
}
/* End of kbd_iomd.c */

114
sys/arch/arm32/iomd/pms_iomd.c
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@ -1,114 +0,0 @@
/* $NetBSD: pms_iomd.c,v 1.3 1999/01/23 22:18:43 sommerfe Exp $ */
/*-
* Copyright (c) 1996 D.C. Tsen
* Copyright (c) 1994 Charles M. Hannum.
* Copyright (c) 1992, 1993 Erik Forsberg.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the RiscBSD team.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* from:pms.c,v 1.24 1995/12/24 02:30:28 mycroft Exp
*/
/*
* Ported from 386 version of PS/2 mouse driver.
* D.C. Tsen
*/
#include <sys/param.h>
#include <sys/kernel.h>
#include <sys/systm.h>
#include <sys/buf.h>
#include <sys/malloc.h>
#include <sys/proc.h>
#include <sys/device.h>
#include <sys/select.h>
#include <sys/tty.h>
#include <machine/bus.h>
#include <machine/irqhandler.h>
#include <arm32/dev/pmsvar.h>
#include <arm32/iomd/iomdvar.h>
static int pms_iomd_probe __P((struct device *, struct cfdata *, void *));
static void pms_iomd_attach __P((struct device *, struct device *, void *));
static void pms_iomd_intenable __P((struct pms_softc *sc, int enable));
struct cfattach opms_iomd_ca = {
sizeof(struct pms_softc), pms_iomd_probe, pms_iomd_attach
};
static int
pms_iomd_probe(parent, cf, aux)
struct device *parent;
struct cfdata *cf;
void *aux;
{
struct pms_attach_args *pa = aux;
if (strcmp(pa->pa_name, "pms") == 0)
return(1);
return(0);
}
static void
pms_iomd_attach(parent, self, aux)
struct device *parent, *self;
void *aux;
{
struct pms_softc *sc = (void *)self;
struct pms_attach_args *pa = aux;
sc->sc_iot = pa->pa_iot;
sc->sc_ioh = pa->pa_ioh;
sc->sc_irqnum = pa->pa_irq;
sc->sc_intenable = pms_iomd_intenable;
if (pmsinit(sc) != 1) {
printf("Mouse not present\n");
}
printf("\n");
}
static void
pms_iomd_intenable(sc, enable)
struct pms_softc *sc;
int enable;
{
if (enable) {
sc->sc_ih = intr_claim(sc->sc_irqnum, IPL_TTY, "pms", pmsintr, sc);
if (!sc->sc_ih)
panic("%s: Cannot claim interrupt\n", sc->sc_dev.dv_xname);
} else {
if (intr_release(sc->sc_ih) != 0)
panic("%s: Cannot release IRQ\n", sc->sc_dev.dv_xname);
}
}
/* End of pms_iomd.c */

138
sys/arch/arm32/iomd/qms_iomd.c
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@ -1,138 +0,0 @@
/* $NetBSD: qms_iomd.c,v 1.3 2001/02/25 23:59:48 reinoud Exp $ */
/*
* Copyright (c) Scott Stevens 1995 All rights reserved
* Copyright (c) Melvin Tang-Richardson 1995 All rights reserved
* Copyright (c) Mark Brinicombe 1995 All rights reserved
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the RiscBSD team.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Quadrature mouse driver
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/types.h>
#include <sys/device.h>
#include <sys/proc.h>
#include <sys/select.h>
#include <sys/tty.h>
#include <machine/bus.h>
#include <machine/irqhandler.h>
#include <arm32/dev/qmsvar.h>
#include <arm32/iomd/iomdvar.h>
extern int iomd_found;
#define TIMER1_COUNT 40000 /* 50Hz */
static int qms_iomd_probe __P((struct device *, struct cfdata *, void *));
static void qms_iomd_attach __P((struct device *, struct device *, void *));
static void qms_iomd_intenable __P((struct qms_softc *sc, int enable));
struct cfattach qms_iomd_ca = {
sizeof(struct qms_softc), qms_iomd_probe, qms_iomd_attach
};
static int
qms_iomd_probe(parent, cf, aux)
struct device *parent;
struct cfdata *cf;
void *aux;
{
struct qms_attach_args *qa = aux;
if (strcmp(qa->qa_name, "qms") == 0)
return(1);
return(0);
}
static void
qms_iomd_attach(parent, self, aux)
struct device *parent;
struct device *self;
void *aux;
{
struct qms_softc *sc = (void *)self;
struct qms_attach_args *qa = aux;
sc->sc_iot = qa->qa_iot;
sc->sc_ioh = qa->qa_ioh;
sc->sc_butioh = qa->qa_ioh_but;
sc->sc_irqnum = qa->qa_irq;
sc->sc_intenable = qms_iomd_intenable;
/* if (sc->sc_irqnum == IRQ_TIMER1) {
WriteByte(IOMD_T1LOW, (TIMER1_COUNT >> 0) & 0xff);
WriteByte(IOMD_T1HIGH, (TIMER1_COUNT >> 8) & 0xff);
WriteByte(IOMD_T1GO, 0);
}
*/
qmsattach(sc);
printf("\n");
}
static void
qms_iomd_intenable(sc, enable)
struct qms_softc *sc;
int enable;
{
if (enable) {
sc->sc_ih = intr_claim(sc->sc_irqnum, IPL_TTY, "qms", qmsintr, sc);
if (!sc->sc_ih)
panic("%s: Cannot claim interrupt\n", sc->sc_device.dv_xname);
} else {
if (intr_release(sc->sc_ih) != 0)
panic("%s: Cannot release IRQ\n", sc->sc_device.dv_xname);
}
}
#ifdef DIAGNOSTIC
#include <arm32/iomd/iomdreg.h>
#include <machine/katelib.h>
void
qms_console_freeze()
{
if (!iomd_found) return;
/* Middle mouse button freezes the display while active */
while ((ReadByte(IO_MOUSE_BUTTONS) & MOUSE_BUTTON_MIDDLE) == 0);
/* Left mouse button slows down the display speed */
if ((ReadByte(IO_MOUSE_BUTTONS) & MOUSE_BUTTON_LEFT) == 0)
delay(5000);
}
#endif /* DIAGNOSTIC */
/* End of qms_iomd.c */

124
sys/arch/arm32/iomd/rpckbd_iomd.c
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@ -1,124 +0,0 @@
/* $NetBSD: rpckbd_iomd.c,v 1.2 2001/04/12 20:15:07 reinoud Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Reinoud Zandijk
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* rpckbd attach routined for iomd
*
* Created: 13/03/2001
*
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/proc.h>
#include <sys/device.h>
#include <sys/tty.h>
#include <sys/select.h>
#include <sys/poll.h>
#include <machine/bus.h>
#include <machine/irqhandler.h>
#include <machine/kbd.h>
#include <arm32/dev/rpckbdvar.h>
#include <arm32/iomd/iomdreg.h>
#include <arm32/iomd/iomdvar.h>
/* Local function prototypes */
static int rpckbd_iomd_probe __P((struct device *, struct cfdata *, void *));
static void rpckbd_iomd_attach __P((struct device *, struct device *, void *));
extern struct rpckbd_softc console_kbd;
/* Device structures */
struct cfattach rpckbd_iomd_ca = {
sizeof(struct rpckbd_softc), rpckbd_iomd_probe, rpckbd_iomd_attach
};
static int
rpckbd_iomd_probe(parent, cf, aux)
struct device *parent;
struct cfdata *cf;
void *aux;
{
struct kbd_attach_args *ka = aux;
if (strcmp(ka->ka_name, "rpckbd") == 0)
return(1);
return(0);
}
static void
rpckbd_iomd_attach(parent, self, aux)
struct device *parent;
struct device *self;
void *aux;
{
struct rpckbd_softc *sc = (void *)self;
struct kbd_attach_args *ka = aux;
int error, isconsole;
#ifdef COMCONSOLE
isconsole = 0;
#else
isconsole = 1;
console_kbd.sc_device = sc->sc_device;
sc = &console_kbd;
#endif
sc->sc_iot = ka->ka_iot;
sc->sc_ioh = ka->ka_ioh;
error = rpckbd_init((void *)sc, isconsole, IOMD_KBDDAT, IOMD_KBDCR);
if (error == 1)
printf(": Cannot enable keyboard");
else if (error == 2)
printf(": No keyboard present");
if (error == 0) {
sc->sc_ih = intr_claim(ka->ka_rxirq, IPL_TTY, "kbd rx", rpckbd_intr, sc);
if (!sc->sc_ih)
panic("%s: Cannot claim RX interrupt\n", sc->sc_device.dv_xname);
};
}
/* End of rpckbd_iomd.c */

120
sys/arch/arm32/iomd/wsqms_iomd.c
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@ -1,120 +0,0 @@
/* $NetBSD: wsqms_iomd.c,v 1.1 2001/04/14 19:22:45 reinoud Exp $ */
/*-
* Copyright (c) 2001 Reinoud Zandijk
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Reinoud Zandijk
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*
* Quadratic mouse driver for the wscons as used in the IOMD; config glue...
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/types.h>
#include <sys/device.h>
#include <sys/proc.h>
#include <sys/select.h>
#include <sys/tty.h>
#include <machine/bus.h>
#include <machine/irqhandler.h>
#include <arm32/dev/wsqmsvar.h>
#include <arm32/iomd/iomdvar.h>
static int wsqms_iomd_probe __P((struct device *, struct cfdata *, void *));
static void wsqms_iomd_attach __P((struct device *, struct device *, void *));
static void wsqms_iomd_intenable __P((struct wsqms_softc *sc, int enable));
struct cfattach wsqms_iomd_ca = {
sizeof(struct wsqms_softc), wsqms_iomd_probe, wsqms_iomd_attach
};
static int
wsqms_iomd_probe(parent, cf, aux)
struct device *parent;
struct cfdata *cf;
void *aux;
{
struct qms_attach_args *qa = aux;
if (strcmp(qa->qa_name, "wsqms") == 0)
return(1);
return(0);
}
static void
wsqms_iomd_attach(parent, self, aux)
struct device *parent;
struct device *self;
void *aux;
{
struct wsqms_softc *sc = (void *)self;
struct qms_attach_args *qa = aux;
sc->sc_device = *self;
sc->sc_iot = qa->qa_iot;
sc->sc_ioh = qa->qa_ioh;
sc->sc_butioh = qa->qa_ioh_but;
sc->sc_irqnum = qa->qa_irq;
sc->sc_intenable = wsqms_iomd_intenable;
wsqms_attach(sc, self);
}
static void
wsqms_iomd_intenable(sc, enable)
struct wsqms_softc *sc;
int enable;
{
if (enable) {
sc->sc_ih = intr_claim(sc->sc_irqnum, IPL_TTY, "wsqms", wsqms_intr, sc);
if (!sc->sc_ih)
panic("%s: Cannot claim interrupt\n", sc->sc_device.dv_xname);
} else {
if (intr_release(sc->sc_ih) != 0)
panic("%s: Cannot release IRQ\n", sc->sc_device.dv_xname);
}
}
/* End of wsqms_iomd.c */

321
sys/arch/arm32/podulebus/amps.c
View File

@ -1,321 +0,0 @@
/* $NetBSD: amps.c,v 1.6 2001/03/18 16:58:55 bjh21 Exp $ */
/*-
* Copyright (c) 1997 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Mark Brinicombe of Causality Limited.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* Card driver and probe and attach functions to use generic 16550 com
* driver for the Atomwide multiport serial podule
*/
/*
* Thanks to Martin Coulson, Atomwide, for providing the hardware
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/ioctl.h>
#include <sys/select.h>
#include <sys/tty.h>
#include <sys/proc.h>
#include <sys/user.h>
#include <sys/conf.h>
#include <sys/file.h>
#include <sys/uio.h>
#include <sys/kernel.h>
#include <sys/syslog.h>
#include <sys/types.h>
#include <sys/device.h>
#include <machine/irqhandler.h>
#include <machine/io.h>
#include <machine/bus.h>
#include <arm32/podulebus/podulebus.h>
#include <arm32/podulebus/ampsreg.h>
#include <dev/ic/comreg.h>
#include <dev/ic/comvar.h>
#include <dev/podulebus/podules.h>
#include "locators.h"
/*
* Atomwide Mulit-port serial podule device.
*
* This probes and attaches the top level multi-port serial device to the
* podulebus. It then configures the child com devices.
*/
/*
* Atomwide Multi-port serial card softc structure.
*
* Contains the device node, podule information and global information
* required by the driver such as the card version and the interrupt mask.
*/
struct amps_softc {
struct device sc_dev; /* device node */
podule_t *sc_podule; /* Our podule info */
int sc_podule_number; /* Our podule number */
bus_space_tag_t sc_iot; /* Bus tag */
};
int amps_probe __P((struct device *, struct cfdata *, void *));
void amps_attach __P((struct device *, struct device *, void *));
void amps_shutdown __P((void *arg));
struct cfattach amps_ca = {
sizeof(struct amps_softc), amps_probe, amps_attach
};
/*
* Attach arguments for child devices.
* Pass the podule details, the parent softc and the channel
*/
struct amps_attach_args {
bus_space_tag_t aa_iot; /* bus space tag */
unsigned int aa_base; /* base address for port */
int aa_port; /* serial port number */
podulebus_intr_handle_t aa_irq; /* IRQ number */
};
/*
* Define prototypes for custom bus space functions.
*/
/* Print function used during child config */
int
amps_print(aux, name)
void *aux;
const char *name;
{
struct amps_attach_args *aa = aux;
if (!name)
printf(", port %d", aa->aa_port);
return(QUIET);
}
/*
* Card probe function
*
* Just match the manufacturer and podule ID's
*/
int
amps_probe(parent, cf, aux)
struct device *parent;
struct cfdata *cf;
void *aux;
{
struct podule_attach_args *pa = (void *)aux;
if (matchpodule(pa, MANUFACTURER_ATOMWIDE2, PODULE_ATOMWIDE2_SERIAL, -1) == 0)
return(0);
return(1);
}
/*
* Card attach function
*
* Identify the card version and configure any children.
* Install a shutdown handler to kill interrupts on shutdown
*/
void
amps_attach(parent, self, aux)
struct device *parent, *self;
void *aux;
{
struct amps_softc *sc = (void *)self;
struct podule_attach_args *pa = (void *)aux;
struct amps_attach_args aa;
/* Note the podule number and validate */
if (pa->pa_podule_number == -1)
panic("Podule has disappeared !");
sc->sc_podule_number = pa->pa_podule_number;
sc->sc_podule = pa->pa_podule;
podules[sc->sc_podule_number].attached = 1;
sc->sc_iot = pa->pa_iot;
/* Install a clean up handler to make sure IRQ's are disabled */
/* if (shutdownhook_establish(amps_shutdown, (void *)sc) == NULL)
panic("%s: Cannot install shutdown handler", self->dv_xname);*/
/* Set the interrupt info for this podule */
/* sc->sc_podule->irq_addr = pa->pa_podule->slow_base +;*/ /* XXX */
/* sc->sc_podule->irq_mask = ;*/
printf("\n");
/* Configure the children */
aa.aa_iot = sc->sc_iot;
aa.aa_base = pa->pa_podule->slow_base + AMPS_BASE_OFFSET;
aa.aa_base += MAX_AMPS_PORTS * AMPS_PORT_SPACING;
aa.aa_irq = pa->pa_podule->interrupt;
for (aa.aa_port = 0; aa.aa_port < MAX_AMPS_PORTS; ++aa.aa_port) {
aa.aa_base -= AMPS_PORT_SPACING;
config_found_sm(self, &aa, amps_print, NULL);
}
}
/*
* Card shutdown function
*
* Called via do_shutdown_hooks() during kernel shutdown.
* Clear the cards's interrupt mask to stop any podule interrupts.
*/
/*void
amps_shutdown(arg)
void *arg;
{
}*/
/*
* Atomwide Multi-Port Serial probe and attach code for the com device.
*
* This provides a different pair of probe and attach functions
* for attaching the com device (dev/ic/com.c) to the Atomwide serial card.
*/
struct com_amps_softc {
struct com_softc sc_com; /* real "com" softc */
void *sc_ih; /* interrupt handler */
struct evcnt sc_intrcnt; /* interrupt count */
};
/* Prototypes for functions */
static int com_amps_probe __P((struct device *, struct cfdata *, void *));
static void com_amps_attach __P((struct device *, struct device *, void *));
/* device attach structure */
struct cfattach com_amps_ca = {
sizeof(struct com_amps_softc), com_amps_probe, com_amps_attach
};
/*
* Controller probe function
*
* Map all the required I/O space for this channel, make sure interrupts
* are disabled and probe the bus.
*/
int
com_amps_probe(parent, cf, aux)
struct device *parent;
struct cfdata *cf;
void *aux;
{
bus_space_tag_t iot;
bus_space_handle_t ioh;
int iobase;
int rv = 1;
struct amps_attach_args *aa = aux;
iot = aa->aa_iot;
iobase = aa->aa_base;
/* if it's in use as console, it's there. */
if (!com_is_console(iot, iobase, 0)) {
if (bus_space_map(iot, iobase, COM_NPORTS, 0, &ioh)) {
return 0;
}
/*
* We don't use the generic comprobe1() function as it
* is not good enough to identify which ports are present.
*
* Instead test for the presence of the scratch register
*/
bus_space_write_1(iot, ioh, com_scratch, 0x55);
bus_space_write_1(iot, ioh, com_ier, 0);
(void)bus_space_read_1(iot, ioh, com_data);
if (bus_space_read_1(iot, ioh, com_scratch) != 0x55)
rv = 0;
bus_space_write_1(iot, ioh, com_scratch, 0xaa);
bus_space_write_1(iot, ioh, com_ier, 0);
(void)bus_space_read_1(iot, ioh, com_data);
if (bus_space_read_1(iot, ioh, com_scratch) != 0xaa)
rv = 0;
bus_space_unmap(iot, ioh, COM_NPORTS);
}
return (rv);
}
/*
* Controller attach function
*
* Map all the required I/O space for this port and attach the driver
* The generic attach will probe and attach any device.
* Install an interrupt handler and we are ready to rock.
*/
void
com_amps_attach(parent, self, aux)
struct device *parent, *self;
void *aux;
{
struct com_amps_softc *asc = (void *)self;
struct com_softc *sc = &asc->sc_com;
u_int iobase;
bus_space_tag_t iot;
struct amps_attach_args *aa = aux;
iot = sc->sc_iot = aa->aa_iot;
iobase = sc->sc_iobase = aa->aa_base;
if (!com_is_console(iot, iobase, &sc->sc_ioh)
&& bus_space_map(iot, iobase, COM_NPORTS, 0, &sc->sc_ioh))
panic("comattach: io mapping failed");
sc->sc_frequency = AMPS_FREQ;
com_attach_subr(sc);
evcnt_attach_dynamic(&asc->sc_intrcnt, EVCNT_TYPE_INTR, NULL,
self->dv_xname, "intr");
asc->sc_ih = podulebus_irq_establish(aa->aa_irq, IPL_SERIAL, comintr,
sc, &asc->sc_intrcnt);
}

53
sys/arch/arm32/podulebus/ampsreg.h
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@ -1,53 +0,0 @@
/* $NetBSD: ampsreg.h,v 1.1 1997/11/06 02:08:54 mark Exp $ */
/*-
* Copyright (c) 1997 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Mark Brinicombe of Causality Limited.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Thanks to Martin Coulson, Atomwide, for providing the hardware
*/
/*
* Registers and address offsets for the Atomwide multiport serial card
*/
#define AMPS_FREQ 7372800
#define AMPS_BASE_OFFSET 0x2000
#define AMPS_PORT_SPACING 0x400
#define MAX_AMPS_PORTS 3
#define AMPS_STATUS 0x1c00 /* XXX */

387
sys/arch/arm32/podulebus/asc.c
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@ -1,387 +0,0 @@
/* $NetBSD: asc.c,v 1.36 2001/08/15 22:28:15 rearnsha Exp $ */
/*
* Copyright (c) 2001 Richard Earnshaw
* All rights reserved.
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* POSSIBILITY OF SUCH DAMAGE.
*
*
* Copyright (c) 1996 Mark Brinicombe
* Copyright (c) 1982, 1990 The Regents of the University of California.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* from:ahsc.c
*/
/*
* Driver for the Acorn SCSI card using the SBIC (WD33C93A) generic driver
*
* Thanks to Acorn for supplying programming information on this card.
*/
/* #define ASC_DMAMAP_DEBUG */
/* #define DEBUG */
#include "opt_ddb.h"
#include <sys/types.h>
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/device.h>
#include <sys/buf.h>
#include <uvm/uvm_extern.h>
#include <machine/bus.h>
#include <machine/irqhandler.h>
#include <machine/bootconfig.h> /* asc_poll */
#include <dev/scsipi/scsi_all.h>
#include <dev/scsipi/scsipi_all.h>
#include <dev/scsipi/scsiconf.h>
#include <machine/katelib.h>
#include <dev/podulebus/podules.h>
#include <dev/podulebus/powerromreg.h>
#include <arm32/podulebus/podulebus.h>
#include <arm32/podulebus/sbicreg.h>
#include <arm32/podulebus/sbicvar.h>
#include <arm32/podulebus/ascreg.h>
#include <arm32/podulebus/ascvar.h>
void ascattach (struct device *, struct device *, void *);
int ascmatch (struct device *, struct cfdata *, void *);
void asc_enintr (struct sbic_softc *);
int asc_dmaok (void *, bus_dma_tag_t, struct sbic_acb *);
int asc_dmasetup (void *, bus_dma_tag_t, struct sbic_acb *, int);
int asc_dmanext (void *, bus_dma_tag_t, struct sbic_acb *, int);
void asc_dmastop (void *, bus_dma_tag_t, struct sbic_acb *);
void asc_dmafinish (void *, bus_dma_tag_t, struct sbic_acb *);
void asc_scsi_request (struct scsipi_channel *,
scsipi_adapter_req_t, void *);
int asc_intr (void *);
void asc_minphys (struct buf *);
#ifdef DEBUG
int asc_dmadebug = 0;
#endif
struct cfattach asc_ca = {
sizeof(struct asc_softc), ascmatch, ascattach
};
extern struct cfdriver asc_cd;
u_long scsi_nosync;
int shift_nosync;
#if ASC_POLL > 0
int asc_poll = 0;
#endif
int
ascmatch(struct device *pdp, struct cfdata *cf, void *auxp)
{
struct podule_attach_args *pa = (struct podule_attach_args *)auxp;
/* Look for the card */
/* Standard ROM, skipping the MCS card that used the same ID. */
if (matchpodule(pa, MANUFACTURER_ACORN, PODULE_ACORN_SCSI, -1) &&
strncmp(pa->pa_podule->description, "MCS", 3) != 0)
return 1;
/* PowerROM */
if (pa->pa_product == PODULE_ALSYSTEMS_SCSI &&
podulebus_initloader(pa) == 0 &&
podloader_callloader(pa, 0, 0) == PRID_ACORN_SCSI1)
return 1;
return 0;
}
void
ascattach(struct device *pdp, struct device *dp, void *auxp)
{
/* volatile struct sdmac *rp;*/
struct asc_softc *sc;
struct sbic_softc *sbic;
struct podule_attach_args *pa;
sc = (struct asc_softc *)dp;
pa = (struct podule_attach_args *)auxp;
if (pa->pa_podule_number == -1)
panic("Podule has disappeared !");
sc->sc_podule_number = pa->pa_podule_number;
sc->sc_podule = pa->pa_podule;
podules[sc->sc_podule_number].attached = 1;
sbic = &sc->sc_softc;
sbic->sc_enintr = asc_enintr;
sbic->sc_dmaok = asc_dmaok;
sbic->sc_dmasetup = asc_dmasetup;
sbic->sc_dmanext = asc_dmanext;
sbic->sc_dmastop = asc_dmastop;
sbic->sc_dmafinish = asc_dmafinish;
/* Map sbic */
sbic->sc_sbicp.sc_sbiciot = pa->pa_iot;
if (bus_space_map (sbic->sc_sbicp.sc_sbiciot,
sc->sc_podule->mod_base + ASC_SBIC, ASC_SBIC_SPACE, 0,
&sbic->sc_sbicp.sc_sbicioh))
panic("%s: Cannot map SBIC\n", dp->dv_xname);
sbic->sc_clkfreq = sbic_clock_override ? sbic_clock_override : 143;
sbic->sc_adapter.adapt_dev = &sbic->sc_dev;
sbic->sc_adapter.adapt_nchannels = 1;
sbic->sc_adapter.adapt_openings = 7;
sbic->sc_adapter.adapt_max_periph = 1;
sbic->sc_adapter.adapt_ioctl = NULL;
sbic->sc_adapter.adapt_minphys = asc_minphys;
sbic->sc_adapter.adapt_request = asc_scsi_request;
sbic->sc_channel.chan_adapter = &sbic->sc_adapter;
sbic->sc_channel.chan_bustype = &scsi_bustype;
sbic->sc_channel.chan_channel = 0;
sbic->sc_channel.chan_ntargets = 8;
sbic->sc_channel.chan_nluns = 8;
sbic->sc_channel.chan_id = 7;
/* Provide an override for the host id */
(void)get_bootconf_option(boot_args, "asc.hostid",
BOOTOPT_TYPE_INT, &sbic->sc_channel.chan_id);
printf(": hostid=%d", sbic->sc_channel.chan_id);
#if ASC_POLL > 0
if (boot_args)
get_bootconf_option(boot_args, "ascpoll", BOOTOPT_TYPE_BOOLEAN,
&asc_poll);
if (asc_poll)
printf(" polling");
#endif
printf("\n");
sc->sc_pagereg = sc->sc_podule->fast_base + ASC_PAGEREG;
sc->sc_intstat = sc->sc_podule->fast_base + ASC_INTSTATUS;
/* Reset the card */
WriteByte(sc->sc_pagereg, 0x80);
DELAY(500000);
WriteByte(sc->sc_pagereg, 0x00);
DELAY(250000);
sbicinit(sbic);
/* If we are polling only, we don't need a interrupt handler. */
#ifdef ASC_POLL
if (!asc_poll)
#endif
{
evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL,
dp->dv_xname, "intr");
sc->sc_ih = podulebus_irq_establish(pa->pa_ih, IPL_BIO,
asc_intr, sc, &sc->sc_intrcnt);
if (sc->sc_ih == NULL)
panic("%s: Cannot claim podule IRQ\n", dp->dv_xname);
}
/*
* attach all scsi units on us
*/
config_found(dp, &sbic->sc_channel, scsiprint);
}
void
asc_enintr(struct sbic_softc *sbicsc)
{
struct asc_softc *sc = (struct asc_softc *)sbicsc;
sbicsc->sc_flags |= SBICF_INTR;
WriteByte(sc->sc_pagereg, 0x40);
}
int
asc_dmaok (void *dma_h, bus_dma_tag_t dma_t, struct sbic_acb *acb)
{
return 0;
}
int
asc_dmasetup (void *dma_h, bus_dma_tag_t dma_t, struct sbic_acb *acb, int dir)
{
printf("asc_dmasetup()");
#ifdef DDB
Debugger();
#else
panic("Hit a brick wall\n");
#endif
return 0;
}
int
asc_dmanext (void *dma_h, bus_dma_tag_t dma_t, struct sbic_acb *acb, int dir)
{
printf("asc_dmanext()");
#ifdef DDB
Debugger();
#else
panic("Hit a brick wall\n");
#endif
return 0;
}
void
asc_dmastop (void *dma_h, bus_dma_tag_t dma_t, struct sbic_acb *acb)
{
printf("asc_dmastop\n");
}
void
asc_dmafinish (void *dma_h, bus_dma_tag_t dma_t, struct sbic_acb *acb)
{
printf("asc_dmafinish\n");
}
int
asc_dmaintr(dev)
struct sbic_softc *dev;
{
panic("asc_dmaintr");
return 0;
}
void
asc_dump(void)
{
int i;
for (i = 0; i < asc_cd.cd_ndevs; ++i)
if (asc_cd.cd_devs[i])
sbic_dump(asc_cd.cd_devs[i]);
}
void
asc_scsi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req,
void *arg)
{
struct scsipi_xfer *xs;
switch (req) {
case ADAPTER_REQ_RUN_XFER:
xs = arg;
#if ASC_POLL > 0
/* ensure command is polling for the moment */
if (asc_poll)
xs->xs_control |= XS_CTL_POLL;
#endif
/* printf("id=%d lun=%dcmdlen=%d datalen=%d opcode=%02x flags=%08x status=%02x blk=%02x %02x\n",
xs->xs_periph->periph_target, xs->xs_periph->periph_lun, xs->cmdlen, xs->datalen, xs->cmd->opcode,
xs->xs_control, xs->status, xs->cmd->bytes[0], xs->cmd->bytes[1]);*/
default:
}
sbic_scsi_request(chan, req, arg);
}
int
asc_intr(void *arg)
{
struct asc_softc *sc = arg;
int intr;
/* printf("ascintr:");*/
intr = ReadByte(sc->sc_intstat);
/* printf("%02x\n", intr);*/
if (intr & IS_SBIC_IRQ)
sbicintr((struct sbic_softc *)sc);
return 0; /* Pass interrupt on down the chain */
}
/*
* limit the transfer as required.
*/
void
asc_minphys(struct buf *bp)
{
#if 0
/*
* We must limit the DMA xfer size
*/
if (bp->b_bcount > MAX_DMA_LEN) {
printf("asc: Reducing dma length\n");
bp->b_bcount = MAX_DMA_LEN;
}
#endif
minphys(bp);
}

281
sys/arch/arm32/podulebus/ascreg.h
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@ -1,281 +0,0 @@
/* $NetBSD: ascreg.h,v 1.6 2001/04/21 20:47:26 rearnsha Exp $ */
/*
* Copyright (c) 1996 Mark Brinicombe
* Copyright (c) 1994 Christian E. Hopps
* Copyright (c) 1982, 1990 The Regents of the University of California.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* from:ahscreg.h,v 1.2 1994/10/26 02:02:46
*/
#ifndef _ASCREG_H_
#define _ASCREG_H_
/*
* Hardware layout of the A3000 SDMAC. This also contains the
* registers for the sbic chip, but in favor of separating DMA and
* scsi, the scsi-driver doesn't make use of this dependency
*/
#define v_char volatile char
#define v_int volatile int
#define vu_char volatile u_char
#define vu_short volatile u_short
#define vu_int volatile u_int
struct sdmac {
short pad0;
vu_short DAWR; /* DACK Width Register WO */
vu_int WTC; /* Word Transfer Count Register RW */
short pad1;
vu_short CNTR; /* Control Register RW */
vu_int ACR; /* Address Count Register RW */
short pad2;
vu_short ST_DMA; /* Start DMA Transfers RW-Strobe */
short pad3;
vu_short FLUSH; /* Flush FIFO RW-Strobe */
short pad4;
vu_short CINT; /* Clear Interrupts RW-Strobe */
short pad5;
vu_short ISTR; /* Interrupt Status Register RO */
int pad6[7];
short pad7;
vu_short SP_DMA; /* Stop DMA Transfers RW-Strobe */
char pad8;
vu_char SASR; /* sbic asr */
char pad9;
vu_char SCMD; /* sbic data */
};
/*
* value to go into DAWR
*/
#define DAWR_AHSC 3 /* according to A3000T service-manual */
/*
* bits defined for CNTR
*/
#define CNTR_TCEN (1<<5) /* Terminal Count Enable */
#define CNTR_PREST (1<<4) /* Perp Reset (not implemented :-((( ) */
#define CNTR_PDMD (1<<3) /* Perp Device Mode Select (1=SCSI,0=XT/AT) */
#define CNTR_INTEN (1<<2) /* Interrupt Enable */
#define CNTR_DDIR (1<<1) /* Device Direction. 1==rd host, wr perp */
#define CNTR_IO_DX (1<<0) /* IORDY & CSX1 Polarity Select */
/*
* bits defined for ISTR
*/
#define ISTR_INTX (1<<8) /* XT/AT Interrupt pending */
#define ISTR_INT_F (1<<7) /* Interrupt Follow */
#define ISTR_INTS (1<<6) /* SCSI Peripheral Interrupt */
#define ISTR_E_INT (1<<5) /* End-Of-Process Interrupt */
#define ISTR_INT_P (1<<4) /* Interrupt Pending */
#define ISTR_UE_INT (1<<3) /* Under-Run FIFO Error Interrupt */
#define ISTR_OE_INT (1<<2) /* Over-Run FIFO Error Interrupt */
#define ISTR_FF_FLG (1<<1) /* FIFO-Full Flag */
#define ISTR_FE_FLG (1<<0) /* FIFO-Empty Flag */
#define DMAGO_READ 0x01
/* Addresses relative to podule base */
#define ASC_INTSTATUS 0x2000
#define ASC_CLRINT 0x2000
#define ASC_PAGEREG 0x3000
/* Addresses relative to module base */
#define ASC_DMAC 0x3000
#define ASC_SBIC 0x2000
#define ASC_SRAM 0x0000
#define ASC_SBIC_SPACE 8
#define ASC_SRAM_BLKSIZE 0x1000
#define IS_IRQREQ 0x01
#define IS_DMAC_IRQ 0x02
#define IS_SBIC_IRQ 0x08
#if 0
/* SBIC Commands */
#define SBIC_CMD_Reset 0x00 /* Reset the SBIC */
#define SBIC_Abort 0x01 /* Abort command */
#define SBIC_Sel_tx_wATN 0x08 /* Select and Transfer with ATN */
#define SBIC_Sel_tx_woATN 0x09 /* Select and Transfer without ATN */
/* SBIC status codes */
#define SBIC_ResetOk 0x00
#define SBIC_ResetAFOk 0x01
/* SBIC registers bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 */
#define SBIC_OWNID 0x00 /* RW FS1 FS0 0 EHP EAF ID2 ID1 ID0 */
#define SBIC_CONTROL 0x01 /* RW DM2 DM1 DM0 HHP EDI IDI HA HSP */
#define SBIC_TIMEREG 0x02 /* RW timeout period value = Tper*Ficlk/80d */
#define SBIC_CDB1TSECT 0x03 /* RW CDB byte 1 & Total sectors per track */
#define SBIC_CDB2THEAD 0x04 /* RW CDB byte 2 & Total number of heads */
#define SBIC_CDB3TCYL1 0x05 /* RW CDB byte 3 & Total no. of cylinders MSB */
#define SBIC_CDB4TCYL2 0x06 /* RW CDB byte 4 & Total no. of cylinders LSB */
#define SBIC_CDB5LADR1 0x07 /* RW CDB byte 5 & Logical addr to translate */
#define SBIC_CBD6LADR2 0x08 /* RW CDB byte 6 & Logical addr to translate */
#define SBIC_CDB7LADR3 0x09 /* RW CDB byte 7 & Logical addr to translate */
#define SBIC_CDB8LADR4 0x0A /* RW CDB byte 8 & Logical addr to translate */
#define SBIC_CDB9SECT 0x0B /* RW CDB byte 9 & Translation sector result */
#define SBIC_CDB10HEAD 0x0C /* RW CDB byte 10 & Translation head result */
#define SBIC_CDB11CYL1 0x0D /* RW CDB byte 11 & Translation cyl result MSB*/
#define SBIC_CDB12CYL2 0x0E /* RW CDB byte 12 & Translation cyl result LSB*/
#define SBIC_TARGETLUN 0x0F /* RW TLV DOK 0 0 0 TL2 TL1 TL0 */
#define SBIC_COMPHASE 0x10 /* RW Command Phase Register for multi-phase */
#define SBIC_SYNCTX 0x11 /* RW 0 TP2 TP1 TP0 OF3 OF2 OF1 OF0 */
#define SBIC_TXCOUNT1 0x12 /* RW Transfer count MSB */
#define SBIC_TXCOUNT2 0x13 /* RW Transfer count */
#define SBIC_TXCOUNT3 0x14 /* RW Transfer count LSB */
#define SBIC_DESTID 0x15 /* RW SCC DPD 0 0 0 DI2 DI1 DI0 */
#define SBIC_SOURCEID 0x16 /* RW ER ES DSP 0 SIV SI2 SI1 SI0 */
#define SBIC_SCSISTAT 0x17 /* RO **Interrupt type*** **Int. qualifier** */
#define SBIC_COMMAND 0x18 /* RW SBT *********Command code************* */
#define SBIC_DATA 0x19 /* RW Access to data i/o FIFO for polled use */
#define SBIC_ADDRREG 0x00
#define SBIC_DATAREG 0x04
#define SBIC_AUX_STATUS 0x00
/*
* My ID register, and/or CDB Size
*/
#define SBIC_ID_FS_8_10 0x00 /* Input clock is 8-10 Mhz */
/* 11 Mhz is invalid */
#define SBIC_ID_FS_12_15 0x40 /* Input clock is 12-15 Mhz */
#define SBIC_ID_FS_16_20 0x80 /* Input clock is 16-20 Mhz */
#define SBIC_ID_EHP 0x10 /* Enable host parity */
#define SBIC_ID_EAF 0x08 /* Enable Advanced Features */
#define SBIC_ID_MASK 0x07
#define SBIC_ID_CBDSIZE_MASK 0x0f /* if unk SCSI cmd group */
/*
* Control register
*/
#define SBIC_CTL_DMA 0x80 /* Single byte dma */
#define SBIC_CTL_DBA_DMA 0x40 /* direct buffer acces (bus master)*/
#define SBIC_CTL_BURST_DMA 0x20 /* continuous mode (8237) */
#define SBIC_CTL_NO_DMA 0x00 /* Programmed I/O */
#define SBIC_CTL_HHP 0x10 /* Halt on host parity error */
#define SBIC_CTL_EDI 0x08 /* Ending disconnect interrupt */
#define SBIC_CTL_IDI 0x04 /* Intermediate disconnect interrupt*/
#define SBIC_CTL_HA 0x02 /* Halt on ATN */
#define SBIC_CTL_HSP 0x01 /* Halt on SCSI parity error */
/*
* Destination ID register
*/
#define SBIC_DID_DPD 0x40 /* Data Phase Direction */
/*
* Auxiliary Status Register
*/
#define SBIC_ASR_INT 0x80 /* Interrupt pending */
#define SBIC_ASR_LCI 0x40 /* Last command ignored */
#define SBIC_ASR_BSY 0x20 /* Busy, only cmd/data/asr readable */
#define SBIC_ASR_CIP 0x10 /* Busy, cmd unavail also */
#define SBIC_ASR_xxx 0x0c
#define SBIC_ASR_PE 0x02 /* Parity error (even) */
#define SBIC_ASR_DBR 0x01 /* Data Buffer Ready */
/* DMAC constants */
#define DMAC_Bits 0x01
#define DMAC_Ctrl1 0x60
#define DMAC_Ctrl2 0x01
#define DMAC_CLEAR_MASK 0x0E
#define DMAC_SET_MASK 0x0F
#define DMAC_DMA_RD_MODE 0x04
#define DMAC_DMA_WR_MODE 0x08
/* DMAC registers */
#define DMAC_INITIALISE 0x0000 /* WO ---- ---- ---- ---- ---- ---- 16B RES */
#define DMAC_CHANNEL 0x0200 /* R ---- ---- ---- BASE SEL3 SEL2 SEL1 SEL0 */
/* W ---- ---- ---- ---- ---- BASE *SELECT** */
#define DMAC_TXCNTLO 0x0004 /* RW C7 C6 C5 C4 C3 C2 C1 C0 */
#define DMAC_TXCNTHI 0x0204 /* RW C15 C14 C13 C12 C11 C10 C9 C8 */
#define DMAC_TXADRLO 0x0008 /* RW A7 A6 A5 A4 A3 A2 A1 A0 */
#define DMAC_TXADRMD 0x0208 /* RW A15 A14 A13 A12 A11 A10 A9 A8 */
#define DMAC_TXADRHI 0x000C /* RW A23 A22 A21 A20 A19 A18 A17 A16 */
#define DMAC_DEVCON1 0x0010 /* RW AKL RQL EXW ROT CMP DDMA AHLD MTM */
#define DMAC_DEVCON2 0x0210 /* RW ---- ---- ---- ---- ---- ---- WEV BHLD */
#define DMAC_MODECON 0x0014 /* RW **TMODE** ADIR AUTI **TDIR*** ---- WORD */
#define DMAC_STATUS 0x0214 /* RO RQ3 RQ2 RQ1 RQ0 TC3 TC2 TC1 TC0 */
#if 0
templo = dmac + 0x0018;/* RO T7 T6 T5 T4 T3 T2 T1 T0 */
temphi = dmac + 0x0218;/* RO T15 T14 T13 T12 T11 T10 T9 T8 */
#endif
#define DMAC_REQREG 0x001C /* RW ---- ---- ---- ---- SRQ3 SRQ2 SRQ1 SRQ0 */
#define DMAC_MASKREG 0x021C /* RW ---- ---- ---- ---- M3 M2 M1 M0 */
#ifndef _LOCORE
#define WriteSBIC(a, d) \
WriteByte(sbic_base + SBIC_ADDRREG, a); \
WriteByte(sbic_base + SBIC_DATAREG, d);
/*
#define ReadSBIC(a) \
(WriteByte(sbic_base, a), ReadWord(sbic_base + 4) & 0xff)
*/
#define ReadSBIC(a) \
ReadSBIC1(sbic_base, a)
static __inline int
ReadSBIC1(sbic_base, a)
u_int sbic_base;
int a;
{
WriteByte(sbic_base + SBIC_ADDRREG, a);
return(ReadByte(sbic_base + SBIC_DATAREG));
}
#define WriteDMAC(a, d) WriteByte(dmac_base + a, d)
#define ReadDMAC(a) ReadByte(dmac_base + a)
#endif
#endif
#endif /* _ASCREG_H_ */

53
sys/arch/arm32/podulebus/ascvar.h
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@ -1,53 +0,0 @@
/* $NetBSD: ascvar.h,v 1.2 2001/03/18 01:31:03 bjh21 Exp $ */
/*
* Copyright (c) 1996 Mark Brinicombe
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Mark Brinicombe
* for the NetBSD Project.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ASCVAR_H_
#define _ASCVAR_H_
#include <arm32/podulebus/sbicvar.h>
#include <arm32/podulebus/ascreg.h>
#define ASC_POLL 1
struct asc_softc {
struct sbic_softc sc_softc;
podule_t *sc_podule;
int sc_podule_number;
void *sc_ih;
struct evcnt sc_intrcnt;
vu_int sc_pagereg;
vu_int sc_intstat;
};
#endif /* _ASCVAR_H_ */

463
sys/arch/arm32/podulebus/cosc.c
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@ -1,463 +0,0 @@
/* $NetBSD: cosc.c,v 1.17 2001/05/13 13:53:08 bjh21 Exp $ */
/*
* Copyright (c) 1996 Mark Brinicombe
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Mark Brinicombe
* for the NetBSD Project.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* from: asc.c,v 1.8 1996/06/12 20:46:58 mark Exp
*/
/*
* Driver for the MCS Connect 32 SCSI 2 card with AM53C94 SCSI controller.
*
* Thanks to Mike <mcsmike@knipp.de> at MCS for loaning a card.
* Thanks to Andreas Gandor <andi@knipp.de> for some technical information
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/device.h>
#include <dev/scsipi/scsi_all.h>
#include <dev/scsipi/scsipi_all.h>
#include <dev/scsipi/scsiconf.h>
#include <machine/bootconfig.h>
#include <machine/io.h>
#include <machine/irqhandler.h>
#include <machine/katelib.h>
#include <arm32/podulebus/podulebus.h>
#include <arm32/podulebus/escreg.h>
#include <arm32/podulebus/escvar.h>
#include <arm32/podulebus/coscreg.h>
#include <arm32/podulebus/coscvar.h>
#include <dev/podulebus/podules.h>
void coscattach __P((struct device *, struct device *, void *));
int coscmatch __P((struct device *, struct cfdata *, void *));
void cosc_scsi_request __P((struct scsipi_channel *,
scsipi_adapter_req_t, void *));
struct cfattach cosc_ca = {
sizeof(struct cosc_softc), coscmatch, coscattach
};
int cosc_intr __P((void *arg));
int cosc_setup_dma __P((struct esc_softc *sc, void *ptr, int len,
int mode));
int cosc_build_dma_chain __P((struct esc_softc *sc,
struct esc_dma_chain *chain, void *p, int l));
int cosc_need_bump __P((struct esc_softc *sc, void *ptr, int len));
void cosc_led __P((struct esc_softc *sc, int mode));
#if COSC_POLL > 0
int cosc_poll = 1;
#endif
int
coscmatch(pdp, cf, auxp)
struct device *pdp;
struct cfdata *cf;
void *auxp;
{
struct podule_attach_args *pa = (struct podule_attach_args *)auxp;
/* Look for the card */
if (matchpodule(pa, MANUFACTURER_MCS, PODULE_MCS_SCSI, -1) != 0)
return(1);
/* Old versions of the ROM on this card could have the wrong ID */
if (matchpodule(pa, MANUFACTURER_ACORN, PODULE_ACORN_SCSI, -1) == 0)
return(0);
if (strncmp(pa->pa_podule->description, "MCS", 3) != 0)
return(0);
return(1);
}
static int dummy[6];
void
coscattach(pdp, dp, auxp)
struct device *pdp, *dp;
void *auxp;
{
struct cosc_softc *sc = (struct cosc_softc *)dp;
struct podule_attach_args *pa;
cosc_regmap_p rp = &sc->sc_regmap;
vu_char *esc;
pa = (struct podule_attach_args *)auxp;
if (pa->pa_podule_number == -1)
panic("Podule has disappeared !");
sc->sc_podule_number = pa->pa_podule_number;
sc->sc_podule = pa->pa_podule;
podules[sc->sc_podule_number].attached = 1;
printf(":");
if (pa->pa_podule->manufacturer == MANUFACTURER_ACORN
&& pa->pa_podule->product == PODULE_ACORN_SCSI)
printf(" Faulty expansion card identity\n");
sc->sc_iobase = (vu_char *)sc->sc_podule->fast_base;
/* Select page zero (so we can see the config info) */
sc->sc_iobase[COSC_PAGE_REGISTER] = 0;
rp->chipreset = (vu_char *)&dummy[0];
rp->inten = (vu_char *)&dummy[1];
rp->status = (vu_char *)&dummy[2];
rp->term = &sc->sc_iobase[COSC_TERMINATION_CONTROL];
rp->led = (vu_char *)&dummy[4];
esc = &sc->sc_iobase[COSC_ESCOFFSET_BASE];
rp->esc.esc_tc_low = &esc[COSC_ESCOFFSET_TCL];
rp->esc.esc_tc_mid = &esc[COSC_ESCOFFSET_TCM];
rp->esc.esc_fifo = &esc[COSC_ESCOFFSET_FIFO];
rp->esc.esc_command = &esc[COSC_ESCOFFSET_COMMAND];
rp->esc.esc_dest_id = &esc[COSC_ESCOFFSET_DESTID];
rp->esc.esc_timeout = &esc[COSC_ESCOFFSET_TIMEOUT];
rp->esc.esc_syncper = &esc[COSC_ESCOFFSET_PERIOD];
rp->esc.esc_syncoff = &esc[COSC_ESCOFFSET_OFFSET];
rp->esc.esc_config1 = &esc[COSC_ESCOFFSET_CONFIG1];
rp->esc.esc_clkconv = &esc[COSC_ESCOFFSET_CLOCKCONV];
rp->esc.esc_test = &esc[COSC_ESCOFFSET_TEST];
rp->esc.esc_config2 = &esc[COSC_ESCOFFSET_CONFIG2];
rp->esc.esc_config3 = &esc[COSC_ESCOFFSET_CONFIG3];
rp->esc.esc_config4 = &esc[COSC_ESCOFFSET_CONFIG4];
rp->esc.esc_tc_high = &esc[COSC_ESCOFFSET_TCH];
rp->esc.esc_fifo_bot = &esc[COSC_ESCOFFSET_FIFOBOTTOM];
*rp->esc.esc_command = ESC_CMD_RESET_CHIP;
delay(1000);
*rp->esc.esc_command = ESC_CMD_NOP;
/* See if we recognise the controller */
switch (*rp->esc.esc_tc_high) {
case 0x12:
printf(" AM53CF94");
break;
default:
printf(" Unknown controller (%02x)", *rp->esc.esc_tc_high);
break;
}
/* Set termination power */
if (sc->sc_iobase[COSC_CONFIG_TERMINATION] & COSC_CONFIG_TERMINATION_ON) {
printf(" termpwr on");
sc->sc_iobase[COSC_TERMINATION_CONTROL] = COSC_TERMINATION_ON;
} else {
printf(" termpwr off");
sc->sc_iobase[COSC_TERMINATION_CONTROL] = COSC_TERMINATION_OFF;
}
/* Don't know what this is for */
{
int byte;
int loop;
byte = sc->sc_iobase[COSC_REGISTER_01];
byte = 0;
for (loop = 0; loop < 8; ++loop) {
if (sc->sc_iobase[COSC_REGISTER_00] & 0x01)
byte |= (1 << loop);
}
printf(" byte=%02x", byte);
}
/*
* Control register 4 is an AMD special (not on FAS216)
*
* The powerdown and glitch eater facilities could be useful
* Use the podule configuration for this register
*/
sc->sc_softc.sc_config4 = sc->sc_iobase[COSC_CONFIG_CONTROL_REG4];
sc->sc_softc.sc_esc = (esc_regmap_p)rp;
/* sc->sc_softc.sc_spec = &sc->sc_specific;*/
sc->sc_softc.sc_led = cosc_led;
sc->sc_softc.sc_setup_dma = cosc_setup_dma;
sc->sc_softc.sc_build_dma_chain = cosc_build_dma_chain;
sc->sc_softc.sc_need_bump = cosc_need_bump;
sc->sc_softc.sc_clock_freq = 40; /* Connect32 runs at 40MHz */
sc->sc_softc.sc_timeout = 250; /* Set default timeout to 250ms */
sc->sc_softc.sc_config_flags = ESC_NO_DMA;
sc->sc_softc.sc_host_id = sc->sc_iobase[COSC_CONFIG_CONTROL_REG1] & ESC_DEST_ID_MASK;
printf(" hostid=%d", sc->sc_softc.sc_host_id);
#if COSC_POLL > 0
if (boot_args)
get_bootconf_option(boot_args, "coscpoll",
BOOTOPT_TYPE_BOOLEAN, &cosc_poll);
if (cosc_poll)
printf(" polling");
#endif
sc->sc_softc.sc_bump_sz = NBPG;
sc->sc_softc.sc_bump_pa = 0x0;
escinitialize((struct esc_softc *)sc);
sc->sc_softc.sc_adapter.adapt_dev = &sc->sc_softc.sc_dev;
sc->sc_softc.sc_adapter.adapt_nchannels = 1;
sc->sc_softc.sc_adapter.adapt_openings = 7;
sc->sc_softc.sc_adapter.adapt_max_periph = 1;
sc->sc_softc.sc_adapter.adapt_ioctl = NULL;
sc->sc_softc.sc_adapter.adapt_minphys = esc_minphys;
sc->sc_softc.sc_adapter.adapt_request = cosc_scsi_request;
sc->sc_softc.sc_channel.chan_adapter = &sc->sc_softc.sc_adapter;
sc->sc_softc.sc_channel.chan_bustype = &scsi_bustype;
sc->sc_softc.sc_channel.chan_channel = 0;
sc->sc_softc.sc_channel.chan_ntargets = 8;
sc->sc_softc.sc_channel.chan_nluns = 8;
sc->sc_softc.sc_channel.chan_id = sc->sc_softc.sc_host_id;
/* initialise the card */
#if 0
*rp->inten = (COSC_POLL?0:1);
*rp->led = 0;
#endif
sc->sc_softc.sc_ih.ih_func = cosc_intr;
sc->sc_softc.sc_ih.ih_arg = &sc->sc_softc;
sc->sc_softc.sc_ih.ih_level = IPL_BIO;
sc->sc_softc.sc_ih.ih_name = "scsi: cosc";
sc->sc_softc.sc_ih.ih_maskaddr = sc->sc_podule->irq_addr;
sc->sc_softc.sc_ih.ih_maskbits = sc->sc_podule->irq_mask;
#if COSC_POLL > 0
if (!cosc_poll)
#endif
{
evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL,
dp->dv_xname, "intr");
sc->sc_ih = podulebus_irq_establish(pa->pa_ih, IPL_BIO,
cosc_intr, sc, &sc->sc_intrcnt);
if (sc->sc_ih == NULL)
panic("%s: Cannot install IRQ handler\n",
dp->dv_xname);
}
printf("\n");
/* attach all scsi units on us */
config_found(dp, &sc->sc_softc.sc_channel, scsiprint);
}
/* Turn on/off led */
void
cosc_led(sc, mode)
struct esc_softc *sc;
int mode;
{
cosc_regmap_p rp;
rp = (cosc_regmap_p)sc->sc_esc;
if (mode) {
sc->sc_led_status++;
} else {
if (sc->sc_led_status)
sc->sc_led_status--;
}
/* *rp->led = (sc->sc_led_status?1:0);*/
}
int
cosc_intr(arg)
void *arg;
{
struct esc_softc *dev = arg;
cosc_regmap_p rp;
int quickints;
rp = (cosc_regmap_p)dev->sc_esc;
printf("cosc_intr:%08x %02x\n", (u_int)rp->esc.esc_status, *rp->esc.esc_status);
if (*rp->esc.esc_status & ESC_STAT_INTERRUPT_PENDING) {
quickints = 16;
do {
dev->sc_status = *rp->esc.esc_status;
dev->sc_interrupt = *rp->esc.esc_interrupt;
if (dev->sc_interrupt & ESC_INT_RESELECTED) {
dev->sc_resel[0] = *rp->esc.esc_fifo;
dev->sc_resel[1] = *rp->esc.esc_fifo;
}
escintr(dev);
} while((*rp->esc.esc_status & ESC_STAT_INTERRUPT_PENDING)
&& --quickints);
}
return(0); /* Pass interrupt on down the chain */
}
/* Load transfer address into dma register */
void
cosc_set_dma_adr(sc, ptr)
struct esc_softc *sc;
void *ptr;
{
printf("cosc_set_dma_adr(sc = 0x%08x, ptr = 0x%08x)\n", (u_int)sc, (u_int)ptr);
return;
}
/* Set DMA transfer counter */
void
cosc_set_dma_tc(sc, len)
struct esc_softc *sc;
unsigned int len;
{
printf("cosc_set_dma_tc(sc, len = 0x%08x)", len);
/* Set the transfer size on the SCSI controller */
*sc->sc_esc->esc_tc_low = len; len >>= 8;
*sc->sc_esc->esc_tc_mid = len; len >>= 8;
*sc->sc_esc->esc_tc_high = len;
}
/* Set DMA mode */
void
cosc_set_dma_mode(sc, mode)
struct esc_softc *sc;
int mode;
{
printf("cosc_set_dma_mode(sc, mode = %d)", mode);
}
/* Initialize DMA for transfer */
int
cosc_setup_dma(sc, ptr, len, mode)
struct esc_softc *sc;
void *ptr;
int len;
int mode;
{
/* printf("cosc_setup_dma(sc, ptr = 0x%08x, len = 0x%08x, mode = 0x%08x)\n", (u_int)ptr, len, mode);*/
return(0);
}
/* Check if address and len is ok for DMA transfer */
int
cosc_need_bump(sc, ptr, len)
struct esc_softc *sc;
void *ptr;
int len;
{
int p;
p = (int)ptr & 0x03;
if (p) {
p = 4-p;
if (len < 256)
p = len;
}
return(p);
}
/* Interrupt driven routines */
int
cosc_build_dma_chain(sc, chain, p, l)
struct esc_softc *sc;
struct esc_dma_chain *chain;
void *p;
int l;
{
printf("cosc_build_dma_chain()\n");
return(0);
}
void
cosc_scsi_request(chan, req, arg)
struct scsipi_channel *chan;
scsipi_adapter_req_t req;
void *arg;
{
struct scsipi_xfer *xs;
switch (req) {
case ADAPTER_REQ_RUN_XFER:
xs = arg;
#if COSC_POLL > 0
if (cosc_poll)
xs->xs_control |= XS_CTL_POLL;
#endif
#if 0
if (periph->periph_lun == 0)
printf("id=%d lun=%d cmdlen=%d datalen=%d opcode=%02x flags=%08x status=%02x blk=%02x %02x\n",
xs->xs_periph->periph_target, xs->xs_periph->periph_lun, xs->cmdlen, xs->datalen, xs->cmd->opcode,
xs->xs_control, xs->status, xs->cmd->bytes[0], xs->cmd->bytes[1]);
#endif
default:
}
esc_scsi_request(chan, req, arg);
}

111
sys/arch/arm32/podulebus/coscreg.h
View File

@ -1,111 +0,0 @@
/* $NetBSD: coscreg.h,v 1.2 1997/01/03 23:24:48 mark Exp $ */
/*
* Copyright (c) 1996 Mark Brinicombe
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Mark Brinicombe
* for the NetBSD Project.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Termination and DMA enable registers provided by
* Andreas Gandor <andi@knipp.de>
*/
#ifndef _COSCREG_H_
#define _COSCREG_H_
#include <arm32/podulebus/escvar.h>
typedef volatile unsigned short vu_short;
typedef struct cosc_regmap {
esc_regmap_t esc;
vu_char *chipreset;
vu_char *inten;
vu_char *status;
vu_char *term;
vu_char *led;
} cosc_regmap_t;
typedef cosc_regmap_t *cosc_regmap_p;
/*
#define COSC_CONTROL_CHIPRESET
#define COSC_CONTROL_INTEN
#define COSC_STATUS
#define COSC_CONTROL_LED
*/
#define COSC_CONFIG_CONTROL_REG1 0x0ff0
#define COSC_CONFIG_CONTROL_REG1_MASK 0x97
#define COSC_CONFIG_CONTROL_REG2 0x0ff4
#define COSC_CONFIG_CONTROL_REG2_MASK 0x07
#define COSC_CONFIG_CONTROL_REG3 0x0ff8
#define COSC_CONFIG_CONTROL_REG3_MASK 0x83
#define COSC_CONFIG_CONTROL_REG4 0x0ffc
#define COSC_CONFIG_CONTROL_REG4_MASK 0xec
#define COSC_CONFIG_TERMINATION 0x1000
#define COSC_CONFIG_TERMINATION_ON 0x01
#define COSC_CONFIG_FIRST_SCANNED 0x1040 /* Used by RiscOS */
#define COSC_CONFIG_INC_FURTHER_PARTS 0x1048 /* Used by RiscOS */
#define COSC_CONFIG_SYNCH_MODE 0x1050
#define COSC_CONFIG_SYNCH_MODE_ON 0x01
#define COSC_CONFIG_SHUTDOWN 0x1054 /* Used by RiscOS */
#define COSC_CONFIG_SHUTDOWN_SPINDOWN 0x01 /* Used by RiscOS */
#define COSC_CONFIG_SHUTDOWN_EJECT 0x02 /* Used by RiscOS */
#define COSC_CONFIG_DELAY_REMOVABLE 0x105c /* Used by RiscOS */
#define COSC_CONFIG_DELAY_HARDDISC 0x1060 /* Used by RiscOS */
#define COSC_CONFIG_DELAY_BOOT 0x1064 /* Used by RiscOS */
#define COSC_CONFIG_CDROM 0x1068 /* Used by RiscOS */
#define COSC_TERMINATION_CONTROL 0x2600
#define COSC_TERMINATION_ON 0x00
#define COSC_TERMINATION_OFF 0x01
#define COSC_REGISTER_00 0x2800
#define COSC_REGISTER_01 0x2a00
#define COSC_PAGE_REGISTER 0x3000
#define COSC_ESCOFFSET_BASE 0x3c00
#define COSC_ESCOFFSET_TCL 0x0000
#define COSC_ESCOFFSET_TCM 0x0004
#define COSC_ESCOFFSET_FIFO 0x0008
#define COSC_ESCOFFSET_COMMAND 0x000c
#define COSC_ESCOFFSET_DESTID 0x0010
#define COSC_ESCOFFSET_TIMEOUT 0x0014
#define COSC_ESCOFFSET_PERIOD 0x0018
#define COSC_ESCOFFSET_OFFSET 0x001c
#define COSC_ESCOFFSET_CONFIG1 0x0020
#define COSC_ESCOFFSET_CLOCKCONV 0x0024
#define COSC_ESCOFFSET_TEST 0x0028
#define COSC_ESCOFFSET_CONFIG2 0x002c
#define COSC_ESCOFFSET_CONFIG3 0x0030
#define COSC_ESCOFFSET_CONFIG4 0x0034
#define COSC_ESCOFFSET_TCH 0x0038
#define COSC_ESCOFFSET_FIFOBOTTOM 0x003c
#endif /* _COSCREG_H_ */

51
sys/arch/arm32/podulebus/coscvar.h
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@ -1,51 +0,0 @@
/* $NetBSD: coscvar.h,v 1.2 2001/03/18 01:31:04 bjh21 Exp $ */
/*
* Copyright (c) 1996 Mark Brinicombe
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Mark Brinicombe
* for the NetBSD Project.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _COSCVAR_H_
#define _COSCVAR_H_
#include <arm32/podulebus/escvar.h>
#include <arm32/podulebus/coscreg.h>
#define COSC_POLL 1
struct cosc_softc {
struct esc_softc sc_softc;
cosc_regmap_t sc_regmap;
vu_char *sc_iobase;
podule_t *sc_podule;
int sc_podule_number;
void *sc_ih;
struct evcnt sc_intrcnt;
};
#endif /* _COCVAR_H_ */

229
sys/arch/arm32/podulebus/csa.c
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@ -1,229 +0,0 @@
/* $NetBSD: csa.c,v 1.12 2001/07/04 17:54:18 bjh21 Exp $ */
/*
* Copyright (c) 1998 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Mark Brinicombe of Causality Limited.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Cumana SCSI 1 driver using the generic NCR5380 driver
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/device.h>
#include <sys/buf.h>
#include <dev/scsipi/scsi_all.h>
#include <dev/scsipi/scsipi_all.h>
#include <dev/scsipi/scsiconf.h>
#include <dev/ic/ncr5380reg.h>
#include <dev/ic/ncr5380var.h>
#include <machine/io.h>
#include <machine/irqhandler.h>
#include <machine/bootconfig.h>
#include <arm32/podulebus/podulebus.h>
#include <dev/podulebus/podules.h>
#include <dev/podulebus/powerromreg.h>
#define CSA_NCR5380_OFFSET 0x2100
#define CSA_CTRL_OFFSET 0x2000 - 2308
#define CSA_DIRWRITE 0x02
#define CSA_DIRREAD 0x00
#define CSA_16BITS 0x00
#define CSA_8BITS 0x10
#define CSA_XXX 0x40
#define CSA_DATA_OFFSET 0x2000
#define CSA_INTR_OFFSET 0x2000
#define CSA_INTR_MASK 0x80
#define CSA_STAT_OFFSET 0x2004
#define CSA_STAT_DRQ 0x40
#define CSA_STAT_END 0x80
void csa_attach __P((struct device *, struct device *, void *));
int csa_match __P((struct device *, struct cfdata *, void *));
/*
* Cumana SCSI 1 softc structure.
*
* Contains the generic ncr5380 device node, podule information and global information
* required by the driver.
*/
struct csa_softc {
struct ncr5380_softc sc_ncr5380;
void *sc_ih;
struct evcnt sc_intrcnt;
int sc_podule_number;
podule_t *sc_podule;
volatile u_char *sc_irqstatus;
u_char sc_irqmask;
volatile u_char *sc_ctrl;
volatile u_char *sc_status;
volatile u_char *sc_data;
};
struct cfattach csa_ca = {
sizeof(struct csa_softc), csa_match, csa_attach
};
int csa_intr __P((void *arg));
/*
* Card probe function
*
* Just match the manufacturer and podule ID's
*/
int
csa_match(parent, cf, aux)
struct device *parent;
struct cfdata *cf;
void *aux;
{
struct podule_attach_args *pa = aux;
if (matchpodule(pa, MANUFACTURER_CUMANA, PODULE_CUMANA_SCSI1, -1))
return(1);
/* PowerROM */
if (pa->pa_product == PODULE_ALSYSTEMS_SCSI &&
podulebus_initloader(pa) == 0 &&
(podloader_callloader(pa, 0, 0) == PRID_CUMANA_SCSI1_8 ||
podloader_callloader(pa, 0, 0) == PRID_CUMANA_SCSI1_16))
return 1;
return 0;
}
/*
* Card attach function
*
*/
void
csa_attach(parent, self, aux)
struct device *parent, *self;
void *aux;
{
struct csa_softc *sc = (struct csa_softc *)self;
struct podule_attach_args *pa = aux;
u_char *iobase;
char hi_option[sizeof(sc->sc_ncr5380.sc_dev.dv_xname) + 8];
/* Note the podule number and validate */
if (pa->pa_podule_number == -1)
panic("Podule has disappeared !");
sc->sc_podule_number = pa->pa_podule_number;
sc->sc_podule = pa->pa_podule;
podules[sc->sc_podule_number].attached = 1;
sc->sc_ncr5380.sc_flags |= NCR5380_FORCE_POLLING;
sc->sc_ncr5380.sc_min_dma_len = 0;
sc->sc_ncr5380.sc_no_disconnect = 0x00;
sc->sc_ncr5380.sc_parity_disable = 0x00;
sc->sc_ncr5380.sc_dma_alloc = NULL;
sc->sc_ncr5380.sc_dma_free = NULL;
sc->sc_ncr5380.sc_dma_poll = NULL;
sc->sc_ncr5380.sc_dma_setup = NULL;
sc->sc_ncr5380.sc_dma_start = NULL;
sc->sc_ncr5380.sc_dma_eop = NULL;
sc->sc_ncr5380.sc_dma_stop = NULL;
sc->sc_ncr5380.sc_intr_on = NULL;
sc->sc_ncr5380.sc_intr_off = NULL;
iobase = (u_char *)pa->pa_podule->slow_base + CSA_NCR5380_OFFSET;
sc->sc_ncr5380.sci_r0 = iobase + 0;
sc->sc_ncr5380.sci_r1 = iobase + 4;
sc->sc_ncr5380.sci_r2 = iobase + 8;
sc->sc_ncr5380.sci_r3 = iobase + 12;
sc->sc_ncr5380.sci_r4 = iobase + 16;
sc->sc_ncr5380.sci_r5 = iobase + 20;
sc->sc_ncr5380.sci_r6 = iobase + 24;
sc->sc_ncr5380.sci_r7 = iobase + 28;
sc->sc_ncr5380.sc_rev = NCR_VARIANT_NCR5380;
sc->sc_ctrl = (u_char *)pa->pa_podule->slow_base + CSA_CTRL_OFFSET;
sc->sc_status = (u_char *)pa->pa_podule->slow_base + CSA_STAT_OFFSET;
sc->sc_data = (u_char *)pa->pa_podule->slow_base + CSA_DATA_OFFSET;
sc->sc_ncr5380.sc_pio_in = ncr5380_pio_in;
sc->sc_ncr5380.sc_pio_out = ncr5380_pio_out;
/* Provide an override for the host id */
sc->sc_ncr5380.sc_channel.chan_id = 7;
sprintf(hi_option, "%s.hostid", sc->sc_ncr5380.sc_dev.dv_xname);
(void)get_bootconf_option(boot_args, hi_option,
BOOTOPT_TYPE_INT, &sc->sc_ncr5380.sc_channel.chan_id);
sc->sc_ncr5380.sc_adapter.adapt_minphys = minphys;
printf(": host=%d, using 8 bit PIO",
sc->sc_ncr5380.sc_channel.chan_id);
sc->sc_irqstatus = (u_char *)pa->pa_podule->slow_base + CSA_INTR_OFFSET;
sc->sc_irqmask = CSA_INTR_MASK;
evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL,
self->dv_xname, "intr");
sc->sc_ih = podulebus_irq_establish(pa->pa_ih, IPL_BIO, csa_intr, sc,
&sc->sc_intrcnt);
if (sc->sc_ih == NULL)
sc->sc_ncr5380.sc_flags |= NCR5380_FORCE_POLLING;
if (sc->sc_ncr5380.sc_flags & NCR5380_FORCE_POLLING)
printf(", polling");
printf("\n");
*sc->sc_ctrl = 0;
ncr5380_attach(&sc->sc_ncr5380);
}
int
csa_intr(arg)
void *arg;
{
struct csa_softc *sc = arg;
if ((*sc->sc_irqstatus) & sc->sc_irqmask)
(void)ncr5380_intr(&sc->sc_ncr5380);
return(0);
}

348
sys/arch/arm32/podulebus/csc.c
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@ -1,348 +0,0 @@
/* $NetBSD: csc.c,v 1.13 2001/07/04 17:54:18 bjh21 Exp $ */
/*-
* Copyright (c) 1998 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Scott Stevens.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Cumana SCSI-2 driver uses the SFAS216 generic driver
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/device.h>
#include <dev/scsipi/scsi_all.h>
#include <dev/scsipi/scsipi_all.h>
#include <dev/scsipi/scsiconf.h>
#include <uvm/uvm_extern.h>
#include <machine/pmap.h>
#include <machine/io.h>
#include <machine/irqhandler.h>
#include <machine/bootconfig.h>
#include <arm32/podulebus/podulebus.h>
#include <arm32/podulebus/sfasreg.h>
#include <arm32/podulebus/sfasvar.h>
#include <arm32/podulebus/cscreg.h>
#include <arm32/podulebus/cscvar.h>
#include <dev/podulebus/podules.h>
#include <dev/podulebus/powerromreg.h>
void cscattach __P((struct device *, struct device *, void *));
int cscmatch __P((struct device *, struct cfdata *, void *));
void csc_scsi_request __P((struct scsipi_channel *,
scsipi_adapter_req_t, void *));
struct cfattach csc_ca = {
sizeof(struct csc_softc), cscmatch, cscattach
};
int csc_intr __P((void *arg));
int csc_setup_dma __P((struct sfas_softc *sc, void *ptr, int len,
int mode));
int csc_build_dma_chain __P((struct sfas_softc *sc,
struct sfas_dma_chain *chain, void *p, int l));
int csc_need_bump __P((struct sfas_softc *sc, void *ptr, int len));
void csc_led __P((struct sfas_softc *sc, int mode));
/*
* if we are a Cumana SCSI-2 card
*/
int
cscmatch(pdp, cf, auxp)
struct device *pdp;
struct cfdata *cf;
void *auxp;
{
struct podule_attach_args *pa = (struct podule_attach_args *)auxp;
/* Look for the card */
if (matchpodule(pa, MANUFACTURER_CUMANA, PODULE_CUMANA_SCSI2, -1))
return 1;
/* PowerROM */
if (pa->pa_product == PODULE_ALSYSTEMS_SCSI &&
podulebus_initloader(pa) == 0 &&
podloader_callloader(pa, 0, 0) == PRID_CUMANA_SCSI2)
return 1;
return 0;
}
void
cscattach(pdp, dp, auxp)
struct device *pdp;
struct device *dp;
void *auxp;
{
struct csc_softc *sc = (struct csc_softc *)dp;
struct podule_attach_args *pa;
csc_regmap_p rp = &sc->sc_regmap;
vu_char *fas;
int loop;
pa = (struct podule_attach_args *)auxp;
if (pa->pa_podule_number == -1)
panic("Podule has disappeared !");
sc->sc_specific.sc_podule_number = pa->pa_podule_number;
sc->sc_specific.sc_podule = pa->pa_podule;
sc->sc_specific.sc_iobase =
(vu_char *)sc->sc_specific.sc_podule->mod_base;
rp->status0 = &sc->sc_specific.sc_iobase[CSC_STATUS0];
rp->alatch = &sc->sc_specific.sc_iobase[CSC_ALATCH];
rp->dack = (vu_short *)&sc->sc_specific.sc_iobase[CSC_DACK];
fas = &sc->sc_specific.sc_iobase[CSC_FAS_OFFSET_BASE];
rp->FAS216.sfas_tc_low = &fas[CSC_FAS_OFFSET_TCL];
rp->FAS216.sfas_tc_mid = &fas[CSC_FAS_OFFSET_TCM];
rp->FAS216.sfas_fifo = &fas[CSC_FAS_OFFSET_FIFO];
rp->FAS216.sfas_command = &fas[CSC_FAS_OFFSET_COMMAND];
rp->FAS216.sfas_dest_id = &fas[CSC_FAS_OFFSET_DESTID];
rp->FAS216.sfas_timeout = &fas[CSC_FAS_OFFSET_TIMEOUT];
rp->FAS216.sfas_syncper = &fas[CSC_FAS_OFFSET_PERIOD];
rp->FAS216.sfas_syncoff = &fas[CSC_FAS_OFFSET_OFFSET];
rp->FAS216.sfas_config1 = &fas[CSC_FAS_OFFSET_CONFIG1];
rp->FAS216.sfas_clkconv = &fas[CSC_FAS_OFFSET_CLKCONV];
rp->FAS216.sfas_test = &fas[CSC_FAS_OFFSET_TEST];
rp->FAS216.sfas_config2 = &fas[CSC_FAS_OFFSET_CONFIG2];
rp->FAS216.sfas_config3 = &fas[CSC_FAS_OFFSET_CONFIG3];
rp->FAS216.sfas_tc_high = &fas[CSC_FAS_OFFSET_TCH];
rp->FAS216.sfas_fifo_bot = &fas[CSC_FAS_OFFSET_FIFOBOT];
sc->sc_softc.sc_fas = (sfas_regmap_p)rp;
sc->sc_softc.sc_spec = &sc->sc_specific;
sc->sc_softc.sc_led = csc_led;
sc->sc_softc.sc_setup_dma = csc_setup_dma;
sc->sc_softc.sc_build_dma_chain = csc_build_dma_chain;
sc->sc_softc.sc_need_bump = csc_need_bump;
sc->sc_softc.sc_clock_freq = 8; /* Cumana runs at 8MHz */
sc->sc_softc.sc_timeout = 250; /* Set default timeout to 250ms */
sc->sc_softc.sc_config_flags = SFAS_NO_DMA /*| SFAS_NF_DEBUG*/;
sc->sc_softc.sc_host_id = 7; /* Should check the jumpers */
sc->sc_softc.sc_bump_sz = NBPG;
sc->sc_softc.sc_bump_pa = 0x0;
sfasinitialize((struct sfas_softc *)sc);
sc->sc_softc.sc_adapter.adapt_dev = &sc->sc_softc.sc_dev;
sc->sc_softc.sc_adapter.adapt_nchannels = 1;
sc->sc_softc.sc_adapter.adapt_openings = 7;
sc->sc_softc.sc_adapter.adapt_max_periph = 1;
sc->sc_softc.sc_adapter.adapt_ioctl = NULL;
sc->sc_softc.sc_adapter.adapt_minphys = sfas_minphys;
sc->sc_softc.sc_adapter.adapt_request = csc_scsi_request;
sc->sc_softc.sc_channel.chan_adapter = &sc->sc_softc.sc_adapter;
sc->sc_softc.sc_channel.chan_bustype = &scsi_bustype;
sc->sc_softc.sc_channel.chan_channel = 0;
sc->sc_softc.sc_channel.chan_ntargets = 8;
sc->sc_softc.sc_channel.chan_nluns = 8;
sc->sc_softc.sc_channel.chan_id = sc->sc_softc.sc_host_id;
/* Provide an override for the host id */
(void)get_bootconf_option(boot_args, "csc.hostid",
BOOTOPT_TYPE_INT, &sc->sc_softc.sc_channel.chan_id);
printf(": host=%d", sc->sc_softc.sc_channel.chan_id);
/* initialise the alatch */
sc->sc_specific.sc_alatch_defs = (CSC_POLL?0:CSC_ALATCH_DEFS_INTEN);
for (loop = 0; loop < 8; loop ++) {
if(loop != 3)
*rp->alatch = (loop << 1) |
((sc->sc_specific.sc_alatch_defs & (1 << loop))?1:0);
}
#if CSC_POLL == 0
evcnt_attach_dynamic(&sc->sc_softc.sc_intrcnt, EVCNT_TYPE_INTR, NULL,
dp->dv_xname, "intr");
sc->sc_softc.sc_ih = podulebus_irq_establish(pa->pa_ih, IPL_BIO,
csc_intr, &sc->sc_softc, &sc->sc_softc.sc_intrcnt);
if (sc->sc_softc.sc_ih == NULL)
panic("%s: Cannot install IRQ handler\n", dp->dv_xname);
#else
printf(" polling");
#endif
printf("\n");
/* attach all scsi units on us */
config_found(dp, &sc->sc_softc.sc_channel, scsiprint);
}
int
csc_intr(arg)
void *arg;
{
struct sfas_softc *dev = arg;
csc_regmap_p rp;
int quickints;
rp = (csc_regmap_p)dev->sc_fas;
if (*rp->FAS216.sfas_status & SFAS_STAT_INTERRUPT_PENDING) {
quickints = 16;
do {
dev->sc_status = *rp->FAS216.sfas_status;
dev->sc_interrupt = *rp->FAS216.sfas_interrupt;
if (dev->sc_interrupt & SFAS_INT_RESELECTED) {
dev->sc_resel[0] = *rp->FAS216.sfas_fifo;
dev->sc_resel[1] = *rp->FAS216.sfas_fifo;
}
sfasintr(dev);
} while((*rp->FAS216.sfas_status & SFAS_STAT_INTERRUPT_PENDING)
&& --quickints);
}
return(0); /* Pass interrupt on down the chain */
}
/* Load transfer address into dma register */
void
csc_set_dma_adr(sc, ptr)
struct sfas_softc *sc;
void *ptr;
{
return;
}
/* Set DMA transfer counter */
void
csc_set_dma_tc(sc, len)
struct sfas_softc *sc;
unsigned int len;
{
*sc->sc_fas->sfas_tc_low = len; len >>= 8;
*sc->sc_fas->sfas_tc_mid = len; len >>= 8;
*sc->sc_fas->sfas_tc_high = len;
}
/* Set DMA mode */
void
csc_set_dma_mode(sc, mode)
struct sfas_softc *sc;
int mode;
{
}
/* Initialize DMA for transfer */
int
csc_setup_dma(sc, ptr, len, mode)
struct sfas_softc *sc;
void *ptr;
int len;
int mode;
{
return(0);
}
/* Check if address and len is ok for DMA transfer */
int
csc_need_bump(sc, ptr, len)
struct sfas_softc *sc;
void *ptr;
int len;
{
int p;
p = (int)ptr & 0x03;
if (p) {
p = 4-p;
if (len < 256)
p = len;
}
return(p);
}
/* Interrupt driven routines */
int
csc_build_dma_chain(sc, chain, p, l)
struct sfas_softc *sc;
struct sfas_dma_chain *chain;
void *p;
int l;
{
return(0);
}
/* Turn on/off led */
void
csc_led(sc, mode)
struct sfas_softc *sc;
int mode;
{
csc_regmap_p rp;
rp = (csc_regmap_p)sc->sc_fas;
if (mode) {
sc->sc_led_status++;
} else {
if (sc->sc_led_status)
sc->sc_led_status--;
}
}
void
csc_scsi_request(chan, req, arg)
struct scsipi_channel *chan;
scsipi_adapter_req_t req;
void *arg;
{
struct scsipi_xfer *xs;
switch (req) {
case ADAPTER_REQ_RUN_XFER:
xs = arg;
/* ensure command is polling for the moment */
#if CSC_POLL > 0
xs->xs_control |= XS_CTL_POLL;
#endif
default:
}
sfas_scsi_request(chan, req, arg);
}

95
sys/arch/arm32/podulebus/cscreg.h
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@ -1,95 +0,0 @@
/* $NetBSD: cscreg.h,v 1.1 1998/09/01 02:24:12 mark Exp $ */
/*-
* Copyright (c) 1998 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Scott Stevens.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Cumana SCSI-2 with FAS216 SCSI interface hardware description.
*/
#ifndef _CSCREG_H_
#define _CSCREG_H_
#include <arm32/podulebus/sfasvar.h>
typedef volatile unsigned short vu_short;
typedef struct csc_regmap {
sfas_regmap_t FAS216;
vu_char *status0;
vu_char *alatch;
vu_short *dack;
} csc_regmap_t;
typedef csc_regmap_t *csc_regmap_p;
/*
* Register information
*/
#define CSC_STATUS0 0x0000
#define CSC_ALATCH 0x0014
#define CSC_DACK 0x0200
#define CSC_FAS_OFFSET_BASE 0x0300
#define CSC_FAS_OFFSET_TCL 0x00
#define CSC_FAS_OFFSET_TCM 0x04
#define CSC_FAS_OFFSET_FIFO 0x08
#define CSC_FAS_OFFSET_COMMAND 0x0c
#define CSC_FAS_OFFSET_DESTID 0x10
#define CSC_FAS_OFFSET_TIMEOUT 0x14
#define CSC_FAS_OFFSET_PERIOD 0x18
#define CSC_FAS_OFFSET_OFFSET 0x1c
#define CSC_FAS_OFFSET_CONFIG1 0x20
#define CSC_FAS_OFFSET_CLKCONV 0x24
#define CSC_FAS_OFFSET_TEST 0x28
#define CSC_FAS_OFFSET_CONFIG2 0x2c
#define CSC_FAS_OFFSET_CONFIG3 0x30
#define CSC_FAS_OFFSET_TCH 0x38
#define CSC_FAS_OFFSET_FIFOBOT 0x3c
#define CSC_STATUS0_INT 0x01
#define CSC_STATUS0_DREQ 0x02
#define CSC_STATUS0_EDOUT 0x04
#define CSC_STATUS0_LATCHED 0x08
#define CSC_ALATCH_DEFS_P7 0x01
#define CSC_ALATCH_DEFS_INTEN 0x02
#define CSC_ALATCH_DEFS_TERM 0x04
#define CSC_ALATCH_DEFS_RSVD 0x08
#define CSC_ALATCH_DEFS_PROG 0x10
#define CSC_ALATCH_DEFS_DMA32 0x20
#define CSC_ALATCH_DEFS_DMAEN 0x40
#define CSC_ALATCH_DEFS_DMADIR 0x80
#endif

60
sys/arch/arm32/podulebus/cscvar.h
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@ -1,60 +0,0 @@
/* $NetBSD: cscvar.h,v 1.1 1998/09/01 02:24:12 mark Exp $ */
/*-
* Copyright (c) 1998 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Scott Stevens.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _CSCVAR_H_
#define _CSCVAR_H_
#include <arm32/podulebus/sfasvar.h>
#include <arm32/podulebus/cscreg.h>
#define CSC_POLL 1
struct csc_specific {
vu_char *sc_iobase;
u_char sc_alatch_defs;
int sc_podule_number;
podule_t *sc_podule;
};
struct csc_softc {
struct sfas_softc sc_softc;
csc_regmap_t sc_regmap;
struct csc_specific sc_specific;
};
#endif /* _CSCVAR_H_ */

1637
sys/arch/arm32/podulebus/esc.c
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File diff suppressed because it is too large Load Diff

165
sys/arch/arm32/podulebus/escreg.h
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@ -1,165 +0,0 @@
/* $NetBSD: escreg.h,v 1.1 1996/10/15 00:05:06 mark Exp $ */
/*
* Copyright (c) 1995 Daniel Widenfalk
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Daniel Widenfalk
* for the NetBSD Project.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ESCREG_H_
#define _ESCREG_H_
/*
* AMD AM53CF94 SCSI interface hardware description.
*/
typedef volatile unsigned char vu_char;
typedef struct {
vu_char *esc_tc_low; /* rw: Transfer count low */
vu_char *esc_tc_mid; /* rw: Transfer count mid */
vu_char *esc_fifo; /* rw: Data FIFO */
vu_char *esc_command; /* rw: Chip command reg */
vu_char *esc_dest_id; /* w: (Re)select bus ID */
#define esc_status esc_dest_id /* r: Status */
vu_char *esc_timeout; /* w: (Re)select timeout */
#define esc_interrupt esc_timeout /* r: Interrupt */
vu_char *esc_syncper; /* w: Synch. transfer period */
#define esc_seqstep esc_syncper /* r: Sequence step */
vu_char *esc_syncoff; /* w: Synch. transfer offset */
#define esc_fifo_flags esc_syncoff /* r: FIFO flags */
vu_char *esc_config1; /* rw: Config register #1 */
vu_char *esc_clkconv; /* w: Clock conv. factor */
vu_char *esc_test; /* w: Test register */
vu_char *esc_config2; /* rw: Config register #2 */
vu_char *esc_config3; /* rw: Config register #3 */
vu_char *esc_config4; /* rw: Config register #4 */
vu_char *esc_tc_high; /* rw: Transfer count high */
vu_char *esc_fifo_bot; /* w: FIFO bottom register */
} esc_regmap_t;
typedef esc_regmap_t *esc_regmap_p;
/* Commands for the FAS216 */
#define ESC_CMD_DMA 0x80
#define ESC_CMD_SEL_NO_ATN 0x41
#define ESC_CMD_SEL_ATN 0x42
#define ESC_CMD_SEL_ATN3 0x46
#define ESC_CMD_SEL_ATN_STOP 0x43
#define ESC_CMD_ENABLE_RESEL 0x44
#define ESC_CMD_DISABLE_RESEL 0x45
#define ESC_CMD_TRANSFER_INFO 0x10
#define ESC_CMD_TRANSFER_PAD 0x98
#define ESC_CMD_COMMAND_COMPLETE 0x11
#define ESC_CMD_MESSAGE_ACCEPTED 0x12
#define ESC_CMD_SET_ATN 0x1A
#define ESC_CMD_RESET_ATN 0x1B
#define ESC_CMD_NOP 0x00
#define ESC_CMD_FLUSH_FIFO 0x01
#define ESC_CMD_RESET_CHIP 0x02
#define ESC_CMD_RESET_SCSI_BUS 0x03
#define ESC_STAT_PHASE_MASK 0x07
#define ESC_STAT_PHASE_TRANS_CPLT 0x08
#define ESC_STAT_TRANSFER_COUNT_ZERO 0x10
#define ESC_STAT_PARITY_ERROR 0x20
#define ESC_STAT_GROSS_ERROR 0x40
#define ESC_STAT_INTERRUPT_PENDING 0x80
#define ESC_PHASE_DATA_OUT 0
#define ESC_PHASE_DATA_IN 1
#define ESC_PHASE_COMMAND 2
#define ESC_PHASE_STATUS 3
#define ESC_PHASE_MESSAGE_OUT 6
#define ESC_PHASE_MESSAGE_IN 7
#define ESC_DEST_ID_MASK 0x07
#define ESC_INT_SELECTED 0x01
#define ESC_INT_SELECTED_WITH_ATN 0x02
#define ESC_INT_RESELECTED 0x04
#define ESC_INT_FUNCTION_COMPLETE 0x08
#define ESC_INT_BUS_SERVICE 0x10
#define ESC_INT_DISCONNECT 0x20
#define ESC_INT_ILLEGAL_COMMAND 0x40
#define ESC_INT_SCSI_RESET_DETECTED 0x80
#define ESC_SYNCHRON_PERIOD_MASK 0x1F
#define ESC_FIFO_COUNT_MASK 0x1F
#define ESC_FIFO_SEQUENCE_STEP_MASK 0xE0
#define ESC_FIFO_SEQUENCE_SHIFT 5
#define ESC_SYNCHRON_OFFSET_MASK 0x0F
#define ESC_SYNC_ASSERT_MASK 0x30
#define ESC_SYNC_ASSERT_SHIFT 4
#define ESC_SYNC_DEASSERT_MASK 0x30
#define ESC_SYNC_DEASSERT_SHIFT 6
#define ESC_CFG1_BUS_ID_MASK 0x07
#define ESC_CFG1_CHIP_TEST_MODE 0x08
#define ESC_CFG1_SCSI_PARITY_ENABLE 0x10
#define ESC_CFG1_PARITY_TEST_MODE 0x20
#define ESC_CFG1_SCSI_RES_INT_DIS 0x40
#define ESC_CFG1_SLOW_CABLE_MODE 0x80
#define ESC_CLOCK_CONVERSION_MASK 0x07
#define ESC_TEST_TARGET_TEST_MODE 0x01
#define ESC_TEST_INITIATOR_TEST_MODE 0x02
#define ESC_TEST_TRISTATE_TEST_MODE 0x04
#define ESC_CFG2_DMA_PARITY_ENABLE 0x01
#define ESC_CFG2_REG_PARITY_ENABLE 0x02
#define ESC_CFG2_TARG_BAD_PARITY_ABORT 0x04
#define ESC_CFG2_SCSI_2_MODE 0x08
#define ESC_CFG2_TRISTATE_DMA_REQ 0x10
#define ESC_CFG2_BYTE_CONTROL_MODE 0x20
#define ESC_CFG2_FEATURES_ENABLE 0x40
#define ESC_CFG2_RESERVE_FIFO_BYTE 0x80
#define ESC_CFG3_THRESHOLD_8_MODE 0x01
#define ESC_CFG3_ALTERNATE_DMA_MODE 0x02
#define ESC_CFG3_SAVE_RESIDUAL_BYTE 0x04
#define ESC_CFG3_FASTCLK 0x08
#define ESC_CFG3_FASTSCSI 0x10
#define ESC_CFG3_CDB10 0x20
#define ESC_CFG3_QENB 0x40
#define ESC_CFG3_IDRESCHK 0x80
#define ESC_CFG4_RADE 0x04
#define ESC_CFG4_RAE 0x08
#define ESC_CFG4_POWERDOWN 0x20
#define ESC_CFG4_GLITCH_EATER_0 0x40
#define ESC_CFG4_GLITCH_EATER_1 0x80
#endif

265
sys/arch/arm32/podulebus/escvar.h
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@ -1,265 +0,0 @@
/* $NetBSD: escvar.h,v 1.6 2001/06/12 15:17:17 wiz Exp $ */
/*
* Copyright (c) 1995 Daniel Widenfalk
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Daniel Widenfalk
* for the NetBSD Project.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ESCVAR_H_
#define _ESCVAR_H_
#ifndef _ESCREG_H_
#include <arm32/podulebus/escreg.h>
#endif
/*
* MAXCHAIN is the anticipated maximum number of chain blocks needed. This
* assumes that we are NEVER requested to transfer more than MAXPHYS bytes.
*/
#define MAXCHAIN (MAXPHYS/NBPG+2)
/*
* Maximum number of requests standing by. Could be anything, but I think 9
* looks nice :-) NOTE: This does NOT include requests already started!
*/
#define MAXPENDING 9 /* 7 IDs + 2 extra */
/*
* DMA chain block. If flg == ESC_CHAIN_PRG or flg == ESC_CHAIN_BUMP then
* ptr is a VIRTUAL adress. If flg == ESC_CHAIN_DMA then ptr is a PHYSICAL
* adress.
*/
struct esc_dma_chain {
vm_offset_t ptr;
u_short len;
short flg;
};
#define ESC_CHAIN_DMA 0x00
#define ESC_CHAIN_BUMP 0x01
#define ESC_CHAIN_PRG 0x02
/*
* This struct contains the necessary info for a pending request. Pointer to
* a scsipi_xfer struct.
*/
struct esc_pending {
TAILQ_ENTRY(esc_pending) link;
struct scsipi_xfer *xs;
};
/*
* nexus contains all active data for one SCSI unit. Parts of the info in this
* struct survives between scsi commands.
*/
struct nexus {
struct scsipi_xfer *xs; /* Pointer to request */
u_char ID; /* ID message to be sent */
u_char clen; /* scsi command length + */
u_char cbuf[14]; /* the actual command bytes */
struct esc_dma_chain dma[MAXCHAIN]; /* DMA chain blocks */
short max_link; /* Maximum used of above */
short cur_link; /* Currently handled block */
u_char *buf; /* Virtual adress of data */
int len; /* Bytes left to transfer */
vm_offset_t dma_buf; /* Current DMA adress */
int dma_len; /* Current DMA length */
vm_offset_t dma_blk_ptr; /* Current chain adress */
int dma_blk_len; /* Current chain length */
u_char dma_blk_flg; /* Current chain flags */
u_char state; /* Nexus state, see below */
u_short flags; /* Nexus flags, see below */
short period; /* Sync period to request */
u_char offset; /* Sync offset to request */
u_char syncper; /* FAS216 variable storage */
u_char syncoff; /* FAS216 variable storage */
u_char config3; /* FAS216 variable storage */
u_char lun_unit; /* (Lun<<4) | Unit of nexus */
u_char status; /* Status byte from unit*/
};
/* SCSI nexus_states */
#define ESC_NS_IDLE 0 /* Nexus idle */
#define ESC_NS_SELECTED 1 /* Last command was a SELECT command */
#define ESC_NS_DATA_IN 2 /* Last command was a TRANSFER_INFO */
/* command during a data in phase */
#define ESC_NS_DATA_OUT 3 /* Last command was a TRANSFER_INFO */
/* command during a data out phase */
#define ESC_NS_STATUS 4 /* We have send a COMMAND_COMPLETE */
/* command and are awaiting status */
#define ESC_NS_MSG_IN 5 /* Last phase was MESSAGE IN */
#define ESC_NS_MSG_OUT 6 /* Last phase was MESSAGE OUT */
#define ESC_NS_SVC 7 /* We have sent the command */
#define ESC_NS_DISCONNECTING 8 /* We have received a disconnect msg */
#define ESC_NS_DISCONNECTED 9 /* We are disconnected */
#define ESC_NS_RESELECTED 10 /* We was reselected */
#define ESC_NS_DONE 11 /* Done. Prephsase to FINISHED */
#define ESC_NS_FINISHED 12 /* Realy done. Call scsi_done */
#define ESC_NS_RESET 13 /* We are reseting this unit */
/* SCSI nexus flags */
#define ESC_NF_UNIT_BUSY 0x0001 /* Unit is not available */
#define ESC_NF_SELECT_ME 0x0002 /* Nexus is set up, waiting for bus */
#define ESC_NF_HAS_MSG 0x0010 /* We have received a complete msg */
#define ESC_NF_DO_SDTR 0x0020 /* We should send a SDTR */
#define ESC_NF_SDTR_SENT 0x0040 /* We have sent a SDTR */
#define ESC_NF_SYNC_TESTED 0x0080 /* We have negotiated sync */
#define ESC_NF_RESET 0x0100 /* Reset this nexus */
#define ESC_NF_IMMEDIATE 0x0200 /* We are operating from escicmd */
#define ESC_NF_RETRY_SELECT 0x1000 /* Selection needs retrying */
#define ESC_NF_DEBUG 0x8000 /* As it says: DEBUG */
struct esc_softc {
struct device sc_dev; /* System required struct */
struct scsipi_channel sc_channel; /* For sub devices */
struct scsipi_adapter sc_adapter;
irqhandler_t sc_ih; /* Interrupt chain struct */
TAILQ_HEAD(,esc_pending) sc_xs_pending;
TAILQ_HEAD(,esc_pending) sc_xs_free;
struct esc_pending sc_xs_store[MAXPENDING];
esc_regmap_p sc_esc; /* FAS216 Address */
void *sc_spec; /* Board-specific data */
u_char *sc_bump_va; /* Bumpbuf virtual adr */
vm_offset_t sc_bump_pa; /* Bumpbuf physical adr */
int sc_bump_sz; /* Bumpbuf size */
/* Configuration registers, must be set BEFORE escinitialize */
u_char sc_clock_freq;
u_short sc_timeout;
u_char sc_host_id;
u_char sc_config_flags;
/* Generic DMA functions */
int (*sc_setup_dma)();
int (*sc_build_dma_chain)();
int (*sc_need_bump)();
/* Generic Led data */
int sc_led_status;
void (*sc_led)();
/* Nexus list */
struct nexus sc_nexus[8];
struct nexus *sc_cur_nexus;
struct nexus *sc_sel_nexus;
/* Current transfer data */
u_char *sc_buf; /* va */
int sc_len;
vm_offset_t sc_dma_buf; /* pa */
int sc_dma_len;
vm_offset_t sc_dma_blk_ptr;
int sc_dma_blk_len;
short sc_dma_blk_flg;
struct esc_dma_chain *sc_chain; /* Current DMA chain */
short sc_max_link;
short sc_cur_link;
/* Interrupt registers */
u_char sc_status;
u_char sc_interrupt;
u_char sc_resel[2];
u_char sc_units_disconnected;
/* Storage for FAS216 config registers (current values) */
u_char sc_config1;
u_char sc_config2;
u_char sc_config3;
u_char sc_config4;
u_char sc_clock_conv_fact;
u_char sc_timeout_val;
u_char sc_clock_period;
u_char sc_msg_in[7];
u_char sc_msg_in_len;
u_char sc_msg_out[7];
u_char sc_msg_out_len;
u_char sc_unit;
u_char sc_lun;
u_char sc_flags;
};
#define ESC_DMA_READ 0
#define ESC_DMA_WRITE 1
#define ESC_DMA_CLEAR 2
/* sc_flags */
#define ESC_ACTIVE 0x01
#define ESC_DONT_WAIT 0x02
/* SCSI Selection modes */
#define ESC_SELECT 0x00 /* Normal selection: No sync, no resel */
#define ESC_SELECT_R 0x01 /* Reselection allowed */
#define ESC_SELECT_S 0x02 /* Synchronous transfer allowed */
#define ESC_SELECT_I 0x04 /* Selection for escicmd */
#define ESC_SELECT_K 0x08 /* Send a BUS DEVICE RESET message (Kill) */
/* Nice abbreviations of the above */
#define ESC_SELECT_RS (ESC_SELECT_R|ESC_SELECT_S)
#define ESC_SELECT_RI (ESC_SELECT_R|ESC_SELECT_I)
#define ESC_SELECT_SI (ESC_SELECT_S|ESC_SELECT_I)
#define ESC_SELECT_RSI (ESC_SELECT_R|ESC_SELECT_S|ESC_SELECT_I)
/* sc_config_flags */
#define ESC_NO_SYNCH 0x01 /* Disable synchronous transfer */
#define ESC_NO_DMA 0x02 /* Do not use DMA! EVER! */
#define ESC_NO_RESELECT 0x04 /* Do not allow relesection */
#define ESC_SLOW_CABLE 0x08 /* Cable is "unsafe" for fast scsi-2 */
#define ESC_SLOW_START 0x10 /* There are slow starters on the bus */
void escinitialize __P((struct esc_softc *sc));
void esc_minphys __P((struct buf *bp));
void esc_scsi_request __P((struct scsipi_channel *,
scsipi_adapter_req_t, void *));
void escintr __P((struct esc_softc *dev));
#endif /* _ESCVAR_H_ */

326
sys/arch/arm32/podulebus/icside.c
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@ -1,326 +0,0 @@
/* $NetBSD: icside.c,v 1.15 2001/03/18 15:56:05 bjh21 Exp $ */
/*
* Copyright (c) 1997-1998 Mark Brinicombe
* Copyright (c) 1997-1998 Causality Limited
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Mark Brinicombe
* for the NetBSD Project.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Probe and attach functions to use generic IDE driver for the ICS IDE podule
*/
/*
* Thanks to David Baildon for loaning an IDE card for the development
* of this driver.
* Thanks to Ian Copestake and David Baildon for providing register mapping
* information
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/conf.h>
#include <sys/device.h>
#include <sys/malloc.h>
#include <machine/irqhandler.h>
#include <machine/io.h>
#include <machine/bus.h>
#include <arm32/podulebus/podulebus.h>
#include <arm32/podulebus/icsidereg.h>
#include <dev/ata/atavar.h>
#include <dev/ic/wdcvar.h>
#include <dev/podulebus/podules.h>
/*
* ICS IDE podule device.
*
* This probes and attaches the top level ICS IDE device to the podulebus.
* It then configures any children of the ICS IDE device.
* The child is expected to be a wdc device using icside attachments.
*/
/*
* ICS IDE card softc structure.
*
* Contains the device node and podule information.
*/
struct icside_softc {
struct wdc_softc sc_wdcdev; /* common wdc definitions */
podule_t *sc_podule; /* Our podule */
int sc_podule_number; /* Our podule number */
struct bus_space sc_tag; /* custom tag */
struct podule_attach_args *sc_pa; /* podule info */
struct icside_channel {
struct channel_softc wdc_channel; /* generic part */
void *ic_ih; /* interrupt handler */
struct evcnt ic_intrcnt; /* interrupt count */
u_int ic_irqaddr; /* interrupt flag */
u_int ic_irqmask; /* location */
bus_space_tag_t ic_irqiot; /* Bus space tag */
bus_space_handle_t ic_irqioh; /* handle for IRQ */
} *icside_channels;
};
int icside_probe __P((struct device *, struct cfdata *, void *));
void icside_attach __P((struct device *, struct device *, void *));
int icside_intr __P((void *));
struct cfattach icside_ca = {
sizeof(struct icside_softc), icside_probe, icside_attach
};
/*
* Define prototypes for custom bus space functions.
*/
bs_rm_2_proto(icside);
bs_wm_2_proto(icside);
#define MAX_CHANNELS 2
/*
* Define a structure for describing the different card versions
*/
struct ide_version {
int id; /* IDE card ID */
int modspace; /* Type of podule space */
int channels; /* Number of channels */
const char *name; /* name */
int ideregs[MAX_CHANNELS]; /* IDE registers */
int auxregs[MAX_CHANNELS]; /* AUXSTAT register */
int irqregs[MAX_CHANNELS]; /* IRQ register */
int irqstatregs[MAX_CHANNELS];
} ide_versions[] = {
/* A3IN - Unsupported */
/* { 0, 0, 0, NULL, { 0, 0 }, { 0, 0 }, { 0, 0 }, { 0, 0 } },*/
/* A3USER - Unsupported */
/* { 1, 0, 0, NULL, { 0, 0 }, { 0, 0 }, { 0, 0 }, { 0, 0 } },*/
/* ARCIN V6 - Supported */
{ 3, 0, 2, "ARCIN V6",
{ V6_P_IDE_BASE, V6_S_IDE_BASE },
{ V6_P_AUX_BASE, V6_S_AUX_BASE },
{ V6_P_IRQ_BASE, V6_S_IRQ_BASE },
{ V6_P_IRQSTAT_BASE, V6_S_IRQSTAT_BASE }
},
/* ARCIN V5 - Supported (ID reg not supported so reads as 15) */
{ 15, 1, 1, "ARCIN V5",
{ V5_IDE_BASE, 0 },
{ V5_AUX_BASE, 0 },
{ V5_IRQ_BASE, 0 },
{ V5_IRQSTAT_BASE, 0 }
}
};
/*
* Card probe function
*
* Just match the manufacturer and podule ID's
*/
int
icside_probe(parent, cf, aux)
struct device *parent;
struct cfdata *cf;
void *aux;
{
struct podule_attach_args *pa = (void *)aux;
if (matchpodule(pa, MANUFACTURER_ICS, PODULE_ICS_IDE, -1) == 0)
return(0);
return(1);
}
/*
* Card attach function
*
* Identify the card version and configure any children.
*/
void
icside_attach(parent, self, aux)
struct device *parent, *self;
void *aux;
{
struct icside_softc *sc = (void *)self;
struct podule_attach_args *pa = (void *)aux;
bus_space_tag_t iot;
bus_space_handle_t ioh;
struct ide_version *ide = NULL;
u_int iobase;
int channel;
struct icside_channel *icp;
struct channel_softc *cp;
int loop;
int id;
/* Note the podule number and validate */
if (pa->pa_podule_number == -1)
panic("Podule has disappeared !");
sc->sc_podule_number = pa->pa_podule_number;
sc->sc_podule = pa->pa_podule;
podules[sc->sc_podule_number].attached = 1;
/* The ID register if present is always in FAST podule space */
iot = pa->pa_iot;
if (bus_space_map(iot, pa->pa_podule->fast_base +
ID_REGISTER_OFFSET, ID_REGISTER_SPACE, 0, &ioh)) {
printf("%s: cannot map ID register\n", self->dv_xname);
return;
}
for (id = 0, loop = 0; loop < 4; ++loop)
id |= (bus_space_read_1(iot, ioh, loop) & 1) << loop;
/* Do we recognise the ID ? */
for (loop = 0; loop < sizeof(ide_versions) / sizeof(struct ide_version);
++loop) {
if (ide_versions[loop].id == id) {
ide = &ide_versions[loop];
break;
}
}
/* Report the version and name */
if (ide == NULL || ide->name == NULL) {
printf(": rev %d is unsupported\n", id);
return;
} else
printf(": %s\n", ide->name);
/*
* Ok we need our own bus tag as the register spacing
* is not the default.
*
* For the podulebus the bus tag cookie is the shift
* to apply to registers
* So duplicate the bus space tag and change the
* cookie.
*
* Also while we are at it replace the default
* read/write mulitple short functions with
* optimised versions
*/
sc->sc_tag = *pa->pa_iot;
sc->sc_tag.bs_cookie = (void *) REGISTER_SPACING_SHIFT;
sc->sc_tag.bs_rm_2 = icside_bs_rm_2;
sc->sc_tag.bs_wm_2 = icside_bs_wm_2;
/* Initialize wdc struct */
sc->sc_wdcdev.channels = malloc(
sizeof(struct channel_softc *) * ide->channels, M_DEVBUF, M_NOWAIT);
sc->icside_channels = malloc(
sizeof(struct icside_channel) * ide->channels, M_DEVBUF, M_NOWAIT);
if (sc->sc_wdcdev.channels == NULL || sc->icside_channels == NULL) {
printf("%s: can't allocate channel infos\n",
sc->sc_wdcdev.sc_dev.dv_xname);
return;
}
sc->sc_wdcdev.nchannels = ide->channels;
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16;
sc->sc_wdcdev.PIO_cap = 0;
sc->sc_pa = pa;
for (channel = 0; channel < ide->channels; ++channel) {
icp = &sc->icside_channels[channel];
sc->sc_wdcdev.channels[channel] = &icp->wdc_channel;
cp = &icp->wdc_channel;
cp->channel = channel;
cp->wdc = &sc->sc_wdcdev;
cp->ch_queue = malloc(sizeof(struct channel_queue), M_DEVBUF,
M_NOWAIT);
if (cp->ch_queue == NULL) {
printf("%s %s channel: "
"can't allocate memory for command queue",
sc->sc_wdcdev.sc_dev.dv_xname,
(channel == 0) ? "primary" : "secondary");
continue;
}
cp->cmd_iot = &sc->sc_tag;
cp->ctl_iot = &sc->sc_tag;
if (ide->modspace)
iobase = pa->pa_podule->mod_base;
else
iobase = pa->pa_podule->fast_base;
if (bus_space_map(iot, iobase + ide->ideregs[channel],
IDE_REGISTER_SPACE, 0, &cp->cmd_ioh))
return;
if (bus_space_map(iot, iobase + ide->auxregs[channel],
AUX_REGISTER_SPACE, 0, &cp->ctl_ioh))
return;
icp->ic_irqiot = iot;
if (bus_space_map(iot, iobase + ide->irqregs[channel],
IRQ_REGISTER_SPACE, 0, &icp->ic_irqioh))
return;
/* Disable interrupts */
(void)bus_space_read_1(iot, icp->ic_irqioh, 0);
/* Call common attach routines */
wdcattach(cp);
/* Disable interrupts */
(void)bus_space_read_1(iot, icp->ic_irqioh, 0);
pa->pa_podule->irq_addr = iobase + ide->irqstatregs[channel];
pa->pa_podule->irq_mask = IRQ_STATUS_REGISTER_MASK;
icp->ic_irqaddr = pa->pa_podule->irq_addr;
icp->ic_irqmask = pa->pa_podule->irq_mask;
evcnt_attach_dynamic(&icp->ic_intrcnt, EVCNT_TYPE_INTR, NULL,
self->dv_xname, "intr");
icp->ic_ih = podulebus_irq_establish(pa->pa_ih, IPL_BIO,
icside_intr, icp, &icp->ic_intrcnt);
if (icp->ic_ih == NULL) {
printf("%s: Cannot claim interrupt %d\n",
sc->sc_wdcdev.sc_dev.dv_xname,
pa->pa_podule->interrupt);
continue;
}
/* Enable interrupts */
bus_space_write_1(iot, icp->ic_irqioh, 0, 0);
}
}
/*
* Podule interrupt handler
*
* If the interrupt was from our card pass it on to the wdc interrupt handler
*/
int
icside_intr(arg)
void *arg;
{
struct icside_channel *icp = arg;
volatile u_char *intraddr = (volatile u_char *)icp->ic_irqaddr;
/* XXX - not bus space yet - should really be handled by podulebus */
if ((*intraddr) & icp->ic_irqmask)
wdcintr(&icp->wdc_channel);
return(0);
}

60
sys/arch/arm32/podulebus/icside_io_asm.S
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@ -1,60 +0,0 @@
/* $NetBSD: icside_io_asm.S,v 1.7 1999/10/26 06:53:44 cgd Exp $ */
/*
* Copyright (c) 1997 Mark Brinicombe.
* Copyright (c) 1997 Causality Limited.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Mark Brinicombe
* for the NetBSD Project.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <machine/asm.h>
/*
* Custom bus_space I/O functions for ICS IDE podule
*/
/*
* read multiple
*/
ENTRY(icside_bs_rm_2)
add r0, r1, r2, lsl r0
mov r1, r3
ldr r2, [sp, #0]
b _C_LABEL(inswm8)
/*
* write multiple
*/
ENTRY(icside_bs_wm_2)
add r0, r1, r2, lsl r0
mov r1, r3
ldr r2, [sp, #0]
b _C_LABEL(outswm8)

65
sys/arch/arm32/podulebus/icsidereg.h
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@ -1,65 +0,0 @@
/* $NetBSD: icsidereg.h,v 1.3 1998/09/22 00:40:37 mark Exp $ */
/*
* Copyright (c) 1997 Mark Brinicombe
* Copyright (c) 1997 Causality Limited
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Mark Brinicombe
* for the NetBSD Project.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Registers and address offsets for the ICS IDE card.
*/
/* ID register, read 4 consecutive words and extract ID from bit 0 */
#define ID_REGISTER_OFFSET 0x2280 /* byte offset from fast base */
#define REGISTER_SPACING_SHIFT 6
#define IDE_REGISTER_SPACE 0x200
#define AUX_REGISTER_SPACE 4
#define IRQ_REGISTER_SPACE 4
#define ID_REGISTER_SPACE 4
#define IRQ_STATUS_REGISTER_MASK 0x01
/* IDE drive registers */
/* ARCIN V5 registers */
#define V5_IDE_BASE 0x2800 /* byte offset from base */
#define V5_AUX_BASE 0x2a80 /* byte offset from base */
#define V5_IRQ_BASE 0x0004 /* byte offset from base */
#define V5_IRQSTAT_BASE 0x0000 /* byte offset from base */
/* ARCIN V6 registers */
#define V6_P_IDE_BASE 0x2000 /* byte offset from base */
#define V6_P_AUX_BASE 0x2380 /* byte offset from base */
#define V6_P_IRQ_BASE 0x2200 /* byte offset from base */
#define V6_P_IRQSTAT_BASE 0x2290 /* byte offset from base */
#define V6_S_IDE_BASE 0x3000 /* byte offset from base */
#define V6_S_AUX_BASE 0x3380 /* byte offset from base */
#define V6_S_IRQ_BASE 0x3200 /* byte offset from base */
#define V6_S_IRQSTAT_BASE 0x3290 /* byte offset from base */

1617
sys/arch/arm32/podulebus/if_ie.c
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383
sys/arch/arm32/podulebus/if_iereg.h
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@ -1,383 +0,0 @@
/* $NetBSD: if_iereg.h,v 1.3 1998/03/09 19:12:59 mark Exp $ */
/*
* Copyright (C) 1994 Wolfgang Solfrank.
* Copyright (C) 1994 TooLs GmbH.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by TooLs GmbH.
* 4. The name of TooLs GmbH may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#define IE_PAGE 0
#define IE_CONTROL 1
#define IE_CONT_RESET 1
#define IE_CONT_LOOP 2
#define IE_CONT_ATTN 4
#define IE_CONT_CLI 8
#define IE_MEMSIZE 65536
#define IE_PAGESIZE 4096
#define IE_MEMOFF 0x2000
#define IE_COFF2POFF(off) ((off) % IE_PAGESIZE * 2)
#define IE_COFF2PAGE(off) (((off) % IE_MEMSIZE) / IE_PAGESIZE)
#define IE_ISCP_ADDR (IE_SCP_ADDR - sizeof(struct ie_int_sys_conf_ptr))
#define IE_IBASE (0x1000000 - IE_MEMSIZE)
#define IE_SCB_OFF 0
/*-
* Copyright (c) 1998 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Paul Kranenburg.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*-
* Copyright (c) 1992, University of Vermont and State Agricultural College.
* Copyright (c) 1992, Garrett A. Wollman.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* Vermont and State Agricultural College and Garrett A. Wollman.
* 4. Neither the name of the University nor the name of the author
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE UNIVERSITY OR AUTHOR BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* Intel 82586 Ethernet chip
* Register, bit, and structure definitions.
*
* Written by GAW with reference to the Clarkson Packet Driver code for this
* chip written by Russ Nelson and others.
*/
/*
* NOTE, the structure definitions in here are for reference only.
* We use integer offsets exclusively to access the i82586 data structures.
*/
/*
* OLD i82586.h; REMOVE WHEN ALL DRIVERS HAVE BEEN CONVERTED
*/
struct ie_en_addr {
u_char data[6];
};
/*
* This is the master configuration block. It tells the hardware where all
* the rest of the stuff is.
*/
struct ie_sys_conf_ptr {
u_short mbz; /* must be zero */
u_char ie_bus_use; /* true if 8-bit only */
u_char mbz2[5]; /* must be zero */
caddr_t ie_iscp_ptr; /* 24-bit physaddr of ISCP */
};
/*
* Note that this is wired in hardware; the SCP is always located here, no
* matter what.
*/
#define IE_SCP_ADDR 0xfffff4
/*
* The tells the hardware where all the rest of the stuff is, too.
* FIXME: some of these should be re-commented after we figure out their
* REAL function.
*/
struct ie_int_sys_conf_ptr {
u_char ie_busy; /* zeroed after init */
u_char mbz;
u_short ie_scb_offset; /* 16-bit physaddr of next struct */
caddr_t ie_base; /* 24-bit physaddr for all 16-bit vars */
};
/*
* This FINALLY tells the hardware what to do and where to put it.
*/
struct ie_sys_ctl_block {
u_short ie_status; /* status word */
u_short ie_command; /* command word */
u_short ie_command_list; /* 16-pointer to command block list */
u_short ie_recv_list; /* 16-pointer to receive frame list */
u_short ie_err_crc; /* CRC errors */
u_short ie_err_align; /* Alignment errors */
u_short ie_err_resource; /* Resource errors */
u_short ie_err_overrun; /* Overrun errors */
};
/* Command values */
#define IE_RU_COMMAND 0x0070 /* mask for RU command */
#define IE_RU_NOP 0 /* for completeness */
#define IE_RU_START 0x0010 /* start receive unit command */
#define IE_RU_ENABLE 0x0020 /* enable receiver command */
#define IE_RU_DISABLE 0x0030 /* disable receiver command */
#define IE_RU_ABORT 0x0040 /* abort current receive operation */
#define IE_CU_COMMAND 0x0700 /* mask for CU command */
#define IE_CU_NOP 0 /* included for completeness */
#define IE_CU_START 0x0100 /* do-command command */
#define IE_CU_RESUME 0x0200 /* resume a suspended cmd list */
#define IE_CU_STOP 0x0300 /* SUSPEND was already taken */
#define IE_CU_ABORT 0x0400 /* abort current command */
#define IE_ACK_COMMAND 0xf000 /* mask for ACK command */
#define IE_ACK_CX 0x8000 /* ack IE_ST_CX */
#define IE_ACK_FR 0x4000 /* ack IE_ST_FR */
#define IE_ACK_CNA 0x2000 /* ack IE_ST_CNA */
#define IE_ACK_RNR 0x1000 /* ack IE_ST_RNR */
#define IE_ACTION_COMMAND(x) (((x) & IE_CU_COMMAND) == IE_CU_START)
/* is this command an action command? */
/* Status values */
#define IE_ST_WHENCE 0xf000 /* mask for cause of interrupt */
#define IE_ST_CX 0x8000 /* command with I bit completed */
#define IE_ST_FR 0x4000 /* frame received */
#define IE_ST_CNA 0x2000 /* all commands completed */
#define IE_ST_RNR 0x1000 /* receive not ready */
#define IE_CU_STATUS 0x700 /* mask for command unit status */
#define IE_CU_ACTIVE 0x200 /* command unit is active */
#define IE_CU_SUSPEND 0x100 /* command unit is suspended */
#define IE_RU_STATUS 0x70 /* mask for receiver unit status */
#define IE_RU_SUSPEND 0x10 /* receiver is suspended */
#define IE_RU_NOSPACE 0x20 /* receiver has no resources */
#define IE_RU_READY 0x40 /* reveiver is ready */
/*
* This is filled in partially by the chip, partially by us.
*/
struct ie_recv_frame_desc {
u_short ie_fd_status; /* status for this frame */
u_short ie_fd_last; /* end of frame list flag */
u_short ie_fd_next; /* 16-pointer to next RFD */
u_short ie_fd_buf_desc; /* 16-pointer to list of buffer desc's */
struct ie_en_addr dest; /* destination ether */
struct ie_en_addr src; /* source ether */
u_short ie_length; /* 802 length/Ether type */
u_short mbz; /* must be zero */
};
#define IE_FD_LAST 0x8000 /* last rfd in list */
#define IE_FD_SUSP 0x4000 /* suspend RU after receipt */
#define IE_FD_COMPLETE 0x8000 /* frame is complete */
#define IE_FD_BUSY 0x4000 /* frame is busy */
#define IE_FD_OK 0x2000 /* frame is bad */
#define IE_FD_RNR 0x0200 /* receiver out of resources here */
/*
* linked list of buffers...
*/
struct ie_recv_buf_desc {
u_short ie_rbd_actual; /* status for this buffer */
u_short ie_rbd_next; /* 16-pointer to next RBD */
caddr_t ie_rbd_buffer; /* 24-pointer to buffer for this RBD */
u_short ie_rbd_length; /* length of the buffer */
u_short mbz; /* must be zero */
};
#define IE_RBD_LAST 0x8000 /* last buffer */
#define IE_RBD_USED 0x4000 /* this buffer has data */
/*
* All commands share this in common.
*/
struct ie_cmd_common {
u_short ie_cmd_status; /* status of this command */
u_short ie_cmd_cmd; /* command word */
u_short ie_cmd_link; /* link to next command */
};
#define IE_STAT_COMPL 0x8000 /* command is completed */
#define IE_STAT_BUSY 0x4000 /* command is running now */
#define IE_STAT_OK 0x2000 /* command completed successfully */
#define IE_STAT_ABORT 0x1000 /* command was aborted */
#define IE_CMD_NOP 0x0000 /* NOP */
#define IE_CMD_IASETUP 0x0001 /* initial address setup */
#define IE_CMD_CONFIG 0x0002 /* configure command */
#define IE_CMD_MCAST 0x0003 /* multicast setup command */
#define IE_CMD_XMIT 0x0004 /* transmit command */
#define IE_CMD_TDR 0x0005 /* time-domain reflectometer command */
#define IE_CMD_DUMP 0x0006 /* dump command */
#define IE_CMD_DIAGNOSE 0x0007 /* diagnostics command */
#define IE_CMD_LAST 0x8000 /* this is the last command in the list */
#define IE_CMD_SUSPEND 0x4000 /* suspend CU after this command */
#define IE_CMD_INTR 0x2000 /* post an interrupt after completion */
/*
* This is the command to transmit a frame.
*/
struct ie_xmit_cmd {
struct ie_cmd_common com; /* common part */
#define ie_xmit_status com.ie_cmd_status
u_short ie_xmit_desc; /* 16-pointer to buffer descriptor */
struct ie_en_addr ie_xmit_addr; /* destination address */
u_short ie_xmit_length; /* 802.3 length/Ether type field */
};
#define IE_XS_MAXCOLL 0x000f /* number of collisions during transmit */
#define IE_XS_EXCMAX 0x0020 /* exceeded maximum number of collisions */
#define IE_XS_SQE 0x0040 /* SQE positive */
#define IE_XS_DEFERRED 0x0080 /* transmission deferred */
#define IE_XS_UNDERRUN 0x0100 /* DMA underrun */
#define IE_XS_LOSTCTS 0x0200 /* Lost CTS */
#define IE_XS_NOCARRIER 0x0400 /* No Carrier */
#define IE_XS_LATECOLL 0x0800 /* Late collision */
/*
* This is a buffer descriptor for a frame to be transmitted.
*/
struct ie_xmit_buf {
u_short ie_xmit_flags; /* see below */
u_short ie_xmit_next; /* 16-pointer to next desc. */
caddr_t ie_xmit_buf; /* 24-pointer to the actual buffer */
};
#define IE_XMIT_LAST 0x8000 /* this TBD is the last one */
/* The rest of the `flags' word is actually the length. */
/*
* Multicast setup command.
*/
#define MAXMCAST 250 /* must fit in transmit buffer */
struct ie_mcast_cmd {
struct ie_cmd_common com; /* common part */
#define ie_mcast_status com.ie_cmd_status
u_short ie_mcast_bytes; /* size (in bytes) of multicast addresses */
struct ie_en_addr ie_mcast_addrs[MAXMCAST + 1]; /* space for them */
};
/*
* Time Domain Reflectometer command.
*/
struct ie_tdr_cmd {
struct ie_cmd_common com; /* common part */
#define ie_tdr_status com.ie_cmd_status
u_short ie_tdr_time; /* error bits and time */
};
#define IE_TDR_SUCCESS 0x8000 /* TDR succeeded without error */
#define IE_TDR_XCVR 0x4000 /* detected a transceiver problem */
#define IE_TDR_OPEN 0x2000 /* detected an open */
#define IE_TDR_SHORT 0x1000 /* TDR detected a short */
#define IE_TDR_TIME 0x07ff /* mask for reflection time */
/*
* Initial Address Setup command
*/
struct ie_iasetup_cmd {
struct ie_cmd_common com;
#define ie_iasetup_status com.ie_cmd_status
struct ie_en_addr ie_address;
};
/*
* Configuration command
*/
struct ie_config_cmd {
struct ie_cmd_common com; /* common part */
#define ie_config_status com.ie_cmd_status
u_char ie_config_count; /* byte count (0x0c) */
u_char ie_fifo; /* fifo (8) */
u_char ie_save_bad; /* save bad frames (0x40) */
u_char ie_addr_len; /* address length (0x2e) (AL-LOC == 1) */
u_char ie_priority; /* priority and backoff (0x0) */
u_char ie_ifs; /* inter-frame spacing (0x60) */
u_char ie_slot_low; /* slot time, LSB (0x0) */
u_char ie_slot_high; /* slot time, MSN, and retries (0xf2) */
u_char ie_promisc; /* 1 if promiscuous, else 0 */
u_char ie_crs_cdt; /* CSMA/CD parameters (0x0) */
u_char ie_min_len; /* min frame length (0x40) */
u_char ie_junk; /* stuff for 82596 (0xff) */
};

808
sys/arch/arm32/podulebus/if_ne_pbus.c
View File

@ -1,808 +0,0 @@
/* $NetBSD: if_ne_pbus.c,v 1.10 2001/09/19 22:40:17 reinoud Exp $ */
/*
* Copyright (c) 1998 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Mark Brinicombe of Causality Limited.
*
* EtherH code Copyright (c) 1998 Mike Pumford
* EtherN/EtherI code Copyright (c) 1999 Mike Pumford
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* This driver uses the generic ne2000 & dp8390 IC drivers
*
* Currently supports:
* ANT EtherM network slot cards
* ICubed Etherlan 600 (EtherH) network slot cards
* Irlam EtherN podules
* Acorn EtherI podules (identical hardware to EtherN)
*
* Thanks go to Stephen Borrill for providing the EtherN card
* and information to program it.
*
* TO DO List for this Driver.
*
* EtherM - Needs proper media support.
*/
#include <sys/param.h>
#include <sys/device.h>
#include <sys/socket.h>
#include <sys/systm.h>
#include <sys/mbuf.h>
#include <net/if.h>
#include <net/if_dl.h>
#include <net/if_ether.h>
#include <net/if_media.h>
#include <machine/bus.h>
#include <machine/irqhandler.h>
#include <machine/io.h>
#include <dev/ic/dp8390reg.h>
#include <dev/ic/dp8390var.h>
#include <dev/ic/ne2000reg.h>
#include <dev/ic/ne2000var.h>
#include <arch/arm32/podulebus/podulebus.h>
#include <arch/arm32/podulebus/if_ne_pbusreg.h>
#include <dev/podulebus/podules.h>
/*
* ne_pbus_softc: ne2000_softc plus podule, interrupt and bs tag info
*/
struct ne_pbus_softc {
struct ne2000_softc sc_ne2000; /* ne2000 softc */
int sc_podule_number;
podule_t *sc_podule;
struct bus_space sc_tag; /* Patched tag */
irqhandler_t *sc_ih; /* Interrupt handler */
struct evcnt sc_intrcnt; /* Interrupt count */
bus_space_handle_t sc_extrah; /* Bus handle for any
extra registers */
};
/*
* Attach data and prototypes for driver
*/
static int ne_pbus_probe __P((struct device *, struct cfdata *, void *));
static void ne_pbus_attach __P((struct device *, struct device *, void *));
struct cfattach ne_pbus_ca = {
sizeof(struct ne_pbus_softc), ne_pbus_probe, ne_pbus_attach
};
/*
* Prototypes for interface specific routines
*/
static u_int8_t *em_ea __P((struct ne_pbus_softc *sc, u_int8_t *buffer));
static void em_postattach __P((struct ne_pbus_softc *sc));
static void eh600_postattach __P((struct ne_pbus_softc *sc));
static void eh600_preattach __P((struct ne_pbus_softc *sc));
static u_int8_t *eh600_ea __P((struct ne_pbus_softc *sc, u_int8_t *buffer));
int eh600_mediachange __P((struct dp8390_softc *));
void eh600_mediastatus __P((struct dp8390_softc *, struct ifmediareq *));
void eh600_init_card __P((struct dp8390_softc *));
void eh600_init_media __P((struct dp8390_softc *));
int en_mediachange __P((struct dp8390_softc *));
void en_mediastatus __P((struct dp8390_softc *, struct ifmediareq *));
void en_init_card __P((struct dp8390_softc *));
void en_init_media __P((struct dp8390_softc *));
/*
* Define a structure to hold all the information required on an NE2000
* clone interface.
* We create an array of these structures to describe all the interfaces
* that we can handle via the MI NE2000 driver.
*/
struct ne_clone {
int manufacturer; /* podule manufacturer id */
int product; /* podule product id */
unsigned int cookie; /* podulebus space cookie */
unsigned int nicbase; /* byte offset of NIC */
unsigned int nicsize; /* size of NIC (regs) */
unsigned int asicbase; /* byte offset of ASIC */
unsigned int asicsize; /* size of ASIC (regs) */
unsigned int extrabase; /* extra registers byte offset */
unsigned int extrasize; /* size of extra registers(regs) */
unsigned char nicspace; /* easi,fast or mod space ? */
unsigned char asicspace; /* easi,fast or mod space ? */
unsigned char extraspace; /* easi,fast or mod space ? */
#define NE_SPACE_FAST 0
#define NE_SPACE_MOD 1
#define NE_SPACE_EASI 2
unsigned char reserved0; /* not used (padding) */
const char *name; /* name */
u_int8_t * (*getea) /* do this to get the MAC */
__P((struct ne_pbus_softc *sc, u_int8_t *buffer));
void (*preattach) /* do this before attach */
__P((struct ne_pbus_softc *sc));
void (*postattach) /* do this after attach */
__P((struct ne_pbus_softc *sc));
int (*mediachange) /* media change */
__P((struct dp8390_softc *));
void (*mediastatus) /* media status */
__P((struct dp8390_softc *, struct ifmediareq *));
void (*init_card) /* media init card */
__P((struct dp8390_softc *));
void (*init_media) /* media init */
__P((struct dp8390_softc *));
} ne_clones[] = {
/* ANT EtherM netslot interface */
{
MANUFACTURER_ANT, PODULE_ANT_ETHERM, EM_REGSHIFT,
EM_NIC_OFFSET, EM_NIC_SIZE, EM_ASIC_OFFSET, EM_ASIC_SIZE,
0,0, NE_SPACE_FAST,
NE_SPACE_FAST, NE_SPACE_FAST, 0,
"EtherM", em_ea, NULL, em_postattach,
NULL,NULL,NULL,NULL
},
/* ICubed EtherLan EtherH netslot interface */
{
MANUFACTURER_ICUBED, PODULE_ICUBED_ETHERLAN600, EH600_REGSHIFT,
EH600_NIC_OFFSET, EH600_NIC_SIZE, EH600_ASIC_OFFSET, EH600_ASIC_SIZE,
EH600_CONTROL_OFFSET, EH600_CONTROL_SIZE, NE_SPACE_FAST,
NE_SPACE_FAST, NE_SPACE_FAST, 0,
"EtherLan 600", eh600_ea, eh600_preattach, eh600_postattach,
eh600_mediachange, eh600_mediastatus, eh600_init_card,
eh600_init_media
},
/* Acorn EtherLan EtherH netslot interface */
{
MANUFACTURER_ICUBED, PODULE_ICUBED_ETHERLAN600AEH, EH600_REGSHIFT,
EH600_NIC_OFFSET, EH600_NIC_SIZE, EH600_ASIC_OFFSET, EH600_ASIC_SIZE,
EH600_CONTROL_OFFSET, EH600_CONTROL_SIZE, NE_SPACE_FAST,
NE_SPACE_FAST, NE_SPACE_FAST, 0,
"EtherLan 600A", eh600_ea , eh600_preattach, eh600_postattach,
eh600_mediachange, eh600_mediastatus, eh600_init_card,
eh600_init_media
},
/* Irlam EtherN podule. (supplied with NC) */
{
MANUFACTURER_IRLAM ,PODULE_IRLAM_ETHERN ,EN_REGSHIFT,
EN_NIC_OFFSET, EN_NIC_SIZE, EN_ASIC_OFFSET, EN_ASIC_SIZE,
0,0, NE_SPACE_EASI,
NE_SPACE_EASI, NE_SPACE_EASI, 0,
"EtherN", em_ea, NULL ,NULL,
en_mediachange, en_mediastatus, en_init_card,
en_init_media
},
/* Acorn EtherI podule. (supplied with NC) */
{
MANUFACTURER_ACORN ,PODULE_ACORN_ETHERI ,EN_REGSHIFT,
EN_NIC_OFFSET, EN_NIC_SIZE, EN_ASIC_OFFSET, EN_ASIC_SIZE,
0,0, NE_SPACE_EASI,
NE_SPACE_EASI, NE_SPACE_EASI, 0,
"EtherI", em_ea, NULL ,NULL,
en_mediachange, en_mediastatus, en_init_card,
en_init_media
},
};
/*
* Determine if the device is present.
*/
static int
ne_pbus_probe(parent, cf, aux)
struct device *parent;
struct cfdata *cf;
void *aux;
{
struct podule_attach_args *pa = (void *) aux;
int loop;
/* Scan the list of known interfaces looking for a match */
for (loop = 0; loop < sizeof(ne_clones) / sizeof(struct ne_clone);
++loop) {
if (matchpodule(pa, ne_clones[loop].manufacturer,
ne_clones[loop].product, 0) != 0)
return(1);
}
return(0);
}
/*
* Install interface into kernel networking data structures.
*/
static void
ne_pbus_attach(parent, self, aux)
struct device *parent, *self;
void *aux;
{
struct podule_attach_args *pa = (void *)aux;
struct ne_pbus_softc *npsc = (void *)self;
struct ne2000_softc *nsc = &npsc->sc_ne2000;
struct dp8390_softc *dsc = &nsc->sc_dp8390;
int *media, nmedia, defmedia;
struct ne_clone *ne = NULL;
u_int8_t buffer[6];
u_int8_t *myea;
int loop;
media = NULL;
nmedia = defmedia = 0;
/* Check a few things about the attach args */
if (pa->pa_podule_number == -1)
panic("Podule has disappeared !");
npsc->sc_podule_number = pa->pa_podule_number;
npsc->sc_podule = pa->pa_podule;
podules[npsc->sc_podule_number].attached = 1; /* XXX */
/* Scan the list of known interfaces for a match */
for (loop = 0; loop < sizeof(ne_clones) / sizeof(struct ne_clone);
++loop) {
if (IS_PODULE(pa, ne_clones[loop].manufacturer,
ne_clones[loop].product)) {
ne = &ne_clones[loop];
break;
}
}
#ifdef DIAGNOSTIC
/* This should never fail as we must have matched at probe time */
if (ne == NULL)
panic("Podule has vanished\n");
#endif
/* Update the nic and asic base addresses appropriately */
switch (ne->nicspace) {
case NE_SPACE_EASI:
ne->nicbase += npsc->sc_podule->easi_base;
break;
case NE_SPACE_MOD:
ne->nicbase += npsc->sc_podule->mod_base;
break;
case NE_SPACE_FAST:
default:
ne->nicbase += npsc->sc_podule->fast_base;
break;
}
switch (ne->asicspace) {
case NE_SPACE_EASI:
ne->asicbase += npsc->sc_podule->easi_base;
break;
case NE_SPACE_MOD:
ne->asicbase += npsc->sc_podule->mod_base;
break;
case NE_SPACE_FAST:
default:
ne->asicbase += npsc->sc_podule->fast_base;
break;
}
switch (ne->extraspace) {
case NE_SPACE_EASI:
ne->extrabase += npsc->sc_podule->easi_base;
break;
case NE_SPACE_MOD:
ne->extrabase += npsc->sc_podule->mod_base;
break;
case NE_SPACE_FAST:
default:
ne->extrabase += npsc->sc_podule->fast_base;
break;
}
/* Report the interface name */
printf(": %s ethernet\n", ne->name);
/*
* Ok we need our own bus tag as the register spacing
* may not the default.
*
* For the podulebus, the bus tag cookie is the shift
* to apply to registers
* So duplicate the bus space tag and change the
* cookie.
*/
npsc->sc_tag = *pa->pa_iot;
npsc->sc_tag.bs_cookie = (void *) ne->cookie;
dsc->sc_regt = &npsc->sc_tag;
nsc->sc_asict = dsc->sc_regt;
/* Map all the I/O space for the NIC */
if (bus_space_map(dsc->sc_regt, ne->nicbase, ne->nicsize,
0, &dsc->sc_regh)) {
printf("%s: cannot map i/o space\n", dsc->sc_dev.dv_xname);
return;
}
/* Map the I/O space for the ASIC */
if (bus_space_map(nsc->sc_asict, ne->asicbase, ne->asicsize,
0, &nsc->sc_asich)) {
printf("%s: cannot map i/o space\n", dsc->sc_dev.dv_xname);
return;
}
/* Map any extra register space required by the card */
if (ne->extrasize > 0) {
if (bus_space_map(&npsc->sc_tag, ne->extrabase, ne->extrasize,
0, &npsc->sc_extrah)) {
printf("%s: cannot map extra space\n",
dsc->sc_dev.dv_xname);
return;
}
}
/* This interface is always enabled. */
dsc->sc_enabled = 1;
/*
* Now get the ethernet address in an interface specific manner if
* specified
*/
if (ne->getea)
myea = ne->getea(npsc, buffer);
else
myea = NULL;
/* Does the interface need a preattach call ? */
if (ne->preattach)
ne->preattach(npsc);
/* if the interface has media support initialise it */
if (ne->init_media) {
dsc->sc_mediachange = ne->mediachange;
dsc->sc_mediastatus = ne->mediastatus;
dsc->init_card = ne->init_card;
dsc->sc_media_init = ne->init_media;
/* ne->init_media(dsc,&media,&nmedia,&defmedia); */
}
/*
* Do generic NE2000 attach. This will read the station address
* from the EEPROM.
*/
ne2000_attach(nsc, myea);
printf("%s: ", dsc->sc_dev.dv_xname);
switch (nsc->sc_type) {
case NE2000_TYPE_NE1000:
printf("NE1000");
break;
case NE2000_TYPE_NE2000:
printf("NE2000");
break;
case NE2000_TYPE_AX88190:
printf("AX88190");
break;
case NE2000_TYPE_DL10019:
printf("DL10019");
break;
case NE2000_TYPE_DL10022:
printf("DL10022");
break;
default:
printf("??");
};
printf(" chipset, %d Kb memory\n", dsc->mem_start/1024);
/* Does the interface need a postattach call ? */
if (ne->postattach)
ne->postattach(npsc);
/* Install an interrupt handler */
evcnt_attach_dynamic(&npsc->sc_intrcnt, EVCNT_TYPE_INTR, NULL,
self->dv_xname, "intr");
npsc->sc_ih = podulebus_irq_establish(pa->pa_ih, IPL_NET, dp8390_intr,
dsc, &npsc->sc_intrcnt);
if (npsc->sc_ih == NULL)
panic("%s: Cannot install interrupt handler",
dsc->sc_dev.dv_xname);
/* this feels wrong to do this here */
npsc->sc_ih->ih_maskaddr = npsc->sc_podule->irq_addr;
npsc->sc_ih->ih_maskbits = npsc->sc_podule->irq_mask;
}
/*
* em_ea()
*
* return the ethernet address for an EtherM netslot interface.
* The EtherM interface uses the machines ethernet address so just
* fill it out
*/
static u_int8_t *
em_ea(sc, buffer)
struct ne_pbus_softc *sc;
u_int8_t *buffer;
{
/*
* Use the podulebus netslot_ea() function to get the netslot
* ethernet address. This is generated from the machine ID.
*/
netslot_ea(buffer);
return(buffer);
}
/*
* em_postattach()
*
* The EtherM interface has a Diagnostic Status register. After attaching
* the driver, print out some more information using this register.
*/
static void
em_postattach(sc)
struct ne_pbus_softc *sc;
{
int dsr;
/*
* Report information from the Diagnostic Status Register for
* the EtherM card
*/
printf("%s: 16KB buffer memory",
sc->sc_ne2000.sc_dp8390.sc_dev.dv_xname);
/* Get the Diagnostic Status Register */
dsr = bus_space_read_1(sc->sc_ne2000.sc_asict,
sc->sc_ne2000.sc_asich, EM_DSR_REG);
/* Check for bits that indicate a fault */
if (!(dsr & EM_DSR_20M))
printf(", VCO faulty");
if (!(dsr & EM_DSR_TCOK))
printf(", TxClk faulty");
/* Report status of card */
if (dsr & EM_DSR_POL)
printf(", UTP reverse polarity");
if (dsr & EM_DSR_JAB)
printf(", jabber");
if (dsr & EM_DSR_LNK)
printf(", link OK");
if (dsr & EM_DSR_LBK)
printf(", loopback");
if (dsr & EM_DSR_UTP)
printf(", UTP");
printf("\n");
}
/*
* eh600_preattach()
*
* pre-initialise the AT/Lantic chipset so that the card probes and
* detects properly.
*/
static void
eh600_preattach(sc)
struct ne_pbus_softc *sc;
{
u_char tmp;
struct ne2000_softc *nsc = &sc->sc_ne2000;
struct dp8390_softc *dsc = &nsc->sc_dp8390;
bus_space_tag_t nict = dsc->sc_regt;
bus_space_handle_t nich = dsc->sc_regh;
/* initialise EH600 config register */
bus_space_read_1(nict, nich, EH600_MCRA);
bus_space_write_1(nict,nich,EH600_MCRA,0x18);
/* enable interrupts for the card */
tmp = bus_space_read_1(&sc->sc_tag,sc->sc_extrah,0);
tmp |= EH_INTR_MASK;
bus_space_write_1(&sc->sc_tag,sc->sc_extrah,0,tmp);
}
/*
* eh600_postattach()
*
* Etherlan 600 has 32k of buffer memory as it runs the AT/Lantic
* DP8390 clone in IO non-compatible mode. We need to adjust the memory
* description set up by dp8390.c and ne2000.c to reflect this.
*/
static void
eh600_postattach(sc)
struct ne_pbus_softc *sc;
{
struct ne2000_softc *nsc = &sc->sc_ne2000;
struct dp8390_softc *dsc = &nsc->sc_dp8390;
/* first page is mapped to the PROM. so start at 2nd page */
dsc->mem_start = EH600_MEM_START;
dsc->mem_size = EH600_MEM_END - EH600_MEM_START;
dsc->mem_end = EH600_MEM_END;
dsc->txb_cnt = 3; /* >16k of ram setup 3 tx buffers */
/* recompute the mem ring (taken straight from the ne2000 init code) */
dsc->mem_ring =
dsc->mem_start +
(((dsc->txb_cnt + 1) * ED_TXBUF_SIZE ) <<
ED_PAGE_SHIFT);
/* recompute the dp8390 register values. (from dp8390 init code) */
dsc->tx_page_start = dsc->mem_start >> ED_PAGE_SHIFT;
dsc->rec_page_start = dsc->tx_page_start +
(dsc->txb_cnt + 1) * ED_TXBUF_SIZE;
dsc->rec_page_stop = dsc->tx_page_start +
(dsc->mem_size >> ED_PAGE_SHIFT);
printf("%s: 32KB buffer memory\n", dsc->sc_dev.dv_xname);
}
/*
* EtherLan 600 media.
*/
void eh600_init_media(sc)
struct dp8390_softc *sc;
{
static int eh600_media[] = {
IFM_ETHER|IFM_AUTO,
IFM_ETHER|IFM_10_T,
IFM_ETHER|IFM_10_2,
};
int i, defmedia = IFM_ETHER|IFM_AUTO;
static const int eh600_nmedia =
sizeof(eh600_media) / sizeof(eh600_media[0]);
printf("%s: 10base2, 10baseT, auto, default auto\n",
sc->sc_dev.dv_xname);
ifmedia_init(&sc->sc_media, 0, dp8390_mediachange, dp8390_mediastatus);
for (i = 0; i < eh600_nmedia; i++)
ifmedia_add(&sc->sc_media, eh600_media[i], 0, NULL);
ifmedia_set(&sc->sc_media, defmedia);
}
void eh600_init_card(sc)
struct dp8390_softc *sc;
{
struct ifmedia *ifm = &sc->sc_media;
bus_space_tag_t nict = sc->sc_regt;
bus_space_handle_t nich = sc->sc_regh;
u_int8_t reg;
/* Set basic media type. */
switch (IFM_SUBTYPE(ifm->ifm_cur->ifm_media)) {
case IFM_AUTO:
/* software auto detect the media */
reg = bus_space_read_1(nict, nich, EH600_MCRB);
reg = (reg & 0xf8) | EH600_10BTSEL;
bus_space_write_1(nict, nich, EH600_MCRB, reg);
reg = bus_space_read_1(nict, nich, EH600_MCRB);
if ((reg & 0x04) != 0x04) {
/* No UTP use BNC */
reg = (reg & 0xf8) | EH600_10B2SEL;
bus_space_write_1(nict, nich, EH600_MCRB, reg);
}
break;
case IFM_10_T:
reg = bus_space_read_1(nict, nich, EH600_MCRB);
reg = (reg & 0xf8) | EH600_10BTSEL;
bus_space_write_1(nict, nich, EH600_MCRB, reg);
/* seems that re-reading config B here is required to
* prevent the interface hanging when manually selecting.
*/
bus_space_read_1(nict, nich, EH600_MCRB);
break;
case IFM_10_2:
reg = bus_space_read_1(nict, nich, EH600_MCRB);
reg = (reg & 0xf8) | EH600_10B2SEL;
bus_space_write_1(nict, nich, EH600_MCRB,reg);
/* seems that re-reading config B here is required to
* prevent the interface hanging when manually selecting.
*/
bus_space_read_1(nict, nich, EH600_MCRB);
break;
}
}
int
eh600_mediachange(dsc)
struct dp8390_softc *dsc;
{
/* media is already set up. Interface reset will invoke new
* new media setting. */
dp8390_reset(dsc);
return (0);
}
void
eh600_mediastatus(sc, ifmr)
struct dp8390_softc *sc;
struct ifmediareq *ifmr;
{
bus_space_tag_t nict = sc->sc_regt;
bus_space_handle_t nich = sc->sc_regh;
u_int8_t reg;
reg = bus_space_read_1(nict, nich, EH600_MCRB);
if ((reg & 0x3) == 1) {
ifmr->ifm_active = IFM_ETHER|IFM_10_2;
}
else {
ifmr->ifm_active = IFM_ETHER|IFM_10_T;
}
}
/*
* EtherN media.
*/
void
en_init_media(sc)
struct dp8390_softc *sc;
{
static int en_media[] = {
IFM_ETHER|IFM_10_T
};
printf("%s: 10baseT, default 10baseT\n",
sc->sc_dev.dv_xname);
ifmedia_init(&sc->sc_media, 0, dp8390_mediachange, dp8390_mediastatus);
ifmedia_add(&sc->sc_media, en_media[0], 0, NULL);
ifmedia_set(&sc->sc_media, en_media[0]);
}
void
en_init_card(sc)
struct dp8390_softc *sc;
{
}
int
en_mediachange(dsc)
struct dp8390_softc *dsc;
{
/* media is static so any change is invalid. */
return (EINVAL);
}
void
en_mediastatus(sc, ifmr)
struct dp8390_softc *sc;
struct ifmediareq *ifmr;
{
ifmr->ifm_active = IFM_ETHER|IFM_10_T;
}
/*
* extracts the station address from the Podule description string.
* The description has to be re-read here since the podule description
* string is not always long enough to contain the full address.
*
* If for any reason we cannot extract the address this routine will
* use netslot_ea() to return the generic address for the network slot.
*/
#define POD_READ(addr) \
podule->read_rom(podule->sync_base, addr)
static u_int8_t *
eh600_ea(sc, buffer)
struct ne_pbus_softc *sc;
u_int8_t *buffer;
{
podule_t *podule = sc->sc_podule;
u_int address;
u_int id;
address = 0x40;
memset(buffer, 0, 6);
/* read chunks from the podule */
do {
id = POD_READ(address);
/* check for description chunk. */
if (id == 0xf5) {
u_int size;
u_int pod_addr;
int loop;
/* read the size */
size = POD_READ(address + 4);
size |= (POD_READ(address + 8) << 8);
size |= (POD_READ(address + 12) << 16);
/* read address of description */
pod_addr = POD_READ(address + 16);
pod_addr |= (POD_READ(address + 20) << 8);
pod_addr |= (POD_READ(address + 24) << 16);
pod_addr |= (POD_READ(address + 28) << 24);
if (pod_addr < 0x800) {
u_int8_t tmp;
int addr_index = 0;
int found_ether = 0;
/*
* start scanning for ethernet address
* which starts with a '('
*/
for (loop = 0; loop < size; ++loop) {
if (found_ether) {
/* we have found a '(' so start decoding the address */
tmp = POD_READ((pod_addr + loop) * 4);
if (tmp >= '0' && tmp <= '9') {
buffer[addr_index >> 1] |= (tmp - '0') << ((addr_index & 1) ? 0 : 4);
++addr_index;
}
else if (tmp >= 'a' && tmp <= 'f'){
buffer[addr_index >> 1] |= (10 + (tmp - 'a')) << ((addr_index & 1) ? 0 : 4);
++addr_index;
}
else if (tmp >= 'A' && tmp <= 'F'){
buffer[addr_index >> 1] |= (10 + (tmp - 'A')) << ((addr_index & 1) ? 0 : 4);
++addr_index;
}
else if (tmp == ')') {
/* we have read the whole address so we can stop scanning
* the podule description */
break;
}
}
/*
* we have found the start of the ethernet address (decode begins
* on the next run round the loop. */
if (POD_READ((pod_addr + loop) * 4) == '(') {
found_ether = 1;
}
}
/*
* Failed to find the address so fall back
* on the netslot address
*/
if (!found_ether)
netslot_ea(buffer);
return(buffer);
}
}
address += 32;
} while (id != 0 && address < 0x8000);
/*
* If we get here we failed to find the address
* In this case the best solution is to go with the netslot addrness
*/
netslot_ea(buffer);
return(buffer);
}

92
sys/arch/arm32/podulebus/if_ne_pbusreg.h
View File

@ -1,92 +0,0 @@
/* $NetBSD: if_ne_pbusreg.h,v 1.2 2001/03/31 15:32:46 chris Exp $ */
/*
* Copyright (c) 1998 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Mark Brinicombe of Causality Limited.
*
* EtherH code Copyright (c) 1998 Mike Pumford
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* Register definitions for podulebus hosted ne2000 ethernet controllers
*/
/* EtherM netslot cards */
#define EM_NIC_OFFSET 0x0800
#define EM_NIC_SIZE (NE2000_NIC_NPORTS << EM_REGSHIFT)
#define EM_ASIC_OFFSET (EM_NIC_OFFSET + (NE2000_ASIC_OFFSET << EM_REGSHIFT))
#define EM_ASIC_SIZE (NE2000_ASIC_NPORTS << EM_REGSHIFT)
#define EM_REGSHIFT 5
/* EtherM interface has a special Diagnostic status register */
#define EM_DSR_REG 0x0d /* Register number from ASIC base */
/* Diagnostic status register */
#define EM_DSR_20M (1 << 1) /* 20MHz VCO functioning */
#define EM_DSR_TCOK (1 << 2) /* Transmit clock functioning */
#define EM_DSR_POL (1 << 3) /* Polarity of UTP link */
#define EM_DSR_JAB (1 << 4) /* Jabber state */
#define EM_DSR_LNK (1 << 5) /* Link state */
#define EM_DSR_LBK (1 << 6) /* Lookback mode */
#define EM_DSR_UTP (1 << 7) /* Twisted pair selected */
/* EtherLan 600 definitions */
#define EH600_CONTROL_OFFSET 0x0a00
#define EH600_CONTROL_SIZE (1 << EH600_REGSHIFT)
#define EH600_NIC_OFFSET 0x0800
#define EH600_NIC_SIZE (NE2000_NIC_NPORTS << EH600_REGSHIFT)
#define EH600_ASIC_OFFSET (EH600_NIC_OFFSET + (NE2000_ASIC_OFFSET \
<< EH600_REGSHIFT))
#define EH600_ASIC_SIZE (NE2000_ASIC_NPORTS << EH600_REGSHIFT)
#define EH600_REGSHIFT 2
#define EH600_MCRA 0x0a /* master control reg A */
#define EH600_MCRB 0x0b /* master control reg B */
#define EH600_10BTSEL 0 /* 10BaseT interface */
#define EH600_10B2SEL 1 /* 10Base2 interface */
#define EH600_MEM_START 0x100 /* buffer ram start */
#define EH600_MEM_END 0x8000 /* buffer ram end */
/* Acorn EtherN registers */
#define EN_REGSHIFT 3
#define EN_NIC_OFFSET 0x400000
#define EN_NIC_SIZE (NE2000_NIC_NPORTS << EN_REGSHIFT)
#define EN_ASIC_OFFSET (EN_NIC_OFFSET + (NE2000_ASIC_OFFSET \
<< EN_REGSHIFT))
#define EN_ASIC_SIZE (NE2000_ASIC_NPORTS << EN_REGSHIFT)
/* Etherlan 600 control register */
/*Write only */
#define EH_INTR_MASK (1 << 0) /* Interrupt Mask. */
#define EH_ID_CONTROL (1 << 1) /* ID control. */
/* Read only */
#define EH_INTR_STAT (1 << 0) /* Interrupt status. */

161
sys/arch/arm32/podulebus/netslot.c
View File

@ -1,161 +0,0 @@
/* $NetBSD: netslot.c,v 1.1 2001/07/02 23:18:36 bjh21 Exp $ */
/*
* Copyright (c) 1994-1996 Mark Brinicombe.
* Copyright (c) 1994 Brini.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Brini.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/param.h>
__KERNEL_RCSID(1, "$Id: netslot.c,v 1.1 2001/07/02 23:18:36 bjh21 Exp $");
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/conf.h>
#include <sys/malloc.h>
#include <sys/device.h>
#include <uvm/uvm_extern.h>
#include <machine/io.h>
#include <machine/katelib.h>
#include <machine/irqhandler.h>
#include <machine/bootconfig.h>
#include <machine/pte.h>
#include <machine/pmap.h>
#include <arm32/iomd/iomdreg.h>
#include <arm32/iomd/iomdvar.h>
#include <dev/podulebus/podulebus.h>
#include <dev/podulebus/podules.h>
u_int netslotread __P((u_int, int));
u_int
netslotread(address, offset)
u_int address;
int offset;
{
static int netslotoffset = -1;
offset = offset >> 2;
if (netslotoffset == -1 || offset < netslotoffset) {
WriteByte(address, 0);
netslotoffset = 0;
}
while (netslotoffset < offset) {
(void)ReadByte(address);
++netslotoffset;
}
++netslotoffset;
return(ReadByte(address));
}
void
netslotscan(dev)
struct device *dev;
{
podule_t *podule;
volatile u_char *address;
/* Only one netslot atm */
/* Reset the address counter */
WriteByte(NETSLOT_BASE, 0x00);
address = (u_char *)NETSLOT_BASE;
podule = &podules[MAX_PODULES];
podule->fast_base = NETSLOT_BASE;
podule->medium_base = NETSLOT_BASE;
podule->slow_base = NETSLOT_BASE;
podule->sync_base = NETSLOT_BASE;
podule->mod_base = NETSLOT_BASE;
podule->easi_base = 0;
podule->attached = 0;
podule->slottype = SLOT_NONE;
podule->podulenum = MAX_PODULES;
podule->interrupt = IRQ_NETSLOT;
podule->read_rom = netslotread;
podule->dma_channel = -1;
podule->dma_interrupt = -1;
podule->description[0] = 0;
/* XXX - Really needs to be linked to a DMA manager */
if (IOMD_ID == RPC600_IOMD_ID)
podule->dma_channel = 0;
/* Get information from the podule header */
podule->flags0 = *address;
podule->flags1 = *address;
podule->reserved = *address;
podule->product = *address;
podule->product += (*address << 8);
podule->manufacturer = *address;
podule->manufacturer += (*address << 8);
podule->country = *address;
if (podule->flags1 & PODULE_FLAGS_IS) {
podule->irq_mask = *address;
podule->irq_addr = *address;
podule->irq_addr += (*address << 8);
podule->irq_addr += (*address << 16);
podule->irq_addr += podule->slow_base;
if (podule->irq_mask == 0)
podule->irq_mask = 0x01;
podule->fiq_mask = *address;
podule->fiq_addr = *address;
podule->fiq_addr += (*address << 8);
podule->fiq_addr += (*address << 16);
podule->fiq_addr += podule->slow_base;
if (podule->fiq_mask == 0)
podule->fiq_mask = 0x04;
} else {
podule->irq_addr = podule->slow_base;
podule->irq_mask = 0x01;
podule->fiq_addr = podule->slow_base;
podule->fiq_mask = 0x04;
}
poduleexamine(podule, dev, SLOT_NET);
}
void
netslot_ea(buffer)
u_int8_t *buffer;
{
/* Build station address from machine ID */
buffer[0] = 0x00;
buffer[1] = 0x00;
buffer[2] = 0xa4;
buffer[3] = bootconfig.machine_id[2] + 0x10;
buffer[4] = bootconfig.machine_id[1];
buffer[5] = bootconfig.machine_id[0];
}

628
sys/arch/arm32/podulebus/podulebus.c
View File

@ -1,628 +0,0 @@
/* $NetBSD: podulebus.c,v 1.49 2001/07/28 18:12:45 chris Exp $ */
/*
* Copyright (c) 1994-1996 Mark Brinicombe.
* Copyright (c) 1994 Brini.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Brini.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RiscBSD kernel project
*
* podulebus.c
*
* Podule probe and configuration routines
*
* Created : 07/11/94
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/conf.h>
#include <sys/malloc.h>
#include <sys/device.h>
#include <uvm/uvm_extern.h>
#include <machine/io.h>
#include <machine/katelib.h>
#include <machine/irqhandler.h>
#include <machine/bootconfig.h>
#include <machine/pte.h>
#include <machine/pmap.h>
#include <arm32/iomd/iomdreg.h>
#include <arm32/iomd/iomdvar.h>
#include <arm32/podulebus/podulebus.h>
#include <dev/podulebus/podules.h>
#include <dev/podulebus/podule_data.h>
#include "locators.h"
/* Array of podule structures, one per possible podule */
podule_t podules[MAX_PODULES + MAX_NETSLOTS];
extern struct bus_space podulebus_bs_tag;
/* Declare prototypes */
void map_section __P((vm_offset_t, vm_offset_t, vm_offset_t, int cacheable));
u_int poduleread __P((u_int, int));
/*
* int podulebusmatch(struct device *parent, void *match, void *aux)
*
* Probe for the podule bus. Currently all this does is return 1 to
* indicate that the podule bus was found.
*/
int
podulebusmatch(parent, cf, aux)
struct device *parent;
struct cfdata *cf;
void *aux;
{
switch (IOMD_ID) {
case RPC600_IOMD_ID:
case ARM7500_IOC_ID:
case ARM7500FE_IOC_ID:
return(1);
}
return (0);
}
int
podulebusprint(aux, name)
void *aux;
const char *name;
{
struct podule_attach_args *pa = aux;
if (name)
printf("podule at %s", name);
if (pa->pa_podule->slottype == SLOT_POD)
printf(" slot %d", pa->pa_podule_number);
else if (pa->pa_podule->slottype == SLOT_NET)
printf(" [ netslot %d ]", pa->pa_podule_number - MAX_PODULES);
#ifdef DIAGNOSTIC
else
panic("Invalid slot type\n");
#endif
return (UNCONF);
}
int
podulebussubmatch(parent, match, aux)
struct device *parent;
void *match;
void *aux;
{
struct cfdata *cf = match;
struct podule_attach_args *pa = aux;
/* Return priority 0 or 1 for wildcarded podule */
if (cf->cf_loc[PODULEBUSCF_SLOT] == PODULEBUSCF_SLOT_DEFAULT)
return((*cf->cf_attach->ca_match)(parent, match, aux));
/* Return higher priority if we match the specific podule */
else if (cf->cf_loc[PODULEBUSCF_SLOT] == pa->pa_podule_number)
return((*cf->cf_attach->ca_match)(parent, match, aux) * 8);
/* Fail */
return(0);
}
#if 0
void
dump_podule(podule)
podule_t *podule;
{
printf("podule%d: ", podule->podulenum);
printf("flags0=%02x ", podule->flags0);
printf("flags1=%02x ", podule->flags1);
printf("reserved=%02x ", podule->reserved);
printf("product=%02x ", podule->product);
printf("manufacturer=%02x ", podule->manufacturer);
printf("country=%02x ", podule->country);
printf("irq_addr=%08x ", podule->irq_addr);
printf("irq_mask=%02x ", podule->irq_mask);
printf("fiq_addr=%08x ", podule->fiq_addr);
printf("fiq_mask=%02x ", podule->fiq_mask);
printf("fast_base=%08x ", podule->fast_base);
printf("medium_base=%08x ", podule->medium_base);
printf("slow_base=%08x ", podule->slow_base);
printf("sync_base=%08x ", podule->sync_base);
printf("mod_base=%08x ", podule->mod_base);
printf("easi_base=%08x ", podule->easi_base);
printf("attached=%d ", podule->attached);
printf("slottype=%d ", podule->slottype);
printf("podulenum=%d ", podule->podulenum);
printf("description=%s ", podule->description);
printf("\n");
}
#endif
void
podulechunkdirectory(podule)
podule_t *podule;
{
u_int address;
u_int id;
u_int size;
u_int addr;
int loop;
int done_f5;
done_f5 = 0;
address = 0x40;
do {
id = podule->read_rom(podule->sync_base, address);
size = podule->read_rom(podule->sync_base, address + 4);
size |= (podule->read_rom(podule->sync_base, address + 8) << 8);
size |= (podule->read_rom(podule->sync_base, address + 12) << 16);
if (id == 0xf5) {
addr = podule->read_rom(podule->sync_base, address + 16);
addr |= (podule->read_rom(podule->sync_base, address + 20) << 8);
addr |= (podule->read_rom(podule->sync_base, address + 24) << 16);
addr |= (podule->read_rom(podule->sync_base, address + 28) << 24);
if (addr < 0x800 && done_f5 == 0) {
done_f5 = 1;
for (loop = 0; loop < size; ++loop) {
if (loop < PODULE_DESCRIPTION_LENGTH) {
podule->description[loop] =
podule->read_rom(podule->sync_base, (addr + loop)*4);
podule->description[loop + 1] = 0;
}
}
}
}
#ifdef DEBUG_CHUNK_DIR
if (id == 0xf5 || id == 0xf1 || id == 0xf2 || id == 0xf3 || id == 0xf4 || id == 0xf6) {
addr = podule->read_rom(podule->sync_base, address + 16);
addr |= (podule->read_rom(podule->sync_base, address + 20) << 8);
addr |= (podule->read_rom(podule->sync_base, address + 24) << 16);
addr |= (podule->read_rom(podule->sync_base, address + 28) << 24);
printf("<%04x.%04x.%04x.%04x>", id, address, addr, size);
if (addr < 0x800) {
for (loop = 0; loop < size; ++loop) {
printf("%c", podule->read_rom(podule->sync_base, (addr + loop)*4));
}
printf("\\n\n");
}
}
#endif
address += 32;
} while (id != 0 && address < 0x800);
}
void
poduleexamine(podule, dev, slottype)
podule_t *podule;
struct device *dev;
int slottype;
{
struct podule_list *pod_list;
struct podule_description *pod_desc;
/* Test to see if the podule is present */
if ((podule->flags0 & 0x02) == 0x00) {
podule->slottype = slottype;
if (slottype == SLOT_NET)
printf("netslot%d at %s : ", podule->podulenum - MAX_PODULES,
dev->dv_xname);
else
printf("podule%d at %s : ", podule->podulenum,
dev->dv_xname);
/* Is it Acorn conformant ? */
if (podule->flags0 & 0x80)
printf("Non-Acorn conformant expansion card\n");
else {
int id;
/* Is it a simple podule ? */
id = (podule->flags0 >> 3) & 0x0f;
if (id != 0)
printf("Simple expansion card <%x>\n", id);
else {
/* Scan the chunk directory if present for tags we use */
if (podule->flags1 & PODULE_FLAGS_CD)
podulechunkdirectory(podule);
/* Do we know this manufacturer ? */
pod_list = known_podules;
while (pod_list->description) {
if (pod_list->manufacturer_id == podule->manufacturer)
break;
++pod_list;
}
if (!pod_list->description)
printf("man=%04x : ", podule->manufacturer);
else
printf("%s : ", pod_list->description);
/* Do we know this product ? */
pod_desc = pod_list->products;
while (pod_desc->description) {
if (pod_desc->product_id == podule->product)
break;
++pod_desc;
}
if (!pod_desc->description) {
printf("prod=%04x : ", podule->product);
printf("%s\n", podule->description);
} else
printf("%s : %s\n", pod_desc->description, podule->description);
}
}
}
}
u_int
poduleread(address, offset)
u_int address;
int offset;
{
return(ReadByte(address + offset));
}
void
podulescan(dev)
struct device *dev;
{
int loop;
podule_t *podule;
u_char *address;
u_int offset = 0;
/* Loop round all the podules */
for (loop = 0; loop < MAX_PODULES; ++loop, offset += SIMPLE_PODULE_SIZE) {
podule = &podules[loop];
podule->podulenum = loop;
podule->attached = 0;
podule->slottype = SLOT_NONE;
podule->interrupt = IRQ_PODULE;
podule->read_rom = poduleread;
podule->dma_channel = -1;
podule->dma_interrupt = -1;
podule->description[0] = 0;
if (loop == 4) offset += PODULE_GAP;
address = ((u_char *)SYNC_PODULE_BASE) + offset;
if ((address[0] & 0x02) == 0x00) {
podule->fast_base = FAST_PODULE_BASE + offset;
podule->medium_base = MEDIUM_PODULE_BASE + offset;
podule->slow_base = SLOW_PODULE_BASE + offset;
podule->sync_base = SYNC_PODULE_BASE + offset;
podule->mod_base = MOD_PODULE_BASE + offset;
podule->easi_base = EASI_BASE + loop * EASI_SIZE;
} else {
address = ((u_char *)EASI_BASE) + loop * EASI_SIZE;
if ((address[0] & 0x02) != 0x00)
continue;
podule->fast_base = 0;
podule->medium_base = 0;
podule->slow_base = 0;
podule->sync_base = 0;
podule->mod_base = 0;
podule->easi_base = EASI_BASE + loop * EASI_SIZE;
}
/* XXX - Really needs to be linked to a DMA manager */
if (IOMD_ID == RPC600_IOMD_ID) {
switch (loop) {
case 0:
podule->dma_channel = 2;
podule->dma_interrupt = IRQ_DMACH2;
break;
case 1:
podule->dma_channel = 3;
podule->dma_interrupt = IRQ_DMACH3;
break;
}
}
/* Get information from the podule header */
podule->flags0 = address[0];
if ((podule->flags0 & 0x78) == 0) {
podule->flags1 = address[4];
podule->reserved = address[8];
podule->product = address[12] + (address[16] << 8);
podule->manufacturer = address[20] + (address[24] << 8);
podule->country = address[28];
if (podule->flags1 & PODULE_FLAGS_IS) {
podule->irq_addr = address[52] + (address[56] << 8) + (address[60] << 16);
podule->irq_addr += podule->slow_base;
podule->irq_mask = address[48];
if (podule->irq_mask == 0)
podule->irq_mask = 0x01;
podule->fiq_addr = address[36] + (address[40] << 8) + (address[44] << 16);
podule->fiq_addr += podule->slow_base;
podule->fiq_mask = address[32];
if (podule->fiq_mask == 0)
podule->fiq_mask = 0x04;
} else {
podule->irq_addr = podule->slow_base;
podule->irq_mask = 0x01;
podule->fiq_addr = podule->slow_base;
podule->fiq_mask = 0x04;
}
}
poduleexamine(podule, dev, SLOT_POD);
}
}
/*
* void podulebusattach(struct device *parent, struct device *dev, void *aux)
*
* Attach podulebus.
* This probes all the podules and sets up the podules array with
* information found in the podule headers.
* After identifing all the podules, all the children of the podulebus
* are probed and attached.
*/
void
podulebusattach(parent, self, aux)
struct device *parent;
struct device *self;
void *aux;
{
int loop;
struct podule_attach_args pa;
#if 0
int easi_time;
int bit;
#endif
unsigned int value;
char argstring[20];
#if 0
easi_time = IOMD_READ_BYTE(IOMD_ECTCR);
printf(": easi timings=");
for (bit = 0x01; bit < 0x100; bit = bit << 1)
if (easi_time & bit)
printf("C");
else
printf("A");
#endif
printf("\n");
/* Ok we need to map in the podulebus */
/* Map the FAST and SYNC simple podules */
map_section((vm_offset_t)pmap_kernel()->pm_pdir,
SYNC_PODULE_BASE & 0xfff00000, SYNC_PODULE_HW_BASE & 0xfff00000, 0);
cpu_tlb_flushD();
/* Now map the EASI space */
for (loop = 0; loop < MAX_PODULES; ++loop) {
int loop1;
for (loop1 = loop * EASI_SIZE; loop1 < ((loop + 1) * EASI_SIZE);
loop1 += L1_SEC_SIZE)
map_section((vm_offset_t)pmap_kernel()->pm_pdir, EASI_BASE + loop1,
EASI_HW_BASE + loop1, 0);
}
cpu_tlb_flushD();
/*
* The MEDIUM and SLOW simple podules and the module space will have been
* mapped when the IOMD and COMBO we mapped in for the RPC
*/
/* Find out what hardware is bolted on */
podulescan(self);
netslotscan(self);
/* Look for drivers to attach */
for (loop = 0; loop < MAX_PODULES+MAX_NETSLOTS; ++loop) {
#if 1
/* Provide backwards compat for a while */
sprintf(argstring, "podule%d.disable", loop);
if (get_bootconf_option(boot_args, argstring,
BOOTOPT_TYPE_BOOLEAN, &value)) {
if (value) {
if (podules[loop].slottype != SLOT_NONE)
printf("podule%d: Disabled\n", loop);
continue;
}
}
#endif
sprintf(argstring, "podule%d=", loop);
if (get_bootconf_option(boot_args, argstring,
BOOTOPT_TYPE_HEXINT, &value)) {
/* Override the ID */
podules[loop].manufacturer = value >> 16;
podules[loop].product = value & 0xffff;
/* Any old description is now wrong */
podules[loop].description[0] = 0;
if (value != 0xffff) {
printf("podule%d: ID overriden man=%04x prod=%04x\n",
loop, podules[loop].manufacturer,
podules[loop].product);
podules[loop].slottype = SLOT_POD;
pa.pa_podule_number = loop;
pa.pa_ih = pa.pa_podule_number;
pa.pa_podule = &podules[loop];
pa.pa_iot = &podulebus_bs_tag;
config_found_sm(self, &pa, podulebusprint,
podulebussubmatch);
continue;
}
if (value == 0xffff) {
printf("podule%d: Disabled\n", loop);
continue;
}
}
if (podules[loop].slottype != SLOT_NONE) {
pa.pa_podule_number = loop;
pa.pa_ih = pa.pa_podule_number;
pa.pa_podule = &podules[loop];
pa.pa_iot = &podulebus_bs_tag;
config_found_sm(self, &pa, podulebusprint, podulebussubmatch);
}
}
}
struct cfattach podulebus_ca = {
sizeof(struct device), podulebusmatch, podulebusattach
};
/* Useful functions that drivers may share */
/*
* Match a podule structure with the specified parameters
* Returns 0 if the match failed
* The required_slot is not used at the moment.
*/
int
matchpodule(pa, manufacturer, product, required_slot)
struct podule_attach_args *pa;
int manufacturer;
int product;
int required_slot;
{
if (pa->pa_podule->attached)
panic("podulebus: Podule already attached\n");
if (IS_PODULE(pa, manufacturer, product))
return(1);
return(0);
}
void *
podulebus_irq_establish(ih, ipl, func, arg, ev)
podulebus_intr_handle_t ih;
int ipl;
int (*func) __P((void *));
void *arg;
struct evcnt *ev;
{
/* XXX We don't actually use the evcnt supplied, just its name. */
return intr_claim(podules[ih].interrupt, ipl, ev->ev_group, func,
arg);
}
/*
* Generate a bus_space_tag_t with the specified address-bus shift.
*/
void
podulebus_shift_tag(tag, shift, tagp)
bus_space_tag_t tag, *tagp;
u_int shift;
{
/*
* For the podulebus, the bus tag cookie is the shift to apply
* to registers, so duplicate the bus space tag and change the
* cookie.
*/
/* XXX never freed, but podules are never detached anyway. */
*tagp = malloc(sizeof(struct bus_space), M_DEVBUF, M_WAITOK);
**tagp = *tag;
(*tagp)->bs_cookie = (void *)shift;
}
int
podulebus_initloader(struct podulebus_attach_args *pa)
{
/* No loader support at present on arm32, so always fail. */
return -1;
}
int
podloader_readbyte(struct podulebus_attach_args *pa, u_int addr)
{
panic("podloader_readbyte");
}
void
podloader_writebyte(struct podulebus_attach_args *pa, u_int addr, int val)
{
panic("podloader_writebyte");
}
void
podloader_reset(struct podulebus_attach_args *pa)
{
panic("podloader_reset");
}
int
podloader_callloader(struct podulebus_attach_args *pa, u_int r0, u_int r1)
{
panic("podloader_callloader");
}
void
podloader_read_region(struct podulebus_attach_args *pa, u_int src,
u_int8_t *dest, size_t length)
{
while (length--)
*dest++ = podloader_readbyte(pa, src++);
podloader_reset(pa);
}
/* End of podulebus.c */

3
sys/arch/arm32/podulebus/podulebus.h
View File

@ -1,3 +0,0 @@
/* $NetBSD: podulebus.h,v 1.16 2001/03/20 22:59:41 bjh21 Exp $ */
#include <dev/podulebus/podulebus.h>

266
sys/arch/arm32/podulebus/podulebus_io.c
View File

@ -1,266 +0,0 @@
/* $NetBSD: podulebus_io.c,v 1.10 2001/09/10 02:20:20 reinoud Exp $ */
/*
* Copyright (c) 1997 Mark Brinicombe.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Mark Brinicombe.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* bus_space I/O functions for podulebus
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <machine/bus.h>
/* Proto types for all the bus_space structure functions */
bs_protos(podulebus);
bs_protos(bs_notimpl);
/* Declare the podulebus bus space tag */
struct bus_space podulebus_bs_tag = {
/* cookie */
(void *) 2, /* Shift to apply to registers */
/* mapping/unmapping */
podulebus_bs_map,
podulebus_bs_unmap,
podulebus_bs_subregion,
/* allocation/deallocation */
podulebus_bs_alloc,
podulebus_bs_free,
/* get kernel virtual address */
0, /* there is no linear mapping */
/* mmap bus space for userland */
bs_notimpl_bs_mmap, /* there is no bus mapping ... well maybe EASI space? */
/* barrier */
podulebus_bs_barrier,
/* read (single) */
podulebus_bs_r_1,
podulebus_bs_r_2,
podulebus_bs_r_4,
bs_notimpl_bs_r_8,
/* read multiple */
podulebus_bs_rm_1,
podulebus_bs_rm_2,
bs_notimpl_bs_rm_4,
bs_notimpl_bs_rm_8,
/* read region */
podulebus_bs_rr_1,
podulebus_bs_rr_2,
bs_notimpl_bs_rr_4,
bs_notimpl_bs_rr_8,
/* write (single) */
podulebus_bs_w_1,
podulebus_bs_w_2,
podulebus_bs_w_4,
bs_notimpl_bs_w_8,
/* write multiple */
podulebus_bs_wm_1,
podulebus_bs_wm_2,
bs_notimpl_bs_wm_4,
bs_notimpl_bs_wm_8,
/* write region */
podulebus_bs_wr_1,
podulebus_bs_wr_2,
bs_notimpl_bs_wr_4,
bs_notimpl_bs_wr_8,
/* set multiple */
bs_notimpl_bs_sm_1,
bs_notimpl_bs_sm_2,
bs_notimpl_bs_sm_4,
bs_notimpl_bs_sm_8,
/* set region */
podulebus_bs_sr_1,
podulebus_bs_sr_2,
bs_notimpl_bs_sr_4,
bs_notimpl_bs_sr_8,
/* copy */
bs_notimpl_bs_c_1,
bs_notimpl_bs_c_2,
bs_notimpl_bs_c_4,
bs_notimpl_bs_c_8,
};
/* bus space functions */
int
podulebus_bs_map(t, bpa, size, cacheable, bshp)
void *t;
bus_addr_t bpa;
bus_size_t size;
int cacheable;
bus_space_handle_t *bshp;
{
/*
* Temporary implementation as all I/O is already mapped etc.
*
* Eventually this function will do the mapping check for multiple maps
*/
*bshp = bpa;
return(0);
}
int
podulebus_bs_alloc(t, rstart, rend, size, alignment, boundary, cacheable,
bpap, bshp)
void *t;
bus_addr_t rstart, rend;
bus_size_t size, alignment, boundary;
int cacheable;
bus_addr_t *bpap;
bus_space_handle_t *bshp;
{
panic("podulebus_bs_alloc(): Help!\n");
}
void
podulebus_bs_unmap(t, bsh, size)
void *t;
bus_space_handle_t bsh;
bus_size_t size;
{
/*
* Temporary implementation
*/
}
void
podulebus_bs_free(t, bsh, size)
void *t;
bus_space_handle_t bsh;
bus_size_t size;
{
panic("podulebus_bs_free(): Help!\n");
/* podulebus_bs_unmap() does all that we need to do. */
/* podulebus_bs_unmap(t, bsh, size);*/
}
int
podulebus_bs_subregion(t, bsh, offset, size, nbshp)
void *t;
bus_space_handle_t bsh;
bus_size_t offset, size;
bus_space_handle_t *nbshp;
{
*nbshp = bsh + (offset << ((int)t));
return (0);
}
void
podulebus_bs_barrier(t, bsh, offset, len, flags)
void *t;
bus_space_handle_t bsh;
bus_size_t offset, len;
int flags;
{
}
/* Rough-and-ready implementations from arm26 */
void
podulebus_bs_rr_1(void *cookie, bus_space_handle_t bsh,
bus_size_t offset, u_int8_t *datap, bus_size_t count)
{
int i;
for (i = 0; i < count; i++)
datap[i] = podulebus_bs_r_1(cookie, bsh, offset + i);
}
void
podulebus_bs_rr_2(void *cookie, bus_space_handle_t bsh,
bus_size_t offset, u_int16_t *datap, bus_size_t count)
{
int i;
for (i = 0; i < count; i++)
datap[i] = podulebus_bs_r_2(cookie, bsh, offset + i);
}
void
podulebus_bs_wr_1(void *cookie, bus_space_handle_t bsh,
bus_size_t offset, u_int8_t const *datap,
bus_size_t count)
{
int i;
for (i = 0; i < count; i++)
podulebus_bs_w_1(cookie, bsh, offset + i, datap[i]);
}
void
podulebus_bs_wr_2(void *cookie, bus_space_handle_t bsh,
bus_size_t offset, u_int16_t const *datap,
bus_size_t count)
{
int i;
for (i = 0; i < count; i++)
podulebus_bs_w_2(cookie, bsh, offset + i, datap[i]);
}
void
podulebus_bs_sr_1(void *cookie, bus_space_handle_t bsh,
bus_size_t offset, u_int8_t value, bus_size_t count)
{
int i;
for (i = 0; i < count; i++)
podulebus_bs_w_1(cookie, bsh, offset + i, value);
}
void
podulebus_bs_sr_2(void *cookie, bus_space_handle_t bsh,
bus_size_t offset, u_int16_t value, bus_size_t count)
{
int i;
for (i = 0; i < count; i++)
podulebus_bs_w_2(cookie, bsh, offset + i, value);
}

133
sys/arch/arm32/podulebus/podulebus_io_asm.S
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@ -1,133 +0,0 @@
/* $NetBSD: podulebus_io_asm.S,v 1.9 1999/10/26 06:53:44 cgd Exp $ */
/*
* Copyright (c) 1997 Mark Brinicombe.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Mark Brinicombe.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <machine/asm.h>
/*
* bus_space I/O functions for podulebus
*/
/*
* read single
*/
ENTRY(podulebus_bs_r_1)
mov r2, r2, lsl r0
ldrb r0, [r1, r2]
mov pc, lr
ENTRY(podulebus_bs_r_2)
mov r2, r2, lsl r0
ldr r0, [r1, r2]
bic r0, r0, #0xff000000
bic r0, r0, #0x00ff0000
mov pc, lr
ENTRY(podulebus_bs_r_4)
mov r2, r2, lsl r0
ldr r0, [r1, r2]
mov pc, lr
/*
* write single
*/
ENTRY(podulebus_bs_w_1)
mov r2, r2, lsl r0
strb r3, [r1, r2]
mov pc, lr
ENTRY(podulebus_bs_w_2)
mov r3, r3, lsl #16
orr r3, r3, r3, lsr #16
mov r2, r2, lsl r0
str r3, [r1, r2]
mov pc, lr
ENTRY(podulebus_bs_w_4)
mov r2, r2, lsl r0
str r3, [r1, r2]
mov pc, lr
/*
* read multiple
*/
ENTRY(podulebus_bs_rm_1)
add r0, r1, r2, lsl r0
ldr r2, [sp, #0]
/* Make sure that we have a positive length */
cmp r2, #0x00000000
movle pc, lr
podulebus_rm_1_loop:
ldrb r1, [r0]
strb r1, [r3], #0x0001
subs r2, r2, #0x00000001
bgt podulebus_rm_1_loop
mov pc, lr
ENTRY(podulebus_bs_rm_2)
add r0, r1, r2, lsl r0
mov r1, r3
ldr r2, [sp, #0]
b _C_LABEL(insw)
/*
* write multiple
*/
ENTRY(podulebus_bs_wm_1)
add r0, r1, r2, lsl r0
ldr r2, [sp, #0]
/* Make sure that we have a positive length */
cmp r2, #0x00000000
movle pc, lr
podulebus_wm_1_loop:
ldrb r1, [r3], #0x0001
strb r1, [r0]
subs r2, r2, #0x00000001
bgt podulebus_wm_1_loop
mov pc, lr
ENTRY(podulebus_bs_wm_2)
add r0, r1, r2, lsl r0
mov r1, r3
ldr r2, [sp, #0]
b _C_LABEL(outsw)

491
sys/arch/arm32/podulebus/ptsc.c
View File

@ -1,491 +0,0 @@
/* $NetBSD: ptsc.c,v 1.30 2001/07/04 17:54:18 bjh21 Exp $ */
/*
* Copyright (c) 1995 Scott Stevens
* Copyright (c) 1995 Daniel Widenfalk
* Copyright (c) 1994 Christian E. Hopps
* Copyright (c) 1982, 1990 The Regents of the University of California.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)ptsc.c
*/
/*
* Power-tec SCSI-2 driver uses SFAS216 generic driver
*
* Thanks to Alsystems for loaning a development card and providing
* programming information.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/device.h>
#include <dev/scsipi/scsi_all.h>
#include <dev/scsipi/scsipi_all.h>
#include <dev/scsipi/scsiconf.h>
#include <uvm/uvm_extern.h>
#include <machine/pmap.h>
#include <machine/io.h>
#include <machine/irqhandler.h>
#include <machine/bootconfig.h>
#include <arm32/podulebus/podulebus.h>
#include <arm32/podulebus/sfasreg.h>
#include <arm32/podulebus/sfasvar.h>
#include <arm32/podulebus/ptscreg.h>
#include <arm32/podulebus/ptscvar.h>
#include <dev/podulebus/podules.h>
#include <dev/podulebus/powerromreg.h>
void ptscattach __P((struct device *, struct device *, void *));
int ptscmatch __P((struct device *, struct cfdata *, void *));
void ptsc_scsi_request __P((struct scsipi_channel *,
scsipi_adapter_req_t, void *));
struct cfattach ptsc_ca = {
sizeof(struct ptsc_softc), ptscmatch, ptscattach
};
int ptsc_intr __P((void *arg));
int ptsc_setup_dma __P((struct sfas_softc *sc, void *ptr, int len,
int mode));
int ptsc_build_dma_chain __P((struct sfas_softc *sc,
struct sfas_dma_chain *chain, void *p, int l));
int ptsc_need_bump __P((struct sfas_softc *sc, void *ptr, int len));
void ptsc_led __P((struct sfas_softc *sc, int mode));
/*
* if we are a Power-tec SCSI-2 card
*/
int
ptscmatch(pdp, cf, auxp)
struct device *pdp;
struct cfdata *cf;
void *auxp;
{
struct podule_attach_args *pa = (struct podule_attach_args *)auxp;
/* Look for the card */
/*
* All Power-tec cards effectively have PowerROMS. Note,
* though, that here, if we fail to initialise the loader, we
* assume this _is_ the right kind of card.
*/
if (pa->pa_product == PODULE_ALSYSTEMS_SCSI &&
(podulebus_initloader(pa) != 0 ||
podloader_callloader(pa, 0, 0) == PRID_POWERTEC))
return 1;
return 0;
}
void
ptscattach(pdp, dp, auxp)
struct device *pdp;
struct device *dp;
void *auxp;
{
struct ptsc_softc *sc = (struct ptsc_softc *)dp;
struct podule_attach_args *pa;
ptsc_regmap_p rp = &sc->sc_regmap;
vu_char *fas;
pa = (struct podule_attach_args *)auxp;
if (pa->pa_podule_number == -1)
panic("Podule has disappeared !");
sc->sc_specific.sc_podule_number = pa->pa_podule_number;
sc->sc_specific.sc_podule = pa->pa_podule;
sc->sc_specific.sc_iobase =
(vu_char *)sc->sc_specific.sc_podule->fast_base;
rp->chipreset = &sc->sc_specific.sc_iobase[PTSC_CONTROL_CHIPRESET];
rp->inten = &sc->sc_specific.sc_iobase[PTSC_CONTROL_INTEN];
rp->status = &sc->sc_specific.sc_iobase[PTSC_STATUS];
rp->term = &sc->sc_specific.sc_iobase[PTSC_CONTROL_TERM];
rp->led = &sc->sc_specific.sc_iobase[PTSC_CONTROL_LED];
fas = &sc->sc_specific.sc_iobase[PTSC_FASOFFSET_BASE];
rp->FAS216.sfas_tc_low = &fas[PTSC_FASOFFSET_TCL];
rp->FAS216.sfas_tc_mid = &fas[PTSC_FASOFFSET_TCM];
rp->FAS216.sfas_fifo = &fas[PTSC_FASOFFSET_FIFO];
rp->FAS216.sfas_command = &fas[PTSC_FASOFFSET_COMMAND];
rp->FAS216.sfas_dest_id = &fas[PTSC_FASOFFSET_DESTID];
rp->FAS216.sfas_timeout = &fas[PTSC_FASOFFSET_TIMEOUT];
rp->FAS216.sfas_syncper = &fas[PTSC_FASOFFSET_PERIOD];
rp->FAS216.sfas_syncoff = &fas[PTSC_FASOFFSET_OFFSET];
rp->FAS216.sfas_config1 = &fas[PTSC_FASOFFSET_CONFIG1];
rp->FAS216.sfas_clkconv = &fas[PTSC_FASOFFSET_CLOCKCONV];
rp->FAS216.sfas_test = &fas[PTSC_FASOFFSET_TEST];
rp->FAS216.sfas_config2 = &fas[PTSC_FASOFFSET_CONFIG2];
rp->FAS216.sfas_config3 = &fas[PTSC_FASOFFSET_CONFIG3];
rp->FAS216.sfas_tc_high = &fas[PTSC_FASOFFSET_TCH];
rp->FAS216.sfas_fifo_bot = &fas[PTSC_FASOFFSET_FIFOBOTTOM];
sc->sc_softc.sc_fas = (sfas_regmap_p)rp;
sc->sc_softc.sc_spec = &sc->sc_specific;
sc->sc_softc.sc_led = ptsc_led;
sc->sc_softc.sc_setup_dma = ptsc_setup_dma;
sc->sc_softc.sc_build_dma_chain = ptsc_build_dma_chain;
sc->sc_softc.sc_need_bump = ptsc_need_bump;
sc->sc_softc.sc_clock_freq = 40; /* Power-Tec runs at 8MHz */
sc->sc_softc.sc_timeout = 250; /* Set default timeout to 250ms */
sc->sc_softc.sc_config_flags = SFAS_NO_DMA /*| SFAS_NF_DEBUG*/;
sc->sc_softc.sc_host_id = 7; /* Should check the jumpers */
sc->sc_softc.sc_bump_sz = NBPG;
sc->sc_softc.sc_bump_pa = 0x0;
sfasinitialize((struct sfas_softc *)sc);
sc->sc_softc.sc_adapter.adapt_dev = &sc->sc_softc.sc_dev;
sc->sc_softc.sc_adapter.adapt_nchannels = 1;
sc->sc_softc.sc_adapter.adapt_openings = 7;
sc->sc_softc.sc_adapter.adapt_max_periph = 1;
sc->sc_softc.sc_adapter.adapt_ioctl = NULL;
sc->sc_softc.sc_adapter.adapt_minphys = sfas_minphys;
sc->sc_softc.sc_adapter.adapt_request = ptsc_scsi_request;
sc->sc_softc.sc_channel.chan_adapter = &sc->sc_softc.sc_adapter;
sc->sc_softc.sc_channel.chan_bustype = &scsi_bustype;
sc->sc_softc.sc_channel.chan_channel = 0;
sc->sc_softc.sc_channel.chan_ntargets = 8;
sc->sc_softc.sc_channel.chan_nluns = 8;
sc->sc_softc.sc_channel.chan_id = sc->sc_softc.sc_host_id;
/* Provide an override for the host id */
(void)get_bootconf_option(boot_args, "ptsc.hostid",
BOOTOPT_TYPE_INT, &sc->sc_softc.sc_channel.chan_id);
printf(": host=%d", sc->sc_softc.sc_channel.chan_id);
/* initialise the card */
/* *rp->term = 0;*/
*rp->inten = (PTSC_POLL?0:1);
*rp->led = 0;
#if PTSC_POLL == 0
evcnt_attach_dynamic(&sc->sc_softc.sc_intrcnt, EVCNT_TYPE_INTR, NULL,
dp->dv_xname, "intr");
sc->sc_softc.sc_ih = podulebus_irq_establish(pa->pa_ih, IPL_BIO,
ptsc_intr, &sc->sc_softc, &sc->sc_softc.sc_intrcnt);
if (sc->sc_softc.sc_ih == NULL)
panic("%s: Cannot install IRQ handler\n", dp->dv_xname);
#else
printf(" polling");
#endif
printf("\n");
/* attach all scsi units on us */
config_found(dp, &sc->sc_softc.sc_channel, scsiprint);
}
int
ptsc_intr(arg)
void *arg;
{
struct sfas_softc *dev = arg;
ptsc_regmap_p rp;
int quickints;
rp = (ptsc_regmap_p)dev->sc_fas;
if (*rp->FAS216.sfas_status & SFAS_STAT_INTERRUPT_PENDING) {
quickints = 16;
do {
dev->sc_status = *rp->FAS216.sfas_status;
dev->sc_interrupt = *rp->FAS216.sfas_interrupt;
if (dev->sc_interrupt & SFAS_INT_RESELECTED) {
dev->sc_resel[0] = *rp->FAS216.sfas_fifo;
dev->sc_resel[1] = *rp->FAS216.sfas_fifo;
}
sfasintr(dev);
} while((*rp->FAS216.sfas_status & SFAS_STAT_INTERRUPT_PENDING)
&& --quickints);
}
return(0); /* Pass interrupt on down the chain */
}
/* Load transfer address into dma register */
void
ptsc_set_dma_adr(sc, ptr)
struct sfas_softc *sc;
void *ptr;
{
#if 0
ptsc_regmap_p rp;
unsigned int *p;
unsigned int d;
#endif
#if 0
printf("ptsc_set_dma_adr(sc = 0x%08x, ptr = 0x%08x)\n", (u_int)sc, (u_int)ptr);
#endif
return;
#if 0
rp = (ptsc_regmap_p)sc->sc_fas;
d = (unsigned int)ptr;
p = (unsigned int *)((d & 0xFFFFFF) + (int)rp->dmabase);
*rp->clear=0;
*p = d;
#endif
}
/* Set DMA transfer counter */
void
ptsc_set_dma_tc(sc, len)
struct sfas_softc *sc;
unsigned int len;
{
printf("ptsc_set_dma_tc(sc, len = 0x%08x)", len);
*sc->sc_fas->sfas_tc_low = len; len >>= 8;
*sc->sc_fas->sfas_tc_mid = len; len >>= 8;
*sc->sc_fas->sfas_tc_high = len;
}
/* Set DMA mode */
void
ptsc_set_dma_mode(sc, mode)
struct sfas_softc *sc;
int mode;
{
#if 0
struct csc_specific *spec;
spec = sc->sc_spec;
spec->portbits = (spec->portbits & ~FLSC_PB_DMA_BITS) | mode;
*((flsc_regmap_p)sc->sc_fas)->hardbits = spec->portbits;
#endif
}
/* Initialize DMA for transfer */
int
ptsc_setup_dma(sc, ptr, len, mode)
struct sfas_softc *sc;
void *ptr;
int len;
int mode;
{
int retval;
retval = 0;
#if 0
printf("ptsc_setup_dma(sc, ptr = 0x%08x, len = 0x%08x, mode = 0x%08x)\n", (u_int)ptr, len, mode);
#endif
return(0);
#if 0
switch(mode) {
case SFAS_DMA_READ:
case SFAS_DMA_WRITE:
flsc_set_dma_adr(sc, ptr);
if (mode == SFAS_DMA_READ)
flsc_set_dma_mode(sc,FLSC_PB_ENABLE_DMA | FLSC_PB_DMA_READ);
else
flsc_set_dma_mode(sc,FLSC_PB_ENABLE_DMA | FLSC_PB_DMA_WRITE);
flsc_set_dma_tc(sc, len);
break;
case SFAS_DMA_CLEAR:
default:
flsc_set_dma_mode(sc, FLSC_PB_DISABLE_DMA);
flsc_set_dma_adr(sc, 0);
retval = (*sc->sc_fas->sfas_tc_high << 16) |
(*sc->sc_fas->sfas_tc_mid << 8) |
*sc->sc_fas->sfas_tc_low;
flsc_set_dma_tc(sc, 0);
break;
}
return(retval);
#endif
}
/* Check if address and len is ok for DMA transfer */
int
ptsc_need_bump(sc, ptr, len)
struct sfas_softc *sc;
void *ptr;
int len;
{
int p;
p = (int)ptr & 0x03;
if (p) {
p = 4-p;
if (len < 256)
p = len;
}
return(p);
}
/* Interrupt driven routines */
int
ptsc_build_dma_chain(sc, chain, p, l)
struct sfas_softc *sc;
struct sfas_dma_chain *chain;
void *p;
int l;
{
#if 0
vm_offset_t pa, lastpa;
char *ptr;
int len, prelen, postlen, max_t, n;
#endif
#if 0
printf("ptsc_build_dma_chain()\n");
#endif
return(0);
#if 0
if (l == 0)
return(0);
#define set_link(n, p, l, f)\
do { chain[n].ptr = (p); chain[n].len = (l); chain[n++].flg = (f); } while(0)
n = 0;
if (l < 512)
set_link(n, (vm_offset_t)p, l, SFAS_CHAIN_BUMP);
else if (p >= (void *)0xFF000000) {
while(l != 0) {
len = ((l > sc->sc_bump_sz) ? sc->sc_bump_sz : l);
set_link(n, (vm_offset_t)p, len, SFAS_CHAIN_BUMP);
p += len;
l -= len;
}
} else {
ptr = p;
len = l;
pa = kvtop(ptr);
prelen = ((int)ptr & 0x03);
if (prelen) {
prelen = 4-prelen;
set_link(n, (vm_offset_t)ptr, prelen, SFAS_CHAIN_BUMP);
ptr += prelen;
len -= prelen;
}
lastpa = 0;
while(len > 3) {
pa = kvtop(ptr);
max_t = NBPG - (pa & PGOFSET);
if (max_t > len)
max_t = len;
max_t &= ~3;
if (lastpa == pa)
sc->sc_chain[n-1].len += max_t;
else
set_link(n, pa, max_t, SFAS_CHAIN_DMA);
lastpa = pa+max_t;
ptr += max_t;
len -= max_t;
}
if (len)
set_link(n, (vm_offset_t)ptr, len, SFAS_CHAIN_BUMP);
}
return(n);
#endif
}
/* Turn on/off led */
void
ptsc_led(sc, mode)
struct sfas_softc *sc;
int mode;
{
ptsc_regmap_p rp;
rp = (ptsc_regmap_p)sc->sc_fas;
if (mode) {
sc->sc_led_status++;
} else {
if (sc->sc_led_status)
sc->sc_led_status--;
}
*rp->led = (sc->sc_led_status?1:0);
}
void
ptsc_scsi_request(chan, req, arg)
struct scsipi_channel *chan;
scsipi_adapter_req_t req;
void *arg;
{
struct scsipi_xfer *xs;
switch (req) {
case ADAPTER_REQ_RUN_XFER:
xs = arg;
/* ensure command is polling for the moment */
#if PTSC_POLL > 0
xs->xs_control |= XS_CTL_POLL;
#endif
#if 0
printf("Opcode %d\n", (int)(xs->cmd->opcode));
#endif
default:
}
sfas_scsi_request(chan, req, arg);
}

75
sys/arch/arm32/podulebus/ptscreg.h
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@ -1,75 +0,0 @@
/* $NetBSD: ptscreg.h,v 1.2 1996/10/14 23:35:41 mark Exp $ */
/*
* Copyright (c) 1995 Scott Stevens
* Copyright (c) 1995 Daniel Widenfalk
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Daniel Widenfalk
* for the NetBSD Project.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Power-tec SCSI-2 with FAS216 SCSI interface hardware description.
*/
#ifndef _PTSCREG_H_
#define _PTSCREG_H_
#include <arm32/podulebus/sfasvar.h>
typedef volatile unsigned short vu_short;
typedef struct ptsc_regmap {
sfas_regmap_t FAS216;
vu_char *chipreset;
vu_char *inten;
vu_char *status;
vu_char *term;
vu_char *led;
} ptsc_regmap_t;
typedef ptsc_regmap_t *ptsc_regmap_p;
#define PTSC_CONTROL_CHIPRESET 0x1018
#define PTSC_CONTROL_INTEN 0x101c
#define PTSC_STATUS 0x2000
#define PTSC_CONTROL_TERM 0x2018
#define PTSC_CONTROL_LED 0x201c
#define PTSC_FASOFFSET_BASE 0x3000
#define PTSC_FASOFFSET_TCL 0x0000
#define PTSC_FASOFFSET_TCM 0x0040
#define PTSC_FASOFFSET_FIFO 0x0080
#define PTSC_FASOFFSET_COMMAND 0x00c0
#define PTSC_FASOFFSET_DESTID 0x0100
#define PTSC_FASOFFSET_TIMEOUT 0x0140
#define PTSC_FASOFFSET_PERIOD 0x0180
#define PTSC_FASOFFSET_OFFSET 0x01c0
#define PTSC_FASOFFSET_CONFIG1 0x0200
#define PTSC_FASOFFSET_CLOCKCONV 0x0240
#define PTSC_FASOFFSET_TEST 0x0280
#define PTSC_FASOFFSET_CONFIG2 0x02c0
#define PTSC_FASOFFSET_CONFIG3 0x0300
#define PTSC_FASOFFSET_TCH 0x0380
#define PTSC_FASOFFSET_FIFOBOTTOM 0x03c0
#endif

52
sys/arch/arm32/podulebus/ptscvar.h
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@ -1,52 +0,0 @@
/* $NetBSD: ptscvar.h,v 1.2 1997/01/28 04:10:47 mark Exp $ */
/*
* Copyright (c) 1995 Scott Stevens
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Daniel Widenfalk
* for the NetBSD Project.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _PTSCVAR_H_
#define _PTSCVAR_H_
#include <arm32/podulebus/sfasvar.h>
#include <arm32/podulebus/ptscreg.h>
#define PTSC_POLL 0
struct ptsc_specific {
vu_char *sc_iobase;
int sc_podule_number;
podule_t *sc_podule;
};
struct ptsc_softc {
struct sfas_softc sc_softc;
ptsc_regmap_t sc_regmap;
struct ptsc_specific sc_specific;
};
#endif /* _PTSCVAR_H_ */

350
sys/arch/arm32/podulebus/rapide.c
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@ -1,350 +0,0 @@
/* $NetBSD: rapide.c,v 1.15 2001/03/17 20:34:45 bjh21 Exp $ */
/*
* Copyright (c) 1997-1998 Mark Brinicombe
* Copyright (c) 1997-1998 Causality Limited
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Mark Brinicombe
* for the NetBSD Project.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Card driver and probe and attach functions to use generic IDE driver
* for the RapIDE podule
*/
/*
* Thanks to Chris Honey at Raymond Datalink for providing information on
* addressing the RapIDE podule.
* RapIDE32 is Copyright (C) 1995,1996 Raymond Datalink. RapIDE32 is
* manufactured under license by Yellowstone Educational Solutions.
*/
/*
* At present this driver only supports the Issue 2 RapIDE podule.
*/
/*
* A small amount of work is required for Issue 1 podule support.
* The primary differences are the register addresses.
* Things are eased by the fact that we can identify the card by register
* the same register on both issues of the podule.
* Once we kmnow the issue we must change all our addresses accordingly.
* All the control registers are mapped the same between cards.
* The interrupt handler needs to take note that the issue 1 card needs
* the interrupt to be cleared via the interrupt clear register.
* This means we share addresses for the mapping of the control block and
* thus the card driver does not need to know about the differences.
* The differences show up a the controller level.
* A structure is used to hold the information about the addressing etc.
* An array of these structures holds the information for the primary and
* secondary connectors. This needs to be extended to hold this information
* for both issues. Then the indexing of this structures will utilise the
* card version number.
*
* Opps just noticed a mistake. The interrupt request register is different
* between cards so the card level attach routine will need to consider this.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/conf.h>
#include <sys/device.h>
#include <sys/malloc.h>
#include <machine/irqhandler.h>
#include <machine/io.h>
#include <machine/bus.h>
#include <machine/bootconfig.h>
#include <arm32/iomd/iomdreg.h>
#include <arm32/iomd/iomdvar.h>
#include <arm32/podulebus/podulebus.h>
#include <arm32/podulebus/rapidereg.h>
#include <dev/ata/atavar.h>
#include <dev/ic/wdcvar.h>
#include <dev/podulebus/podules.h>
/*
* RapIDE podule device.
*
* This probes and attaches the top level RapIDE device to the podulebus.
* It then configures any children of the RapIDE device.
* The attach args specify whether it is configuring the primary or
* secondary channel.
* The children are expected to be wdc devices using rapide attachments.
*/
/*
* RapIDE card softc structure.
*
* Contains the device node, podule information and global information
* required by the driver such as the card version and the interrupt mask.
*/
struct rapide_softc {
struct wdc_softc sc_wdcdev; /* common wdc definitions */
struct channel_softc *wdc_chanarray[2]; /* channels definition */
podule_t *sc_podule; /* Our podule info */
int sc_podule_number; /* Our podule number */
int sc_intr_enable_mask; /* Global intr mask */
int sc_version; /* Card version */
bus_space_tag_t sc_ctliot; /* Bus tag */
bus_space_handle_t sc_ctlioh; /* control handler */
struct rapide_channel {
struct channel_softc wdc_channel; /* generic part */
irqhandler_t rc_ih; /* interrupt handler */
int rc_irqmask; /* IRQ mask for this channel */
} rapide_channels[2];
};
int rapide_probe __P((struct device *, struct cfdata *, void *));
void rapide_attach __P((struct device *, struct device *, void *));
void rapide_shutdown __P((void *arg));
int rapide_intr __P((void *));
struct cfattach rapide_ca = {
sizeof(struct rapide_softc), rapide_probe, rapide_attach
};
/*
* We have a private bus space tag.
* This is created by copying the podulebus tag and then replacing
* a couple of the transfer functions.
*/
static struct bus_space rapide_bs_tag;
bs_rm_4_proto(rapide);
bs_wm_4_proto(rapide);
/*
* Create an array of address structures. These define the addresses and
* masks needed for the different channels for the card.
*
* XXX - Needs some work for issue 1 cards.
*/
struct {
u_int registers;
u_int aux_register;
u_int data_register;
u_int irq_mask;
} rapide_info[] = {
{ PRIMARY_DRIVE_REGISTERS_OFFSET, PRIMARY_AUX_REGISTER_OFFSET,
PRIMARY_DATA_REGISTER_OFFSET, PRIMARY_IRQ_MASK },
{ SECONDARY_DRIVE_REGISTERS_OFFSET, SECONDARY_AUX_REGISTER_OFFSET,
SECONDARY_DATA_REGISTER_OFFSET, SECONDARY_IRQ_MASK }
};
/*
* Card probe function
*
* Just match the manufacturer and podule ID's
*/
int
rapide_probe(parent, cf, aux)
struct device *parent;
struct cfdata *cf;
void *aux;
{
struct podule_attach_args *pa = (void *)aux;
if (matchpodule(pa, MANUFACTURER_YES, PODULE_YES_RAPIDE, -1) == 0)
return(0);
return(1);
}
/*
* Card attach function
*
* Identify the card version and configure any children.
* Install a shutdown handler to kill interrupts on shutdown
*/
void
rapide_attach(parent, self, aux)
struct device *parent, *self;
void *aux;
{
struct rapide_softc *sc = (void *)self;
struct podule_attach_args *pa = (void *)aux;
bus_space_tag_t iot;
bus_space_handle_t ctlioh;
u_int iobase;
int channel;
struct rapide_channel *rcp;
struct channel_softc *cp;
irqhandler_t *ihp;
/* Note the podule number and validate */
if (pa->pa_podule_number == -1)
panic("Podule has disappeared !");
sc->sc_podule_number = pa->pa_podule_number;
sc->sc_podule = pa->pa_podule;
podules[sc->sc_podule_number].attached = 1;
set_easi_cycle_type(sc->sc_podule_number, EASI_CYCLE_TYPE_C);
/*
* Duplicate the podule bus space tag and provide alternative
* bus_space_read_multi_4() and bus_space_write_multi_4()
* functions.
*/
rapide_bs_tag = *pa->pa_iot;
rapide_bs_tag.bs_rm_4 = rapide_bs_rm_4;
rapide_bs_tag.bs_wm_4 = rapide_bs_wm_4;
sc->sc_ctliot = iot = &rapide_bs_tag;
if (bus_space_map(iot, pa->pa_podule->easi_base +
CONTROL_REGISTERS_OFFSET, CONTROL_REGISTER_SPACE, 0, &ctlioh))
panic("%s: Cannot map control registers\n", self->dv_xname);
sc->sc_ctlioh = ctlioh;
sc->sc_version = bus_space_read_1(iot, ctlioh, VERSION_REGISTER_OFFSET) & VERSION_REGISTER_MASK;
/* bus_space_unmap(iot, ctl_ioh, CONTROL_REGISTER_SPACE);*/
printf(": Issue %d\n", sc->sc_version + 1);
if (sc->sc_version != VERSION_2_ID)
return;
if (shutdownhook_establish(rapide_shutdown, (void *)sc) == NULL)
panic("%s: Cannot install shutdown handler", self->dv_xname);
/* Set the interrupt info for this podule */
sc->sc_podule->irq_addr = pa->pa_podule->easi_base
+ CONTROL_REGISTERS_OFFSET + IRQ_REQUEST_REGISTER_BYTE_OFFSET;
sc->sc_podule->irq_mask = IRQ_MASK;
iobase = pa->pa_podule->easi_base;
/* Fill in wdc and channel infos */
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA32;
sc->sc_wdcdev.PIO_cap = 0;
sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc->sc_wdcdev.nchannels = 2;
for (channel = 0 ; channel < 2; channel++) {
rcp = &sc->rapide_channels[channel];
sc->wdc_chanarray[channel] = &rcp->wdc_channel;
cp = &rcp->wdc_channel;
cp->channel = channel;
cp->wdc = &sc->sc_wdcdev;
cp->ch_queue = malloc(sizeof(struct channel_queue),
M_DEVBUF, M_NOWAIT);
if (cp->ch_queue == NULL) {
printf("%s %s channel: can't allocate memory for "
"command queue", self->dv_xname,
(channel == 0) ? "primary" : "secondary");
continue;
}
cp->cmd_iot = iot;
cp->ctl_iot = iot;
cp->data32iot = iot;
if (bus_space_map(iot, iobase + rapide_info[channel].registers,
DRIVE_REGISTERS_SPACE, 0, &cp->cmd_ioh))
continue;
if (bus_space_map(iot, iobase +
rapide_info[channel].aux_register, 4, 0, &cp->ctl_ioh)) {
bus_space_unmap(iot, cp->cmd_ioh,
DRIVE_REGISTERS_SPACE);
continue;
}
if (bus_space_map(iot, iobase +
rapide_info[channel].data_register, 4, 0, &cp->data32ioh)) {
bus_space_unmap(iot, cp->cmd_ioh,
DRIVE_REGISTERS_SPACE);
bus_space_unmap(iot, cp->ctl_ioh, 4);
continue;
}
/* Disable interrupts and clear any pending interrupts */
rcp->rc_irqmask = rapide_info[channel].irq_mask;
sc->sc_intr_enable_mask &= ~rcp->rc_irqmask;
bus_space_write_1(iot, sc->sc_ctlioh, IRQ_MASK_REGISTER_OFFSET,
sc->sc_intr_enable_mask);
/* XXX - Issue 1 cards will need to clear any pending interrupts */
wdcattach(cp);
ihp = &rcp->rc_ih;
ihp->ih_func = rapide_intr;
ihp->ih_arg = rcp;
ihp->ih_level = IPL_BIO;
ihp->ih_name = "rapide";
ihp->ih_maskaddr = pa->pa_podule->irq_addr;
ihp->ih_maskbits = rcp->rc_irqmask;
if (irq_claim(sc->sc_podule->interrupt, ihp))
panic("%s: Cannot claim interrupt %d\n",
self->dv_xname, sc->sc_podule->interrupt);
/* clear any pending interrupts and enable interrupts */
sc->sc_intr_enable_mask |= rcp->rc_irqmask;
bus_space_write_1(iot, sc->sc_ctlioh,
IRQ_MASK_REGISTER_OFFSET, sc->sc_intr_enable_mask);
/* XXX - Issue 1 cards will need to clear any pending interrupts */
}
}
/*
* Card shutdown function
*
* Called via do_shutdown_hooks() during kernel shutdown.
* Clear the cards's interrupt mask to stop any podule interrupts.
*/
void
rapide_shutdown(arg)
void *arg;
{
struct rapide_softc *sc = arg;
/* Disable card interrupts */
bus_space_write_1(sc->sc_ctliot, sc->sc_ctlioh,
IRQ_MASK_REGISTER_OFFSET, 0);
}
/*
* Podule interrupt handler
*
* If the interrupt was from our card pass it on to the wdc interrupt handler
*/
int
rapide_intr(arg)
void *arg;
{
struct rapide_channel *rcp = arg;
irqhandler_t *ihp = &rcp->rc_ih;
volatile u_char *intraddr = (volatile u_char *)ihp->ih_maskaddr;
/* XXX - Issue 1 cards will need to clear the interrupt */
/* XXX - not bus space yet - should really be handled by podulebus */
if ((*intraddr) & ihp->ih_maskbits)
wdcintr(&rcp->wdc_channel);
return(0);
}

178
sys/arch/arm32/podulebus/rapide_io_asm.S
View File

@ -1,178 +0,0 @@
/* $NetBSD: rapide_io_asm.S,v 1.7 1998/12/12 17:28:05 mycroft Exp $ */
/*
* Copyright (c) 1997 Mark Brinicombe.
* Copyright (c) 1997 Causality Limited.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Mark Brinicombe
* for the NetBSD Project.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <machine/asm.h>
/*
* bus_space I/O functions for Yellowstone RapIDE podule
*
* These are optimised 32 bit transfer routines
*/
ENTRY(rapide_bs_rm_4)
add r0, r1, r2
mov r1, r3
/* Test length */
ldr r2, [sp, #0]
tst r2, #0x7f
beq rapide_rm_4_m128
tst r2, #0x07
beq rapide_rm_4_m8
/* xfer 4 bytes at a time */
rapide_rm_4_loop:
ldr r3, [r0]
str r3, [r1], #0x0004
subs r2, r2, #1
bne rapide_rm_4_loop
mov pc, lr
rapide_rm_4_m8:
/* xfer 32 bytes at a time */
stmfd sp!, {r4-r10}
rapide_rm_4_m8_loop:
ldmia r0, {r3-r10}
stmia r1!, {r3-r10}
subs r2, r2, #8
bne rapide_rm_4_m8_loop
ldmfd sp!, {r4-r10}
mov pc, lr
rapide_rm_4_m128:
/* xfer 512 bytes at a time */
stmfd sp!, {r4-r12, r14}
rapide_rm_4_m128_loop:
ldmia r0, {r3-r12, r14}
stmia r1!, {r3-r12, r14}
ldmia r0, {r3-r12, r14}
stmia r1!, {r3-r12, r14}
ldmia r0, {r3-r12, r14}
stmia r1!, {r3-r12, r14}
ldmia r0, {r3-r12, r14}
stmia r1!, {r3-r12, r14}
ldmia r0, {r3-r12, r14}
stmia r1!, {r3-r12, r14}
ldmia r0, {r3-r12, r14}
stmia r1!, {r3-r12, r14}
ldmia r0, {r3-r12, r14}
stmia r1!, {r3-r12, r14}
ldmia r0, {r3-r12, r14}
stmia r1!, {r3-r12, r14}
ldmia r0, {r3-r12, r14}
stmia r1!, {r3-r12, r14}
ldmia r0, {r3-r12, r14}
stmia r1!, {r3-r12, r14}
ldmia r0, {r3-r12, r14}
stmia r1!, {r3-r12, r14}
ldmia r0, {r3-r9}
stmia r1!, {r3-r9}
subs r2, r2, #128
bne rapide_rm_4_m128_loop
ldmfd sp!, {r4-r12, pc}
ENTRY(rapide_bs_wm_4)
add r0, r1, r2
mov r1, r3
ldr r2, [sp, #0]
tst r2, #0x7f
beq rapide_wm_4_m128
tst r2, #0x07
beq rapide_wm_4_m8
/* xfer 4 bytes at a time */
rapide_wm_4_loop:
ldr r3, [r1], #0x0004
str r3, [r0]
subs r2, r2, #1
bne rapide_wm_4_loop
mov pc, lr
rapide_wm_4_m8:
/* xfer 32 bytes at a time */
stmfd sp!, {r4-r10}
rapide_wm_4_m8_loop:
ldmia r1!, {r3-r10}
stmia r0, {r3-r10}
subs r2, r2, #8
bne rapide_wm_4_m8_loop
ldmfd sp!, {r4-r10}
mov pc, lr
rapide_wm_4_m128:
/* xfer 512 bytes at a time */
stmfd sp!, {r4-r12}
rapide_wm_4_m128_loop:
ldmia r1!, {r3-r12}
stmia r0, {r3-r12}
ldmia r1!, {r3-r12}
stmia r0, {r3-r12}
ldmia r1!, {r3-r12}
stmia r0, {r3-r12}
ldmia r1!, {r3-r12}
stmia r0, {r3-r12}
ldmia r1!, {r3-r12}
stmia r0, {r3-r12}
ldmia r1!, {r3-r12}
stmia r0, {r3-r12}
ldmia r1!, {r3-r12}
stmia r0, {r3-r12}
ldmia r1!, {r3-r12}
stmia r0, {r3-r12}
ldmia r1!, {r3-r12}
stmia r0, {r3-r12}
ldmia r1!, {r3-r12}
stmia r0, {r3-r12}
ldmia r1!, {r3-r12}
stmia r0, {r3-r12}
ldmia r1!, {r3-r12}
stmia r0, {r3-r12}
ldmia r1!, {r3-r10}
stmia r0, {r3-r10}
subs r2, r2, #128
bne rapide_wm_4_m128_loop
ldmfd sp!, {r4-r12}
mov pc, lr

89
sys/arch/arm32/podulebus/rapidereg.h
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@ -1,89 +0,0 @@
/* $NetBSD: rapidereg.h,v 1.4 1999/03/22 10:14:12 mark Exp $ */
/*
* Copyright (c) 1997 Mark Brinicombe
* Copyright (c) 1997 Causality Limited
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Mark Brinicombe
* for the NetBSD Project.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Thanks to Chris Honey at Raymond Datalink for providing information on
* addressing the RapIDE podule.
* RapIDE32 is Copyright (C) 1995,1996 Raymond Datalink. RapIDE32 is
* manufactured under license by Yellowstone Educational Solutions.
*/
/*
* Registers and address offsets for the Yellowstone RapIDE card.
*
* These are for issue 2 cards only.
*/
/*
* This file needs to be extended to provide register information on
* both versions of the card.
*/
/* IDE drive registers */
#define PRIMARY_DRIVE_REGISTERS_OFFSET 0x400080
#define PRIMARY_AUX_REGISTER_OFFSET 0x400298
#define PRIMARY_DATA_REGISTER_OFFSET 0x600080
#define SECONDARY_DRIVE_REGISTERS_OFFSET 0x400000
#define SECONDARY_AUX_REGISTER_OFFSET 0x400218
#define SECONDARY_DATA_REGISTER_OFFSET 0x600000
#define DRIVE_REGISTERS_SPACE 0x20
#define DRIVE_REGISTER_BYTE_SPACING 4
/* Other registers */
#define CONTROL_REGISTERS_OFFSET 0x200000
#define CONTROL_REGISTER_SPACE 16
#define IRQ_MASK_REGISTER_OFFSET 0
#define IRQ_STATUS_REGISTER_OFFSET 0
#define IRQ_REQUEST_REGISTER_OFFSET 1
#define IRQ_REQUEST_REGISTER_BYTE_OFFSET (IRQ_REQUEST_REGISTER_OFFSET << 2)
#define IRQ_CLEAR_REGISTER_OFFSET 1
#define PRIMARY_IRQ_MASK 0x01
#define SECONDARY_IRQ_MASK 0x02
#define IRQ_MASK (PRIMARY_IRQ_MASK | SECONDARY_IRQ_MASK)
#define VERSION_REGISTER_OFFSET 3
#define VERSION_REGISTER_MASK 0x03
#define VERSION_1_ID 0x00
#define VERSION_2_ID 0x01
#define PIO_MODE_CONTROL_REGISTER_OFFSET 3
#define PIO_MODE_0 0
#define PIO_MODE_1 1
#define PIO_MODE_2 2
#define PIO_MODE_3 3
#define PIO_MODE_4 4

2547
sys/arch/arm32/podulebus/sbic.c
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sys/arch/arm32/podulebus/sbicreg.h
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/* $NetBSD: sbicreg.h,v 1.4 2001/08/14 22:58:18 rearnsha Exp $ */
/*
* Copyright (c) 1990 The Regents of the University of California.
* All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* Van Jacobson of Lawrence Berkeley Laboratory.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)scsireg.h 7.3 (Berkeley) 2/5/91
*/
/*
* AMD AM33C93A SCSI interface hardware description.
*
* Using parts of the Mach scsi driver for the 33C93
*/
#define SBIC_myid 0
#define SBIC_cdbsize 0
#define SBIC_control 1
#define SBIC_timeo 2
#define SBIC_cdb1 3
#define SBIC_tsecs 3
#define SBIC_cdb2 4
#define SBIC_theads 4
#define SBIC_cdb3 5
#define SBIC_tcyl_hi 5
#define SBIC_cdb4 6
#define SBIC_tcyl_lo 6
#define SBIC_cdb5 7
#define SBIC_addr_hi 7
#define SBIC_cdb6 8
#define SBIC_addr_2 8
#define SBIC_cdb7 9
#define SBIC_addr_3 9
#define SBIC_cdb8 10
#define SBIC_addr_lo 10
#define SBIC_cdb9 11
#define SBIC_secno 11
#define SBIC_cdb10 12
#define SBIC_headno 12
#define SBIC_cdb11 13
#define SBIC_cylno_hi 13
#define SBIC_cdb12 14
#define SBIC_cylno_lo 14
#define SBIC_tlun 15
#define SBIC_cmd_phase 16
#define SBIC_syn 17
#define SBIC_count_hi 18
#define SBIC_count_med 19
#define SBIC_count_lo 20
#define SBIC_selid 21
#define SBIC_rselid 22
#define SBIC_csr 23
#define SBIC_cmd 24
#define SBIC_data 25
/* sbic_asr is addressed directly */
/*
* Register defines
*/
/*
* Auxiliary Status Register
*/
#define SBIC_ASR_INT 0x80 /* Interrupt pending */
#define SBIC_ASR_LCI 0x40 /* Last command ignored */
#define SBIC_ASR_BSY 0x20 /* Busy, only cmd/data/asr readable */
#define SBIC_ASR_CIP 0x10 /* Busy, cmd unavail also */
#define SBIC_ASR_xxx 0x0c
#define SBIC_ASR_PE 0x02 /* Parity error (even) */
#define SBIC_ASR_DBR 0x01 /* Data Buffer Ready */
/*
* My ID register, and/or CDB Size
*/
#define SBIC_ID_FS_8_10 0x00 /* Input clock is 8-10 Mhz */
/* 11 Mhz is invalid */
#define SBIC_ID_FS_12_15 0x40 /* Input clock is 12-15 Mhz */
#define SBIC_ID_FS_16_20 0x80 /* Input clock is 16-20 Mhz */
#define SBIC_ID_EHP 0x10 /* Enable host parity */
#define SBIC_ID_EAF 0x08 /* Enable Advanced Features */
#define SBIC_ID_MASK 0x07
#define SBIC_ID_CBDSIZE_MASK 0x0f /* if unk SCSI cmd group */
/*
* Control register
*/
#define SBIC_CTL_DMA 0x80 /* Single byte dma */
#define SBIC_CTL_DBA_DMA 0x40 /* direct buffer acces (bus master)*/
#define SBIC_CTL_BURST_DMA 0x20 /* continuous mode (8237) */
#define SBIC_CTL_NO_DMA 0x00 /* Programmed I/O */
#define SBIC_CTL_HHP 0x10 /* Halt on host parity error */
#define SBIC_CTL_EDI 0x08 /* Ending disconnect interrupt */
#define SBIC_CTL_IDI 0x04 /* Intermediate disconnect interrupt*/
#define SBIC_CTL_HA 0x02 /* Halt on ATN */
#define SBIC_CTL_HSP 0x01 /* Halt on SCSI parity error */
/*
* Timeout period register
* [val in msecs, input clk in 0.1 Mhz]
*/
#define SBIC_TIMEOUT(val,clk) ((((val) * (clk)) / 800) + 1)
/*
* CDBn registers, note that
* cdb11 is used for status byte in target mode (send-status-and-cc)
* cdb12 sez if linked command complete, and w/flag if so
*/
/*
* Target LUN register
* [holds target status when select-and-xfer]
*/
#define SBIC_TLUN_VALID 0x80 /* did we receive an Identify msg */
#define SBIC_TLUN_DOK 0x40 /* Disconnect OK */
#define SBIC_TLUN_xxx 0x38
#define SBIC_TLUN_MASK 0x07
/*
* Command Phase register
*/
#define SBIC_CPH_MASK 0x7f /* values/restarts are cmd specific */
#define SBIC_CPH(p) ((p) & SBIC_CPH_MASK)
/*
* FIFO register
*/
#define SBIC_FIFO_DEEP 12
/*
* maximum possible size in TC registers. Since this is 24 bit, it's easy
*/
#define SBIC_TC_MAX ((1 << 24) - 1)
/*
* Synchronous xfer register
*/
#define SBIC_SYN_OFF_MASK 0x0f
#define SBIC_SYN_MAX_OFFSET SBIC_FIFO_DEEP
#define SBIC_SYN_PER_MASK 0x70
#define SBIC_SYN_MIN_PERIOD 2 /* upto 8, encoded as 0 */
#define SBIC_SYN(o,p) \
(((o) & SBIC_SYN_OFF_MASK) | (((p) << 4) & SBIC_SYN_PER_MASK))
/*
* Transfer count register
* optimal access macros depend on addressing
*/
/*
* Destination ID (selid) register
*/
#define SBIC_SID_SCC 0x80 /* Select command chaining (tgt) */
#define SBIC_SID_DPD 0x40 /* Data phase direction (inittor) */
#define SBIC_SID_FROM_SCSI 0x40
#define SBIC_SID_TO_SCSI 0x00
#define SBIC_SID_xxx 0x38
#define SBIC_SID_IDMASK 0x07
/*
* Source ID (rselid) register
*/
#define SBIC_RID_ER 0x80 /* Enable reselection */
#define SBIC_RID_ES 0x40 /* Enable selection */
#define SBIC_RID_DSP 0x20 /* Disable select parity */
#define SBIC_RID_SIV 0x08 /* Source ID valid */
#define SBIC_RID_MASK 0x07
/*
* Status register
*/
#define SBIC_CSR_CAUSE 0xf0
#define SBIC_CSR_RESET 0x00 /* chip was reset */
#define SBIC_CSR_CMD_DONE 0x10 /* cmd completed */
#define SBIC_CSR_CMD_STOPPED 0x20 /* interrupted or abrted*/
#define SBIC_CSR_CMD_ERR 0x40 /* end with error */
#define SBIC_CSR_BUS_SERVICE 0x80 /* REQ pending on the bus */
#define SBIC_CSR_QUALIFIER 0x0f
/* Reset State Interrupts */
#define SBIC_CSR_RESET 0x00 /* reset w/advanced features*/
#define SBIC_CSR_RESET_AM 0x01 /* reset w/advanced features*/
/* Successful Completion Interrupts */
#define SBIC_CSR_TARGET 0x10 /* reselect complete */
#define SBIC_CSR_INITIATOR 0x11 /* select complete */
#define SBIC_CSR_WO_ATN 0x13 /* tgt mode completion */
#define SBIC_CSR_W_ATN 0x14 /* ditto */
#define SBIC_CSR_XLATED 0x15 /* translate address cmd */
#define SBIC_CSR_S_XFERRED 0x16 /* initiator mode completion*/
#define SBIC_CSR_XFERRED 0x18 /* phase in low bits */
/* Paused or Aborted Interrupts */
#define SBIC_CSR_MSGIN_W_ACK 0x20 /* (I) msgin, ACK asserted*/
#define SBIC_CSR_SDP 0x21 /* (I) SDP msg received */
#define SBIC_CSR_SEL_ABRT 0x22 /* sel/resel aborted */
#define SBIC_CSR_XFR_PAUSED 0x23 /* (T) no ATN */
#define SBIC_CSR_XFR_PAUSED_ATN 0x24 /* (T) ATN is asserted */
#define SBIC_CSR_RSLT_AM 0x27 /* (I) lost selection (AM) */
#define SBIC_CSR_MIS 0x28 /* (I) xfer aborted, ph mis */
/* Terminated Interrupts */
#define SBIC_CSR_CMD_INVALID 0x40
#define SBIC_CSR_DISC 0x41 /* (I) tgt disconnected */
#define SBIC_CSR_SEL_TIMEO 0x42
#define SBIC_CSR_PE 0x43 /* parity error */
#define SBIC_CSR_PE_ATN 0x44 /* ditto, ATN is asserted */
#define SBIC_CSR_XLATE_TOOBIG 0x45
#define SBIC_CSR_RSLT_NOAM 0x46 /* (I) lost sel, no AM mode */
#define SBIC_CSR_BAD_STATUS 0x47 /* status byte was nok */
#define SBIC_CSR_MIS_1 0x48 /* ph mis, see low bits */
/* Service Required Interrupts */
#define SBIC_CSR_RSLT_NI 0x80 /* reselected, no ify msg */
#define SBIC_CSR_RSLT_IFY 0x81 /* ditto, AM mode, got ify */
#define SBIC_CSR_SLT 0x82 /* selected, no ATN */
#define SBIC_CSR_SLT_ATN 0x83 /* selected with ATN */
#define SBIC_CSR_ATN 0x84 /* (T) ATN asserted */
#define SBIC_CSR_DISC_1 0x85 /* (I) bus is free */
#define SBIC_CSR_UNK_GROUP 0x87 /* strange CDB1 */
#define SBIC_CSR_MIS_2 0x88 /* (I) ph mis, see low bits */
#define SBIC_PHASE(csr) ((csr) & PHASE_MASK)
/*
* Command register (command codes)
*/
#define SBIC_CMD_SBT 0x80 /* Single byte xfer qualifier */
#define SBIC_CMD_MASK 0x7f
/* Miscellaneous */
#define SBIC_CMD_RESET 0x00 /* (DTI) lev I */
#define SBIC_CMD_ABORT 0x01 /* (DTI) lev I */
#define SBIC_CMD_DISC 0x04 /* ( TI) lev I */
#define SBIC_CMD_SSCC 0x0d /* ( TI) lev I */
#define SBIC_CMD_SET_IDI 0x0f /* (DTI) lev I */
#define SBIC_CMD_XLATE 0x18 /* (DT ) lev II */
/* Initiator state */
#define SBIC_CMD_SET_ATN 0x02 /* ( I) lev I */
#define SBIC_CMD_CLR_ACK 0x03 /* ( I) lev I */
#define SBIC_CMD_XFER_PAD 0x19 /* ( I) lev II */
#define SBIC_CMD_XFER_INFO 0x20 /* ( I) lev II */
/* Target state */
#define SBIC_CMD_SND_DISC 0x0e /* ( T ) lev II */
#define SBIC_CMD_RCV_CMD 0x10 /* ( T ) lev II */
#define SBIC_CMD_RCV_DATA 0x11 /* ( T ) lev II */
#define SBIC_CMD_RCV_MSG_OUT 0x12 /* ( T ) lev II */
#define SBIC_CMD_RCV 0x13 /* ( T ) lev II */
#define SBIC_CMD_SND_STATUS 0x14 /* ( T ) lev II */
#define SBIC_CMD_SND_DATA 0x15 /* ( T ) lev II */
#define SBIC_CMD_SND_MSG_IN 0x16 /* ( T ) lev II */
#define SBIC_CMD_SND 0x17 /* ( T ) lev II */
/* Disconnected state */
#define SBIC_CMD_RESELECT 0x05 /* (D ) lev II */
#define SBIC_CMD_SEL_ATN 0x06 /* (D ) lev II */
#define SBIC_CMD_SEL 0x07 /* (D ) lev II */
#define SBIC_CMD_SEL_ATN_XFER 0x08 /* (D I) lev II */
#define SBIC_CMD_SEL_XFER 0x09 /* (D I) lev II */
#define SBIC_CMD_RESELECT_RECV 0x0a /* (DT ) lev II */
#define SBIC_CMD_RESELECT_SEND 0x0b /* (DT ) lev II */
#define SBIC_CMD_WAIT_SEL_RECV 0x0c /* (DT ) lev II */
/* approximate, but we won't do SBT on selects */
#define sbic_isa_select(cmd) (((cmd) > 0x5) && ((cmd) < 0xa))
#define SBIC_MACHINE_DMA_MODE SBIC_CTL_DMA
typedef struct {
bus_space_tag_t sc_sbiciot;
bus_space_handle_t sc_sbicioh;
} sbic_regmap, *sbic_regmap_p;
#define SBIC_ASR 0
#define SBIC_ADDR 0
#define SBIC_VAL 1
#define sbic_read_reg(regs,regno,val) do { \
bus_space_write_1((regs)->sc_sbiciot, (regs)->sc_sbicioh, SBIC_ADDR, \
(regno)); \
bus_space_barrier((regs)->sc_sbiciot, (regs)->sc_sbicioh, SBIC_ADDR, \
2, BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); \
(val) = bus_space_read_1((regs)->sc_sbiciot, (regs)->sc_sbicioh, \
SBIC_VAL); \
bus_space_barrier((regs)->sc_sbiciot, (regs)->sc_sbicioh, SBIC_ADDR, \
2, BUS_SPACE_BARRIER_READ); \
} while (0)
#define sbic_write_reg(regs,regno,val) do { \
bus_space_write_1((regs)->sc_sbiciot, (regs)->sc_sbicioh, SBIC_ADDR, \
(regno)); \
bus_space_barrier((regs)->sc_sbiciot, (regs)->sc_sbicioh, SBIC_ADDR, \
2, BUS_SPACE_BARRIER_WRITE); \
bus_space_write_1((regs)->sc_sbiciot, (regs)->sc_sbicioh, SBIC_VAL, \
(val)); \
bus_space_barrier((regs)->sc_sbiciot, (regs)->sc_sbicioh, SBIC_ADDR, \
2, BUS_SPACE_BARRIER_WRITE); \
} while (0)
#define SET_SBIC_myid(regs,val) sbic_write_reg(regs,SBIC_myid,val)
#define GET_SBIC_myid(regs,val) sbic_read_reg(regs,SBIC_myid,val)
#define SET_SBIC_cdbsize(regs,val) sbic_write_reg(regs,SBIC_cdbsize,val)
#define GET_SBIC_cdbsize(regs,val) sbic_read_reg(regs,SBIC_cdbsize,val)
#define SET_SBIC_control(regs,val) sbic_write_reg(regs,SBIC_control,val)
#define GET_SBIC_control(regs,val) sbic_read_reg(regs,SBIC_control,val)
#define SET_SBIC_timeo(regs,val) sbic_write_reg(regs,SBIC_timeo,val)
#define GET_SBIC_timeo(regs,val) sbic_read_reg(regs,SBIC_timeo,val)
#define SET_SBIC_cdb1(regs,val) sbic_write_reg(regs,SBIC_cdb1,val)
#define GET_SBIC_cdb1(regs,val) sbic_read_reg(regs,SBIC_cdb1,val)
#define SET_SBIC_cdb2(regs,val) sbic_write_reg(regs,SBIC_cdb2,val)
#define GET_SBIC_cdb2(regs,val) sbic_read_reg(regs,SBIC_cdb2,val)
#define SET_SBIC_cdb3(regs,val) sbic_write_reg(regs,SBIC_cdb3,val)
#define GET_SBIC_cdb3(regs,val) sbic_read_reg(regs,SBIC_cdb3,val)
#define SET_SBIC_cdb4(regs,val) sbic_write_reg(regs,SBIC_cdb4,val)
#define GET_SBIC_cdb4(regs,val) sbic_read_reg(regs,SBIC_cdb4,val)
#define SET_SBIC_cdb5(regs,val) sbic_write_reg(regs,SBIC_cdb5,val)
#define GET_SBIC_cdb5(regs,val) sbic_read_reg(regs,SBIC_cdb5,val)
#define SET_SBIC_cdb6(regs,val) sbic_write_reg(regs,SBIC_cdb6,val)
#define GET_SBIC_cdb6(regs,val) sbic_read_reg(regs,SBIC_cdb6,val)
#define SET_SBIC_cdb7(regs,val) sbic_write_reg(regs,SBIC_cdb7,val)
#define GET_SBIC_cdb7(regs,val) sbic_read_reg(regs,SBIC_cdb7,val)
#define SET_SBIC_cdb8(regs,val) sbic_write_reg(regs,SBIC_cdb8,val)
#define GET_SBIC_cdb8(regs,val) sbic_read_reg(regs,SBIC_cdb8,val)
#define SET_SBIC_cdb9(regs,val) sbic_write_reg(regs,SBIC_cdb9,val)
#define GET_SBIC_cdb9(regs,val) sbic_read_reg(regs,SBIC_cdb9,val)
#define SET_SBIC_cdb10(regs,val) sbic_write_reg(regs,SBIC_cdb10,val)
#define GET_SBIC_cdb10(regs,val) sbic_read_reg(regs,SBIC_cdb10,val)
#define SET_SBIC_cdb11(regs,val) sbic_write_reg(regs,SBIC_cdb11,val)
#define GET_SBIC_cdb11(regs,val) sbic_read_reg(regs,SBIC_cdb11,val)
#define SET_SBIC_cdb12(regs,val) sbic_write_reg(regs,SBIC_cdb12,val)
#define GET_SBIC_cdb12(regs,val) sbic_read_reg(regs,SBIC_cdb12,val)
#define SET_SBIC_tlun(regs,val) sbic_write_reg(regs,SBIC_tlun,val)
#define GET_SBIC_tlun(regs,val) sbic_read_reg(regs,SBIC_tlun,val)
#define SET_SBIC_cmd_phase(regs,val) sbic_write_reg(regs,SBIC_cmd_phase,val)
#define GET_SBIC_cmd_phase(regs,val) sbic_read_reg(regs,SBIC_cmd_phase,val)
#define SET_SBIC_syn(regs,val) sbic_write_reg(regs,SBIC_syn,val)
#define GET_SBIC_syn(regs,val) sbic_read_reg(regs,SBIC_syn,val)
#define SET_SBIC_count_hi(regs,val) sbic_write_reg(regs,SBIC_count_hi,val)
#define GET_SBIC_count_hi(regs,val) sbic_read_reg(regs,SBIC_count_hi,val)
#define SET_SBIC_count_med(regs,val) sbic_write_reg(regs,SBIC_count_med,val)
#define GET_SBIC_count_med(regs,val) sbic_read_reg(regs,SBIC_count_med,val)
#define SET_SBIC_count_lo(regs,val) sbic_write_reg(regs,SBIC_count_lo,val)
#define GET_SBIC_count_lo(regs,val) sbic_read_reg(regs,SBIC_count_lo,val)
#define SET_SBIC_selid(regs,val) sbic_write_reg(regs,SBIC_selid,val)
#define GET_SBIC_selid(regs,val) sbic_read_reg(regs,SBIC_selid,val)
#define SET_SBIC_rselid(regs,val) sbic_write_reg(regs,SBIC_rselid,val)
#define GET_SBIC_rselid(regs,val) sbic_read_reg(regs,SBIC_rselid,val)
#define SET_SBIC_csr(regs,val) sbic_write_reg(regs,SBIC_csr,val)
#define GET_SBIC_csr(regs,val) sbic_read_reg(regs,SBIC_csr,val)
#define SET_SBIC_cmd(regs,val) sbic_write_reg(regs,SBIC_cmd,val)
#define GET_SBIC_cmd(regs,val) sbic_read_reg(regs,SBIC_cmd,val)
#define SET_SBIC_data(regs,val) sbic_write_reg(regs,SBIC_data,val)
#define GET_SBIC_data(regs,val) sbic_read_reg(regs,SBIC_data,val)
#define SBIC_TC_PUT(regs,val) do { \
sbic_write_reg(regs,SBIC_count_hi,((val)>>16)); \
bus_space_write_1(regs->sc_sbiciot, regs->sc_sbicioh, SBIC_VAL, \
(val) >> 8); \
bus_space_barrier((regs)->sc_sbiciot, (regs)->sc_sbicioh, SBIC_VAL, \
1, BUS_SPACE_BARRIER_WRITE); \
bus_space_write_1(regs->sc_sbiciot, regs->sc_sbicioh, SBIC_VAL, \
(val)); \
bus_space_barrier((regs)->sc_sbiciot, (regs)->sc_sbicioh, SBIC_ADDR, \
2, BUS_SPACE_BARRIER_WRITE); \
} while (0)
#define SBIC_TC_GET(regs,val) do { \
sbic_read_reg(regs,SBIC_count_hi,(val)); \
(val) = ((val)<<8) | bus_space_read_1(regs->sc_sbiciot, \
regs->sc_sbicioh, SBIC_VAL); \
bus_space_barrier((regs)->sc_sbiciot, (regs)->sc_sbicioh, SBIC_VAL, \
1, BUS_SPACE_BARRIER_READ); \
(val) = ((val)<<8) | bus_space_read_1(regs->sc_sbiciot, \
regs->sc_sbicioh, SBIC_VAL); \
} while (0)
#define SBIC_LOAD_COMMAND(regs,cmd,cmdsize) do { \
bus_space_write_1(regs->sc_sbiciot, regs->sc_sbicioh, SBIC_ADDR, \
SBIC_cdb1); \
bus_space_barrier((regs)->sc_sbiciot, (regs)->sc_sbicioh, SBIC_ADDR, \
2, BUS_SPACE_BARRIER_WRITE); \
bus_space_write_multi_1(regs->sc_sbiciot, regs->sbic_ioh, SBIC_VAL, \
(char *)(cmd), cmdsize); \
bus_space_barrier((regs)->sc_sbiciot, (regs)->sc_sbicioh, SBIC_ADDR, \
2, BUS_SPACE_BARRIER_WRITE); \
} while (0)
#define GET_SBIC_asr(regs,val) \
(val) = bus_space_read_1((regs)->sc_sbiciot, (regs)->sc_sbicioh, \
SBIC_ASR)
#define WAIT_CIP(regs) do { \
while (bus_space_read_1(regs->sc_sbiciot, regs->sc_sbicioh, SBIC_ASR) \
& SBIC_ASR_CIP) \
; \
} while (0)
/* transmit a byte in programmed I/O mode */
#define SEND_BYTE(regs, ch) do { \
WAIT_CIP(regs); \
SET_SBIC_cmd(regs, SBIC_CMD_SBT | SBIC_CMD_XFER_INFO); \
SBIC_WAIT(regs, SBIC_ASR_DBR, 0); \
SET_SBIC_data(regs, ch); \
} while (0)
/* receive a byte in programmed I/O mode */
#define RECV_BYTE(regs, ch) do { \
WAIT_CIP(regs); \
SET_SBIC_cmd(regs, SBIC_CMD_SBT | SBIC_CMD_XFER_INFO); \
SBIC_WAIT(regs, SBIC_ASR_DBR, 0); \
GET_SBIC_data(regs, ch); \
} while (0)

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sys/arch/arm32/podulebus/sbicvar.h
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@ -1,224 +0,0 @@
/* $NetBSD: sbicvar.h,v 1.9 2001/08/14 22:58:18 rearnsha Exp $ */
/*
* Copyright (c) 1990 The Regents of the University of California.
* All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* Van Jacobson of Lawrence Berkeley Laboratory.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)scsivar.h 7.1 (Berkeley) 5/8/90
*/
#ifndef _SBICVAR_H_
#define _SBICVAR_H_
#include <sys/malloc.h>
#include <sys/callout.h>
/*
* ACB. Holds additional information for each SCSI command Comments: We
* need a separate scsi command block because we may need to overwrite it
* with a request sense command. Basicly, we refrain from fiddling with
* the scsi_xfer struct (except do the expected updating of return values).
* We'll generally update: xs->{flags,resid,error,sense,status} and
* occasionally xs->retries.
*/
struct sbic_acb {
TAILQ_ENTRY(sbic_acb) chain;
struct scsipi_xfer *xs; /* SCSI xfer ctrl block from above */
int flags; /* Status */
#define ACB_FREE 0x00
#define ACB_ACTIVE 0x01
#define ACB_DONE 0x02
#define ACB_DATAIN 0x04 /* DMA direction flag */
#define ACB_DMA 0x08 /* ACB using DMA this time */
struct scsi_generic cmd; /* SCSI command block */
int clen;
bus_dmamap_t dmamap_xfer; /* Handle for dma */
u_char *data; /* Data buffer... */
int datalen; /* ... and its length. */
int offset;
u_long sc_tcnt; /* number of bytes for this DMA */
};
/*
* Some info about each (possible) target on the SCSI bus. This should
* probably have been a "per target+lunit" structure, but we'll leave it at
* this for now. Is there a way to reliably hook it up to sc->fordriver??
*/
struct sbic_tinfo {
int cmds; /* #commands processed */
int dconns; /* #disconnects */
int touts; /* #timeouts */
int perrs; /* #parity errors */
u_char* bounce; /* Bounce buffer for this device */
ushort lubusy; /* What local units/subr. are busy? */
u_char flags;
u_char period; /* Period suggestion */
u_char offset; /* Offset suggestion */
} tinfo_t;
struct sbic_softc {
struct device sc_dev;
/* struct isr sc_isr;*/
struct callout sc_timo_ch;
struct target_sync {
u_char state;
u_char period;
u_char offset;
} sc_sync[8];
u_char target; /* Currently active target */
u_char lun;
struct scsipi_channel sc_channel;
struct scsipi_adapter sc_adapter;
sbic_regmap sc_sbicp; /* Handle for the SBIC */
volatile void *sc_cregs; /* driver specific regs */
/* Lists of command blocks */
TAILQ_HEAD(acb_list, sbic_acb) free_list,
ready_list,
nexus_list;
struct sbic_acb *sc_nexus; /* current command */
struct sbic_acb sc_acb[8]; /* the real command blocks */
struct sbic_tinfo sc_tinfo[8];
u_char sc_flags;
u_char sc_scsiaddr;
u_char sc_stat[2];
u_char sc_msg[7];
u_long sc_clkfreq;
int sc_dmaflags; /* Target-specific busdma flags */
void *sc_dmah; /* Interface specific dma handle */
bus_dma_tag_t sc_dmat; /* Tag for dma accesses */
int sc_max_dmalen; /* Maximum DMA segment length */
int sc_dmamode; /* Machine-specific DMA mode for
the SBIC chip */
u_short sc_dmatimo; /* dma timeout */
int (*sc_dmaok) (void *, bus_dma_tag_t, struct sbic_acb *);
int (*sc_dmasetup) (void *, bus_dma_tag_t, struct sbic_acb *, int);
int (*sc_dmanext) (void *, bus_dma_tag_t, struct sbic_acb *, int);
void (*sc_dmastop) (void *, bus_dma_tag_t, struct sbic_acb *);
void (*sc_dmafinish) (void *, bus_dma_tag_t, struct sbic_acb *);
void (*sc_enintr) (struct sbic_softc *);
};
/* sc_flags */
#define SBICF_ALIVE 0x01 /* controller initialized */
#define SBICF_SELECTED 0x02 /* bus is in selected state. */
#define SBICF_ICMD 0x04 /* Immediate command in execution */
#define SBICF_BADDMA 0x08 /* controller can only DMA to ztwobus space */
#define SBICF_NODMA 0x10 /* Don't use DMA */
#define SBICF_INTR 0x20 /* SBICF interrupt expected */
#define SBICF_INDMA 0x40 /* not used yet, DMA I/O in progress */
/* sync states */
#define SYNC_START 0 /* no sync handshake started */
#define SYNC_SENT 1 /* we sent sync request, no answer yet */
#define SYNC_DONE 2 /* target accepted our (or inferior) settings,
or it rejected the request and we stay
async */
#ifdef DEBUG
#define DDB_FOLLOW 0x04
#define DDB_IO 0x08
#endif
extern u_char sbic_inhibit_sync[8];
extern int sbic_no_dma;
extern int sbic_clock_override;
#define PHASE_MASK 0x07 /* mask for psns/pctl phase */
#define DATA_OUT_PHASE 0x00
#define DATA_IN_PHASE 0x01
#define CMD_PHASE 0x02
#define STATUS_PHASE 0x03
#define BUS_FREE_PHASE 0x04
#define ARB_SEL_PHASE 0x05 /* Fuji chip combines arbitration with sel. */
#define MESG_OUT_PHASE 0x06
#define MESG_IN_PHASE 0x07
#define MSG_CMD_COMPLETE 0x00
#define MSG_EXT_MESSAGE 0x01
#define MSG_SAVE_DATA_PTR 0x02
#define MSG_RESTORE_PTR 0x03
#define MSG_DISCONNECT 0x04
#define MSG_INIT_DETECT_ERROR 0x05
#define MSG_ABORT 0x06
#define MSG_REJECT 0x07
#define MSG_NOOP 0x08
#define MSG_PARITY_ERROR 0x09
#define MSG_BUS_DEVICE_RESET 0x0C
#define MSG_IDENTIFY 0x80
#define MSG_IDENTIFY_DR 0xc0 /* (disconnect/reconnect allowed) */
#define MSG_SYNC_REQ 0x01
#define MSG_ISIDENTIFY(x) (x&MSG_IDENTIFY)
#define IFY_TRN 0x20
#define IFY_LUNTRN(x) (x&0x07)
#define IFY_LUN(x) (!(x&0x20))
/* Check if high bit set */
#define STS_CHECKCOND 0x02 /* Check Condition (ie., read sense) */
#define STS_CONDMET 0x04 /* Condition Met (ie., search worked) */
#define STS_BUSY 0x08
#define STS_INTERMED 0x10 /* Intermediate status sent */
#define STS_EXT 0x80 /* Extended status valid */
/* States returned by our state machine */
#define SBIC_STATE_ERROR -1
#define SBIC_STATE_DONE 0
#define SBIC_STATE_RUNNING 1
#define SBIC_STATE_DISCONNECT 2
/*
* XXXX
*/
struct scsi_fmt_cdb {
int len; /* cdb length (in bytes) */
u_char cdb[28]; /* cdb to use on next read/write */
};
struct buf;
struct scsipi_xfer;
void sbic_minphys (struct buf *bp);
void sbic_scsi_request (struct scsipi_channel *,
scsipi_adapter_req_t, void *);
int sbicinit (struct sbic_softc *dev);
int sbicintr (struct sbic_softc *);
void sbic_dump (struct sbic_softc *dev);
#endif /* _SBICVAR_H_ */

1638
sys/arch/arm32/podulebus/sfas.c
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158
sys/arch/arm32/podulebus/sfasreg.h
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@ -1,158 +0,0 @@
/* $NetBSD: sfasreg.h,v 1.1 1996/01/31 23:26:45 mark Exp $ */
/*
* Copyright (c) 1995 Daniel Widenfalk
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Daniel Widenfalk
* for the NetBSD Project.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _SFASREG_H_
#define _SFASREG_H_
/*
* Emulex FAS216 SCSI interface hardware description.
*/
typedef volatile unsigned char vu_char;
typedef struct {
vu_char *sfas_tc_low; /* rw: Transfer count low */
vu_char *sfas_tc_mid; /* rw: Transfer count mid */
vu_char *sfas_fifo; /* rw: Data FIFO */
vu_char *sfas_command; /* rw: Chip command reg */
vu_char *sfas_dest_id; /* w: (Re)select bus ID */
#define sfas_status sfas_dest_id /* r: Status */
vu_char *sfas_timeout; /* w: (Re)select timeout */
#define sfas_interrupt sfas_timeout /* r: Interrupt */
vu_char *sfas_syncper; /* w: Synch. transfer period */
#define sfas_seqstep sfas_syncper /* r: Sequence step */
vu_char *sfas_syncoff; /* w: Synch. transfer offset */
#define sfas_fifo_flags sfas_syncoff /* r: FIFO flags */
vu_char *sfas_config1; /* rw: Config register #1 */
vu_char *sfas_clkconv; /* w: Clock conv. factor */
vu_char *sfas_test; /* w: Test register */
vu_char *sfas_config2; /* rw: Config register #2 */
vu_char *sfas_config3; /* rw: Config register #3 */
vu_char *sfas_tc_high; /* rw: Transfer count high */
vu_char *sfas_fifo_bot; /* w: FIFO bottom register */
} sfas_regmap_t;
typedef sfas_regmap_t *sfas_regmap_p;
/* Commands for the FAS216 */
#define SFAS_CMD_DMA 0x80
#define SFAS_CMD_SEL_NO_ATN 0x41
#define SFAS_CMD_SEL_ATN 0x42
#define SFAS_CMD_SEL_ATN3 0x46
#define SFAS_CMD_SEL_ATN_STOP 0x43
#define SFAS_CMD_ENABLE_RESEL 0x44
#define SFAS_CMD_DISABLE_RESEL 0x45
#define SFAS_CMD_TRANSFER_INFO 0x10
#define SFAS_CMD_TRANSFER_PAD 0x98
#define SFAS_CMD_COMMAND_COMPLETE 0x11
#define SFAS_CMD_MESSAGE_ACCEPTED 0x12
#define SFAS_CMD_SET_ATN 0x1A
#define SFAS_CMD_RESET_ATN 0x1B
#define SFAS_CMD_NOP 0x00
#define SFAS_CMD_FLUSH_FIFO 0x01
#define SFAS_CMD_RESET_CHIP 0x02
#define SFAS_CMD_RESET_SCSI_BUS 0x03
#define SFAS_STAT_PHASE_MASK 0x07
#define SFAS_STAT_PHASE_TRANS_CPLT 0x08
#define SFAS_STAT_TRANSFER_COUNT_ZERO 0x10
#define SFAS_STAT_PARITY_ERROR 0x20
#define SFAS_STAT_GROSS_ERROR 0x40
#define SFAS_STAT_INTERRUPT_PENDING 0x80
#define SFAS_PHASE_DATA_OUT 0
#define SFAS_PHASE_DATA_IN 1
#define SFAS_PHASE_COMMAND 2
#define SFAS_PHASE_STATUS 3
#define SFAS_PHASE_MESSAGE_OUT 6
#define SFAS_PHASE_MESSAGE_IN 7
#define SFAS_DEST_ID_MASK 0x07
#define SFAS_INT_SELECTED 0x01
#define SFAS_INT_SELECTED_WITH_ATN 0x02
#define SFAS_INT_RESELECTED 0x04
#define SFAS_INT_FUNCTION_COMPLETE 0x08
#define SFAS_INT_BUS_SERVICE 0x10
#define SFAS_INT_DISCONNECT 0x20
#define SFAS_INT_ILLEGAL_COMMAND 0x40
#define SFAS_INT_SCSI_RESET_DETECTED 0x80
#define SFAS_SYNCHRON_PERIOD_MASK 0x1F
#define SFAS_FIFO_COUNT_MASK 0x1F
#define SFAS_FIFO_SEQUENCE_STEP_MASK 0xE0
#define SFAS_FIFO_SEQUENCE_SHIFT 5
#define SFAS_SYNCHRON_OFFSET_MASK 0x0F
#define SFAS_SYNC_ASSERT_MASK 0x30
#define SFAS_SYNC_ASSERT_SHIFT 4
#define SFAS_SYNC_DEASSERT_MASK 0x30
#define SFAS_SYNC_DEASSERT_SHIFT 6
#define SFAS_CFG1_BUS_ID_MASK 0x07
#define SFAS_CFG1_CHIP_TEST_MODE 0x08
#define SFAS_CFG1_SCSI_PARITY_ENABLE 0x10
#define SFAS_CFG1_PARITY_TEST_MODE 0x20
#define SFAS_CFG1_SCSI_RES_INT_DIS 0x40
#define SFAS_CFG1_SLOW_CABLE_MODE 0x80
#define SFAS_CLOCK_CONVERSION_MASK 0x07
#define SFAS_TEST_TARGET_TEST_MODE 0x01
#define SFAS_TEST_INITIATOR_TEST_MODE 0x02
#define SFAS_TEST_TRISTATE_TEST_MODE 0x04
#define SFAS_CFG2_DMA_PARITY_ENABLE 0x01
#define SFAS_CFG2_REG_PARITY_ENABLE 0x02
#define SFAS_CFG2_TARG_BAD_PARITY_ABORT 0x04
#define SFAS_CFG2_SCSI_2_MODE 0x08
#define SFAS_CFG2_TRISTATE_DMA_REQ 0x10
#define SFAS_CFG2_BYTE_CONTROL_MODE 0x20
#define SFAS_CFG2_FEATURES_ENABLE 0x40
#define SFAS_CFG2_RESERVE_FIFO_BYTE 0x80
#define SFAS_CFG3_THRESHOLD_8_MODE 0x01
#define SFAS_CFG3_ALTERNATE_DMA_MODE 0x02
#define SFAS_CFG3_SAVE_RESIDUAL_BYTE 0x04
#define SFAS_CFG3_FASTCLK 0x08
#define SFAS_CFG3_FASTSCSI 0x10
#define SFAS_CFG3_CDB10 0x20
#define SFAS_CFG3_QENB 0x40
#define SFAS_CFG3_IDRESCHK 0x80
#endif

267
sys/arch/arm32/podulebus/sfasvar.h
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@ -1,267 +0,0 @@
/* $NetBSD: sfasvar.h,v 1.9 2001/06/12 15:17:18 wiz Exp $ */
/*
* Copyright (c) 1995 Daniel Widenfalk
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Daniel Widenfalk
* for the NetBSD Project.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _SFASVAR_H_
#define _SFASVAR_H_
#ifndef _SFASREG_H_
#include <arm32/podulebus/sfasreg.h>
#endif
/*
* MAXCHAIN is the anticipated maximum number of chain blocks needed. This
* assumes that we are NEVER requested to transfer more than MAXPHYS bytes.
*/
#define MAXCHAIN (MAXPHYS/NBPG+2)
/*
* Maximum number of requests standing by. Could be anything, but I think 9
* looks nice :-) NOTE: This does NOT include requests already started!
*/
#define MAXPENDING 9 /* 7 IDs + 2 extra */
/*
* DMA chain block. If flg == SFAS_CHAIN_PRG or flg == SFAS_CHAIN_BUMP then
* ptr is a VIRTUAL adress. If flg == SFAS_CHAIN_DMA then ptr is a PHYSICAL
* adress.
*/
struct sfas_dma_chain {
vm_offset_t ptr;
u_short len;
short flg;
};
#define SFAS_CHAIN_DMA 0x00
#define SFAS_CHAIN_BUMP 0x01
#define SFAS_CHAIN_PRG 0x02
/*
* This struct contains the necessary info for a pending request. Pointer to
* a scsipi_xfer struct.
*/
struct sfas_pending {
TAILQ_ENTRY(sfas_pending) link;
struct scsipi_xfer *xs;
};
/*
* nexus contains all active data for one SCSI unit. Parts of the info in this
* struct survives between scsi commands.
*/
struct nexus {
struct scsipi_xfer *xs; /* Pointer to request */
u_char ID; /* ID message to be sent */
u_char clen; /* scsi command length + */
u_char cbuf[14]; /* the actual command bytes */
struct sfas_dma_chain dma[MAXCHAIN]; /* DMA chain blocks */
short max_link; /* Maximum used of above */
short cur_link; /* Currently handled block */
u_char *buf; /* Virtual adress of data */
int len; /* Bytes left to transfer */
vm_offset_t dma_buf; /* Current DMA adress */
int dma_len; /* Current DMA length */
vm_offset_t dma_blk_ptr; /* Current chain adress */
int dma_blk_len; /* Current chain length */
u_char dma_blk_flg; /* Current chain flags */
u_char state; /* Nexus state, see below */
u_short flags; /* Nexus flags, see below */
short period; /* Sync period to request */
u_char offset; /* Sync offset to request */
u_char syncper; /* FAS216 variable storage */
u_char syncoff; /* FAS216 variable storage */
u_char config3; /* FAS216 variable storage */
u_char lun_unit; /* (Lun<<4) | Unit of nexus */
u_char status; /* Status byte from unit*/
};
/* SCSI nexus_states */
#define SFAS_NS_IDLE 0 /* Nexus idle */
#define SFAS_NS_SELECTED 1 /* Last command was a SELECT command */
#define SFAS_NS_DATA_IN 2 /* Last command was a TRANSFER_INFO */
/* command during a data in phase */
#define SFAS_NS_DATA_OUT 3 /* Last command was a TRANSFER_INFO */
/* command during a data out phase */
#define SFAS_NS_STATUS 4 /* We have send a COMMAND_COMPLETE */
/* command and are awaiting status */
#define SFAS_NS_MSG_IN 5 /* Last phase was MESSAGE IN */
#define SFAS_NS_MSG_OUT 6 /* Last phase was MESSAGE OUT */
#define SFAS_NS_SVC 7 /* We have sent the command */
#define SFAS_NS_DISCONNECTING 8 /* We have received a disconnect msg */
#define SFAS_NS_DISCONNECTED 9 /* We are disconnected */
#define SFAS_NS_RESELECTED 10 /* We was reselected */
#define SFAS_NS_DONE 11 /* Done. Prephsase to FINISHED */
#define SFAS_NS_FINISHED 12 /* Realy done. Call scsi_done */
#define SFAS_NS_RESET 13 /* We are reseting this unit */
/* SCSI nexus flags */
#define SFAS_NF_UNIT_BUSY 0x0001 /* Unit is not available */
#define SFAS_NF_SELECT_ME 0x0002 /* Nexus is set up, waiting for bus */
#define SFAS_NF_HAS_MSG 0x0010 /* We have received a complete msg */
#define SFAS_NF_DO_SDTR 0x0020 /* We should send a SDTR */
#define SFAS_NF_SDTR_SENT 0x0040 /* We have sent a SDTR */
#define SFAS_NF_SYNC_TESTED 0x0080 /* We have negotiated sync */
#define SFAS_NF_RESET 0x0100 /* Reset this nexus */
#define SFAS_NF_IMMEDIATE 0x0200 /* We are operating from sfasicmd */
#define SFAS_NF_RETRY_SELECT 0x1000 /* Selection needs retrying */
#define SFAS_NF_DEBUG 0x8000 /* As it says: DEBUG */
struct sfas_softc {
struct device sc_dev; /* System required struct */
struct scsipi_channel sc_channel;
struct scsipi_adapter sc_adapter;
void *sc_ih;
struct evcnt sc_intrcnt;
TAILQ_HEAD(,sfas_pending) sc_xs_pending;
TAILQ_HEAD(,sfas_pending) sc_xs_free;
struct sfas_pending sc_xs_store[MAXPENDING];
sfas_regmap_p sc_fas; /* FAS216 Address */
void *sc_spec; /* Board-specific data */
u_char *sc_bump_va; /* Bumpbuf virtual adr */
vm_offset_t sc_bump_pa; /* Bumpbuf physical adr */
int sc_bump_sz; /* Bumpbuf size */
/* Configuration registers, must be set BEFORE sfasinitialize */
u_char sc_clock_freq;
u_short sc_timeout;
u_char sc_host_id;
u_char sc_config_flags;
/* Generic DMA functions */
int (*sc_setup_dma)();
int (*sc_build_dma_chain)();
int (*sc_need_bump)();
/* Optional replacement ixfer */
void (*sc_ixfer)();
/* Generic Led data */
int sc_led_status;
void (*sc_led)();
/* Nexus list */
struct nexus sc_nexus[8];
struct nexus *sc_cur_nexus;
struct nexus *sc_sel_nexus;
/* Current transfer data */
u_char *sc_buf; /* va */
int sc_len;
vm_offset_t sc_dma_buf; /* pa */
int sc_dma_len;
vm_offset_t sc_dma_blk_ptr;
int sc_dma_blk_len;
short sc_dma_blk_flg;
struct sfas_dma_chain *sc_chain; /* Current DMA chain */
short sc_max_link;
short sc_cur_link;
/* Interrupt registers */
u_char sc_status;
u_char sc_interrupt;
u_char sc_resel[2];
u_char sc_units_disconnected;
/* Storage for FAS216 config registers (current values) */
u_char sc_config1;
u_char sc_config2;
u_char sc_config3;
u_char sc_clock_conv_fact;
u_char sc_timeout_val;
u_char sc_clock_period;
u_char sc_msg_in[7];
u_char sc_msg_in_len;
u_char sc_msg_out[7];
u_char sc_msg_out_len;
u_char sc_unit;
u_char sc_lun;
u_char sc_flags;
};
#define SFAS_DMA_READ 0
#define SFAS_DMA_WRITE 1
#define SFAS_DMA_CLEAR 2
/* sc_flags */
#define SFAS_ACTIVE 0x01
#define SFAS_DONT_WAIT 0x02
/* SCSI Selection modes */
#define SFAS_SELECT 0x00 /* Normal selection: No sync, no resel */
#define SFAS_SELECT_R 0x01 /* Reselection allowed */
#define SFAS_SELECT_S 0x02 /* Synchronous transfer allowed */
#define SFAS_SELECT_I 0x04 /* Selection for sfasicmd */
#define SFAS_SELECT_K 0x08 /* Send a BUS DEVICE RESET message (Kill) */
/* Nice abbreviations of the above */
#define SFAS_SELECT_RS (SFAS_SELECT_R|SFAS_SELECT_S)
#define SFAS_SELECT_RI (SFAS_SELECT_R|SFAS_SELECT_I)
#define SFAS_SELECT_SI (SFAS_SELECT_S|SFAS_SELECT_I)
#define SFAS_SELECT_RSI (SFAS_SELECT_R|SFAS_SELECT_S|SFAS_SELECT_I)
/* sc_config_flags */
#define SFAS_NO_SYNCH 0x01 /* Disable synchronous transfer */
#define SFAS_NO_DMA 0x02 /* Do not use DMA! EVER! */
#define SFAS_NO_RESELECT 0x04 /* Do not allow relesection */
#define SFAS_SLOW_CABLE 0x08 /* Cable is "unsafe" for fast scsi-2 */
#define SFAS_SLOW_START 0x10 /* There are slow starters on the bus */
void sfasinitialize __P((struct sfas_softc *sc));
void sfas_minphys __P((struct buf *bp));
void sfas_scsi_request __P((struct scsipi_channel *,
scsipi_adapter_req_t, void *));
void sfasintr __P((struct sfas_softc *dev));
#endif /* _SFASVAR_H_ */

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sys/arch/arm32/podulebus/simide.c
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/* $NetBSD: simide.c,v 1.12 2001/03/17 20:34:45 bjh21 Exp $ */
/*
* Copyright (c) 1997-1998 Mark Brinicombe
* Copyright (c) 1997-1998 Causality Limited
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Mark Brinicombe
* for the NetBSD Project.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Card driver and probe and attach functions to use generic IDE driver
* for the Simtec IDE podule
*/
/*
* Thanks to Gareth Simpson, Simtec Electronics for providing
* the hardware information
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/conf.h>
#include <sys/device.h>
#include <sys/malloc.h>
#include <machine/irqhandler.h>
#include <machine/io.h>
#include <machine/bus.h>
#include <arm32/podulebus/podulebus.h>
#include <arm32/podulebus/simidereg.h>
#include <dev/ata/atavar.h>
#include <dev/ic/wdcvar.h>
#include <dev/podulebus/podules.h>
/*
* Simtec IDE podule device.
*
* This probes and attaches the top level Simtec IDE device to the podulebus.
* It then configures any children of the Simtec IDE device.
* The attach args specify whether it is configuring the primary or
* secondary channel.
* The children are expected to be wdc devices using simide attachments.
*/
/*
* Simtec IDE card softc structure.
*
* Contains the device node, podule information and global information
* required by the driver such as the card version and the interrupt mask.
*/
struct simide_softc {
struct wdc_softc sc_wdcdev; /* common wdc definitions */
struct channel_softc *wdc_chanarray[2]; /* channels definition */
podule_t *sc_podule; /* Our podule info */
int sc_podule_number; /* Our podule number */
int sc_ctl_reg; /* Global ctl reg */
int sc_version; /* Card version */
bus_space_tag_t sc_ctliot; /* Bus tag */
bus_space_handle_t sc_ctlioh; /* control handle */
struct bus_space sc_tag; /* custom tag */
struct simide_channel {
struct channel_softc wdc_channel; /* generic part */
irqhandler_t sc_ih; /* interrupt handler */
int sc_irqmask; /* IRQ mask for this channel */
} simide_channels[2];
};
int simide_probe __P((struct device *, struct cfdata *, void *));
void simide_attach __P((struct device *, struct device *, void *));
void simide_shutdown __P((void *arg));
int simide_intr __P((void *arg));
struct cfattach simide_ca = {
sizeof(struct simide_softc), simide_probe, simide_attach
};
/*
* Define prototypes for custom bus space functions.
*/
bs_rm_2_proto(simide);
bs_wm_2_proto(simide);
/*
* Create an array of address structures. These define the addresses and
* masks needed for the different channels.
*
* index = channel
*/
struct {
u_int drive_registers;
u_int aux_register;
u_int irq_mask;
} simide_info[] = {
{ PRIMARY_DRIVE_REGISTERS_POFFSET, PRIMARY_AUX_REGISTER_POFFSET,
CONTROL_PRIMARY_IRQ },
{ SECONDARY_DRIVE_REGISTERS_POFFSET, SECONDARY_AUX_REGISTER_POFFSET,
CONTROL_SECONDARY_IRQ }
};
/*
* Card probe function
*
* Just match the manufacturer and podule ID's
*/
int
simide_probe(parent, cf, aux)
struct device *parent;
struct cfdata *cf;
void *aux;
{
struct podule_attach_args *pa = (void *)aux;
if (matchpodule(pa, MANUFACTURER_SIMTEC, PODULE_SIMTEC_IDE, -1) == 0)
return(0);
return(1);
}
/*
* Card attach function
*
* Identify the card version and configure any children.
* Install a shutdown handler to kill interrupts on shutdown
*/
void
simide_attach(parent, self, aux)
struct device *parent, *self;
void *aux;
{
struct simide_softc *sc = (void *)self;
struct podule_attach_args *pa = (void *)aux;
int status;
u_int iobase;
int channel;
struct simide_channel *scp;
struct channel_softc *cp;
irqhandler_t *ihp;
/* Note the podule number and validate */
if (pa->pa_podule_number == -1)
panic("Podule has disappeared !");
sc->sc_podule_number = pa->pa_podule_number;
sc->sc_podule = pa->pa_podule;
podules[sc->sc_podule_number].attached = 1;
/*
* Ok we need our own bus tag as the register spacing
* is not the default.
*
* For the podulebus the bus tag cookie is the shift
* to apply to registers
* So duplicate the bus space tag and change the
* cookie.
*
* Also while we are at it replace the default
* read/write mulitple short functions with
* optimised versions
*/
sc->sc_tag = *pa->pa_iot;
sc->sc_tag.bs_cookie = (void *) DRIVE_REGISTER_SPACING_SHIFT;
sc->sc_tag.bs_rm_2 = simide_bs_rm_2;
sc->sc_tag.bs_wm_2 = simide_bs_wm_2;
sc->sc_ctliot = pa->pa_iot;
/* Obtain bus space handles for all the control registers */
if (bus_space_map(sc->sc_ctliot, pa->pa_podule->mod_base +
CONTROL_REGISTERS_POFFSET, CONTROL_REGISTER_SPACE, 0,
&sc->sc_ctlioh))
panic("%s: Cannot map control registers\n", self->dv_xname);
/* Install a clean up handler to make sure IRQ's are disabled */
if (shutdownhook_establish(simide_shutdown, (void *)sc) == NULL)
panic("%s: Cannot install shutdown handler", self->dv_xname);
/* Set the interrupt info for this podule */
sc->sc_podule->irq_addr = pa->pa_podule->mod_base
+ CONTROL_REGISTERS_POFFSET + (CONTROL_REGISTER_OFFSET << 2);
sc->sc_podule->irq_mask = STATUS_IRQ;
sc->sc_ctl_reg = 0;
status = bus_space_read_1(sc->sc_ctliot, sc->sc_ctlioh,
STATUS_REGISTER_OFFSET);
printf(":");
/* If any of the bits in STATUS_FAULT are zero then we have a fault. */
if ((status & STATUS_FAULT) != STATUS_FAULT)
printf(" card/cable fault (%02x) -", status);
if (!(status & STATUS_RESET))
printf(" (reset)");
if (!(status & STATUS_ADDR_TEST))
printf(" (addr)");
if (!(status & STATUS_CS_TEST))
printf(" (cs)");
if (!(status & STATUS_RW_TEST))
printf(" (rw)");
printf("\n");
/* Perhaps we should just abort at this point. */
/* if ((status & STATUS_FAULT) != STATUS_FAULT)
return;*/
/*
* Enable IDE, Obey IORDY and disabled slow mode
*/
sc->sc_ctl_reg |= CONTROL_IDE_ENABLE | CONTROL_IORDY
| CONTROL_SLOW_MODE_OFF;
bus_space_write_1(sc->sc_ctliot, sc->sc_ctlioh,
CONTROL_REGISTER_OFFSET, sc->sc_ctl_reg);
/* Fill in wdc and channel infos */
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16;
sc->sc_wdcdev.PIO_cap = 0;
sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc->sc_wdcdev.nchannels = 2;
for (channel = 0 ; channel < 2; channel++) {
scp = &sc->simide_channels[channel];
sc->wdc_chanarray[channel] = &scp->wdc_channel;
cp = &scp->wdc_channel;
cp->channel = channel;
cp->wdc = &sc->sc_wdcdev;
cp->ch_queue = malloc(sizeof(struct channel_queue),
M_DEVBUF, M_NOWAIT);
if (cp->ch_queue == NULL) {
printf("%s %s channel: can't allocate memory for "
"command queue", self->dv_xname,
(channel == 0) ? "primary" : "secondary");
continue;
}
cp->cmd_iot = cp->ctl_iot = &sc->sc_tag;
iobase = pa->pa_podule->mod_base;
if (bus_space_map(cp->cmd_iot, iobase +
simide_info[channel].drive_registers,
DRIVE_REGISTERS_SPACE, 0, &cp->cmd_ioh))
continue;
if (bus_space_map(cp->ctl_iot, iobase +
simide_info[channel].aux_register, 4, 0, &cp->ctl_ioh)) {
bus_space_unmap(cp->cmd_iot, cp->cmd_ioh,
DRIVE_REGISTERS_SPACE);
continue;
}
/* Disable interrupts and clear any pending interrupts */
scp->sc_irqmask = simide_info[channel].irq_mask;
sc->sc_ctl_reg &= ~scp->sc_irqmask;
bus_space_write_1(sc->sc_ctliot, sc->sc_ctlioh,
CONTROL_REGISTER_OFFSET, sc->sc_ctl_reg);
wdcattach(cp);
ihp = &scp->sc_ih;
ihp->ih_func = simide_intr;
ihp->ih_arg = scp;
ihp->ih_level = IPL_BIO;
ihp->ih_name = "simide";
ihp->ih_maskaddr = pa->pa_podule->irq_addr;
ihp->ih_maskbits = scp->sc_irqmask;
if (irq_claim(sc->sc_podule->interrupt, ihp))
panic("%s: Cannot claim interrupt %d\n",
self->dv_xname, sc->sc_podule->interrupt);
/* clear any pending interrupts and enable interrupts */
sc->sc_ctl_reg |= scp->sc_irqmask;
bus_space_write_1(sc->sc_ctliot, sc->sc_ctlioh,
CONTROL_REGISTER_OFFSET, sc->sc_ctl_reg);
}
}
/*
* Card shutdown function
*
* Called via do_shutdown_hooks() during kernel shutdown.
* Clear the cards's interrupt mask to stop any podule interrupts.
*/
void
simide_shutdown(arg)
void *arg;
{
struct simide_softc *sc = arg;
sc->sc_ctl_reg &= (CONTROL_PRIMARY_IRQ | CONTROL_SECONDARY_IRQ);
/* Disable card interrupts */
bus_space_write_1(sc->sc_ctliot, sc->sc_ctlioh,
CONTROL_REGISTER_OFFSET, sc->sc_ctl_reg);
}
/*
* Podule interrupt handler
*
* If the interrupt was from our card pass it on to the wdc interrupt handler
*/
int
simide_intr(arg)
void *arg;
{
struct simide_channel *scp = arg;
irqhandler_t *ihp = &scp->sc_ih;
volatile u_char *intraddr = (volatile u_char *)ihp->ih_maskaddr;
/* XXX - not bus space yet - should really be handled by podulebus */
if ((*intraddr) & ihp->ih_maskbits)
wdcintr(&scp->wdc_channel);
return(0);
}

60
sys/arch/arm32/podulebus/simide_io_asm.S
View File

@ -1,60 +0,0 @@
/* $NetBSD: simide_io_asm.S,v 1.5 1999/10/26 06:53:44 cgd Exp $ */
/*
* Copyright (c) 1997 Mark Brinicombe.
* Copyright (c) 1997 Causality Limited.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Mark Brinicombe
* for the NetBSD Project.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <machine/asm.h>
/*
* Custom bus_space I/O functions for Simtec IDE podule
*/
/*
* Fast read multiple
*/
ENTRY(simide_bs_rm_2)
add r0, r1, r2, lsl r0
mov r1, r3
ldr r2, [sp, #0]
b _C_LABEL(inswm8)
/*
* Fast write multiple
*/
ENTRY(simide_bs_wm_2)
add r0, r1, r2, lsl r0
mov r1, r3
ldr r2, [sp, #0]
b _C_LABEL(outswm8)

78
sys/arch/arm32/podulebus/simidereg.h
View File

@ -1,78 +0,0 @@
/* $NetBSD: simidereg.h,v 1.2 1998/09/22 00:40:38 mark Exp $ */
/*
* Copyright (c) 1997 Mark Brinicombe
* Copyright (c) 1997 Causality Limited
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Mark Brinicombe
* for the NetBSD Project.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Thanks to Gareth Simpson, Simtec Electronics for providing
* the hardware information.
*/
/*
* Registers and address offsets for the Simtec IDE card.
*/
/* IDE drive registers */
#define PRIMARY_DRIVE_REGISTERS_POFFSET 0x0000
#define PRIMARY_AUX_REGISTER_POFFSET 0x0700
#define SECONDARY_DRIVE_REGISTERS_POFFSET 0x1000
#define SECONDARY_AUX_REGISTER_POFFSET 0x1700
#define DRIVE_REGISTERS_SPACE 0x800
#define DRIVE_REGISTER_BYTE_SPACING 128
#define DRIVE_REGISTER_SPACING_SHIFT 7
/* Other registers */
#define CONTROL_REGISTERS_POFFSET 0x2000
#define CONTROL_REGISTER_SPACE 8
#define CONTROL_REGISTER_OFFSET 0
#define CONTROL_RESET 0x80
#define CONTROL_IORDY 0x40
#define CONTROL_8_BIT 0x20
#define CONTROL_IDE_ENABLE 0x10
#define CONTROL_SLOW_MODE_OFF 0x08
#define CONTROL_ROM_WRITE 0x04
#define CONTROL_SECONDARY_IRQ 0x02
#define CONTROL_PRIMARY_IRQ 0x01
#define STATUS_REGISTER_OFFSET 1
#define STATUS_RESET 0x80
#define STATUS_IORDY 0x40
#define STATUS_ADDR_TEST 0x20
#define STATUS_CS_TEST 0x10
#define STATUS_RW_TEST 0x08
#define STATUS_IRQ 0x01
#define STATUS_FAULT (STATUS_ADDR_TEST | STATUS_CS_TEST \
| STATUS_RW_TEST | STATUS_RESET)

947
sys/arch/arm32/rc7500/if_es.c
View File

@ -1,947 +0,0 @@
/* $NetBSD: if_es.c,v 1.19 2001/02/24 20:11:08 reinoud Exp $ */
/*
* Copyright (c) 1996, Danny C Tsen.
* Copyright (c) 1996, VLSI Technology Inc. All Rights Reserved.
* Copyright (c) 1995 Michael L. Hitch
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Michael L. Hitch.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Modified from Amiga's es driver for SMC 91C9x ethernet controller.
*/
/*
* SMC 91C90 Single-Chip Ethernet Controller
*/
#include "opt_ddb.h"
#include "opt_inet.h"
#include "opt_ns.h"
#include "bpfilter.h"
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/mbuf.h>
#include <sys/buf.h>
#include <sys/protosw.h>
#include <sys/socket.h>
#include <sys/syslog.h>
#include <sys/ioctl.h>
#include <sys/errno.h>
#include <sys/device.h>
#include <net/if.h>
#include <net/if_dl.h>
#include <net/if_ether.h>
#ifdef INET
#include <netinet/in.h>
#include <netinet/in_systm.h>
#include <netinet/in_var.h>
#include <netinet/ip.h>
#include <netinet/if_inarp.h>
#endif
#ifdef NS
#include <netns/ns.h>
#include <netns/ns_if.h>
#endif
#include <machine/cpu.h>
#include <machine/irqhandler.h>
#include <machine/io.h>
#include <machine/katelib.h>
#include <arm32/rc7500/if_esreg.h>
#include <arm/mainbus/mainbus.h>
#include "locators.h"
#define SWAP(x) (((x & 0xff) << 8) | ((x >> 8) & 0xff))
/*
* Ethernet software status per interface.
*
* Each interface is referenced by a network interface structure,
* es_if, which the routing code uses to locate the interface.
* This structure contains the output queue for the interface, its address, ...
*/
struct es_softc {
struct device sc_dev;
irqhandler_t sc_ih;
struct ethercom sc_ethercom; /* common Ethernet structures */
u_int sc_base; /* base address of board */
int nrxovrn;
u_int sc_intctl;
u_char pktbuf[1530];
#ifdef ESDEBUG
int sc_debug;
int sc_intbusy;
int sc_smcbusy;
#endif
};
#if NBPFILTER > 0
#include <net/bpf.h>
#include <net/bpfdesc.h>
#endif
#ifdef ESDEBUG
/* console error messages */
int esdebug = 0;
int estxints = 0; /* IST_TX with TX enabled */
int estxint2 = 0; /* IST_TX active after IST_TX_EMPTY */
int estxint3 = 0; /* IST_TX interrupt processed */
int estxint4 = 0; /* ~TEMPTY counts */
int estxint5 = 0; /* IST_TX_EMPTY interrupts */
#endif
static int esintr __P((void *));
static void estint __P((struct ifnet *));
static void esstart __P((struct ifnet *));
static void eswatchdog __P((struct ifnet *));
static int esioctl __P((struct ifnet *, u_long, caddr_t));
static void esrint __P((struct es_softc *));
static void esinit __P((struct es_softc *));
static void esreset __P((struct es_softc *));
int esprobe __P((struct device *, struct cfdata *, void *));
void esattach __P((struct device *, struct device *, void *));
struct cfattach es_ca = {
sizeof(struct es_softc), esprobe, esattach
};
int
esprobe(parent, match, aux)
struct device *parent;
struct cfdata *match;
void *aux;
{
struct mainbus_attach_args *mb = aux;
/* We need a base address */
if (mb->mb_iobase == MAINBUSCF_BASE_DEFAULT)
return(0);
/*
* This is a driver for the ethernet controller on the RC7500 motherboard.
* It would be nice to be able to probe rather that using conditional
* compilation. Alternatively we should probe for the RC7500 and
* use a flag for that to enable the driver.
*/
#ifdef RC7500
return(1);
#else
return(0);
#endif
}
/*
* Interface exists: make available by filling in network interface
* record. System will initialize the interface when it is ready
* to accept packets.
*/
/*
* XXX - FIX ME
* fake an Ethernet address.
*/
unsigned long vendor_id = 0x007f00; /* just make one */
void
esattach(parent, self, aux)
struct device *parent, *self;
void *aux;
{
struct es_softc *sc = (void *)self;
struct mainbus_attach_args *mbap = aux;
struct ifnet *ifp = &sc->sc_ethercom.ec_if;
unsigned long ser;
u_int8_t myaddr[ETHER_ADDR_LEN];
sc->sc_base = mbap->mb_iobase;
ser = 0x5B98FF;
/*
* Manufacturer decides the 3 first bytes, i.e. ethernet vendor ID.
* (Currently only Ameristar.)
*/
myaddr[0] = (vendor_id >> 16) & 0xff;
myaddr[1] = (vendor_id >> 8) & 0xff;
myaddr[2] = vendor_id & 0xff;
/*
* XXX We should have a serial number on board!!!!
* Serial number for board contains last 3 bytes.
*/
myaddr[3] = (ser >> 16) & 0xff;
myaddr[4] = (ser >> 8) & 0xff;
myaddr[5] = (ser ) & 0xff;
/* Initialize ifnet structure. */
bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
ifp->if_softc = sc;
ifp->if_ioctl = esioctl;
ifp->if_start = estint;
ifp->if_watchdog = eswatchdog;
/* XXX IFF_MULTICAST */
ifp->if_flags = IFF_BROADCAST | IFF_MULTICAST | IFF_NOTRAILERS;
/* Attach the interface. */
if_attach(ifp);
ether_ifattach(ifp, myaddr);
/* Print additional info when attached. */
printf(": address %s\n", ether_sprintf(myaddr));
sc->sc_ih.ih_func = esintr;
sc->sc_ih.ih_arg = sc;
sc->sc_ih.ih_level = IPL_NET;
if (irq_claim(IRQ_ETHERNET, &sc->sc_ih) == -1)
panic("Cannot installed SMC 91C9x Ethernet IRQ handler\n");
}
#ifdef ESDEBUG
static void
es_dump_smcregs(where, smc)
char *where;
union smcregs *smc;
{
u_int cur_bank = smc->b0.bsr & BSR_BANKMSK;
printf("SMC registers %08x from %s bank %04x\n", smc, where,
smc->b0.bsr);
smc->b0.bsr = BSR_BANK0;
printf("TCR %04x EPHSR %04x RCR %04x ECR %04x MIR %04x MCR %04x\n",
smc->b0.tcr, smc->b0.ephsr, smc->b0.rcr,
smc->b0.ecr, smc->b0.mir, smc->b0.mcr);
smc->b1.bsr = BSR_BANK1;
printf("CR %04x BAR %04x IAR %04x %04x %04x GPR %04x CTR %04x\n",
smc->b1.cr, smc->b1.bar, smc->b1.iar[0], smc->b1.iar[1],
smc->b1.iar[2], smc->b1.gpr, smc->b1.ctr);
smc->b2.bsr = BSR_BANK2;
printf("MMUCR %04x PNR %02x ARR %02x FIFO %04x PTR %04x",
smc->b2.mmucr, smc->b2.pnr, smc->b2.arr, smc->b2.fifo,
smc->b2.ptr);
printf(" DATA %04x %04x IST %02x MSK %02x\n", smc->b2.data,
smc->b2.datax, smc->b2.ist, smc->b2.msk);
smc->b3.bsr = BSR_BANK3;
printf("MT %04x %04x %04x %04x\n",
smc->b3.mt[0], smc->b3.mt[1], smc->b3.mt[2], smc->b3.mt[3]);
smc->b3.bsr = cur_bank;
}
#endif
static void
esstop(sc)
struct es_softc* sc;
{
}
static void
esinit(sc)
struct es_softc *sc;
{
struct ifnet *ifp = &sc->sc_ethercom.ec_if;
u_int iobase = sc->sc_base;
int s;
s = splnet();
#ifdef ESDEBUG
if (ifp->if_flags & IFF_RUNNING)
es_dump_smcregs("esinit", smc);
#endif
outl(iobase + BANKSEL, BSR_BANK0);
outl(iobase + B0RCR, RCR_EPH_RST);
outl(iobase + B0RCR, 0);
/*
* clear Multicast table
*/
outl(iobase + BANKSEL, BSR_BANK3);
outl(iobase + B3MT0, 0);
outl(iobase + B3MT2, 0);
outl(iobase + B3MT4, 0);
outl(iobase + B3MT6, 0);
/* XXX set Multicast table from Multicast list */
outl(iobase + BANKSEL, BSR_BANK1);
outl(iobase + B1CR, (CR_ALLONES | CR_NO_WAIT_ST | CR_16BIT));
outl(iobase + B1CTR, CTR_AUTO_RLSE);
outl(iobase + B1IAR1, *((u_short *) &LLADDR(ifp->if_sadl)[0]));
outl(iobase + B1IAR3, *((u_short *) &LLADDR(ifp->if_sadl)[2]));
outl(iobase + B1IAR5, *((u_short *) &LLADDR(ifp->if_sadl)[4]));
outl(iobase + BANKSEL, BSR_BANK2);
outl(iobase + B2MMUCR, MMUCR_RESET);
outl(iobase + BANKSEL, BSR_BANK0);
outl(iobase + B0MCR, 0); /* reserve 0 x 256 bytes for transmit buffers */
outl(iobase + B0TCR, (TCR_PAD_EN | TCR_TXENA | TCR_MON_CSN | TCR_FDUPLX));
outl(iobase + B0RCR, (RCR_STRIP_CRC | RCR_RXEN));
/* XXX add multicast/promiscuous flags */
outl(iobase + BANKSEL, BSR_BANK2);
outb(iobase + B2MSK, (MSK_RX_OVRN | MSK_RX));
sc->sc_intctl = MSK_RX_OVRN | MSK_RX;
sc->nrxovrn = 0;
/* Interface is now 'running', with no output active. */
ifp->if_flags |= IFF_RUNNING;
ifp->if_flags &= ~IFF_OACTIVE;
#ifdef ESDEBUG
if (ifp->if_flags & IFF_RUNNING)
es_dump_smcregs("esinit", smc);
#endif
/* Attempt to start output, if any. */
esstart(ifp);
(void)splx(s);
}
static int
esintr(arg)
void *arg;
{
struct es_softc *sc = arg;
u_int intsts, intact;
u_int iobase;
int n = 4;
iobase = sc->sc_base;
#ifdef ESDEBUG
while ((smc->b2.bsr & BSR_BANKMSK) != BSR_BANK2 &&
sc->sc_ethercom.ec_if.if_flags & IFF_RUNNING) {
printf("%s: intr BSR not 2: %04x\n", sc->sc_dev.dv_xname,
smc->b2.bsr);
smc->b2.bsr = BSR_BANK2;
}
#endif
intsts = inb(iobase + B2IST);
intact = inb(iobase + B2MSK) & intsts;
if ((intact) == 0) {
return (0); /* Pass interrupt on down the chain */
}
#ifdef ESDEBUG
if (esdebug)
printf ("%s: esintr ist %02x msk %02x",
sc->sc_dev.dv_xname, intsts, smc->b2.msk);
if (sc->sc_intbusy++) {
printf("%s: esintr re-entered\n", sc->sc_dev.dv_xname);
panic("esintr re-entered");
}
#endif
outb(iobase + B2MSK, 0);
#ifdef ESDEBUG
if (esdebug)
printf ("=>%02x%02x pnr %02x arr %02x fifo %04x\n",
smc->b2.ist, smc->b2.ist, smc->b2.pnr, smc->b2.arr,
smc->b2.fifo);
#endif
while (n-- && ((inl(iobase + B2FIFO) & FIFO_REMPTY) == 0)) {
esrint(sc);
}
if (intact & IST_RX_OVRN) {
printf ("%s: Overrun ist %02x", sc->sc_dev.dv_xname,
intsts);
outb(iobase + B2IST, ACK_RX_OVRN);
printf ("->%02x\n", inb(iobase + B2IST));
sc->sc_ethercom.ec_if.if_ierrors++;
if (sc->nrxovrn++ >= 10) {
outl(iobase + B2MMUCR, MMUCR_RESET);
sc->nrxovrn = 0;
}
}
if (intact & IST_ALLOC) {
u_char b2arr;
sc->sc_intctl &= ~MSK_ALLOC;
b2arr = inb(iobase + B2ARR);
if ((b2arr & ARR_FAILED) == 0) {
u_char save_pnr;
save_pnr = inb(iobase + B2PNR);
outb(iobase + B2PNR, b2arr);
outl(iobase + B2MMUCR, MMUCR_RLSPKT);
/*
* we don't want to wait forever.
*/
for (n = 100; n ; n--) {
if (!(inl(iobase + B2MMUCR) & MMUCR_BUSY))
break;
}
outb(iobase + B2PNR, save_pnr);
sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE;
}
#ifdef ESDEBUG
else if (esdebug || 1) {
printf ("%s: ist %02x arr %02x\n", sc->sc_dev.dv_xname,
intsts, smc->b2.arr);
printf (" IST_ALLOC with ARR_FAILED?\n");
}
#endif
}
if (intact & IST_TX_EMPTY) {
u_int ecr;
#ifdef ESDEBUG
if (esdebug)
printf ("%s: TX EMPTY %02x",
sc->sc_dev.dv_xname, intsts);
++estxint5; /* count # IST_TX_EMPTY ints */
#endif
outb(iobase + B2IST, ACK_TX_EMPTY);
sc->sc_intctl &= ~(MSK_TX_EMPTY | MSK_TX);
#ifdef ESDEBUG
if (esdebug)
printf ("->%02x intcl %x pnr %02x arr %02x\n",
smc->b2.ist, sc->sc_intctl, smc->b2.pnr,
smc->b2.arr);
#endif
if (inb(iobase + B2IST) & IST_TX) {
intact |= IST_TX;
#ifdef ESDEBUG
++estxint2; /* count # TX after TX_EMPTY */
#endif
} else {
outl(iobase + BANKSEL, BSR_BANK0);
ecr = inl(iobase + B0ECR); /* Get error counters */
if (ecr & ECR_CCMSK)
sc->sc_ethercom.ec_if.if_collisions += (ecr & 0x0f) +
((ecr >> 4) & 0x0f);
outl(iobase + BANKSEL, BSR_BANK2);
}
}
if (intact & IST_TX) {
u_char tx_pnr, save_pnr;
u_int save_ptr, ephsr, tcr;
#ifdef ESDEBUG
if (esdebug) {
printf ("%s: TX INT ist %02x",
sc->sc_dev.dv_xname, intsts);
printf ("->%02x\n", smc->b2.ist);
}
++estxint3; /* count # IST_TX */
#endif
n = 0;
zzzz:
#ifdef ESDEBUG
++estxint4; /* count # ~TEMPTY */
#endif
outl(iobase + BANKSEL, BSR_BANK0);
ephsr = inl(iobase + B0EPHSR); /* get EPHSR */
tcr = inl(iobase + B0TCR); /* and TCR */
outl(iobase + BANKSEL, BSR_BANK2);
save_ptr = inl(iobase + B2PTR);
save_pnr = inb(iobase + B2PNR);
tx_pnr = inl(iobase + B2FIFO) >> 8; /* pktno from completion fifo */
outb(iobase + B2PNR, tx_pnr); /* set TX packet number */
outl(iobase + B2PTR, PTR_READ); /* point to status word */
if ((ephsr & EPHSR_TX_SUC) == 0 && (tcr & TCR_TXENA) == 0) {
/*
* Transmitter was stopped for some error. Enqueue
* the packet again and restart the transmitter.
* May need some check to limit the number of retries.
*/
outl(iobase + B2MMUCR, MMUCR_ENQ_TX);
outl(iobase + BANKSEL, BSR_BANK0);
outl(iobase + B0TCR, inl(iobase + B0TCR) | TCR_TXENA);
outl(iobase + BANKSEL, BSR_BANK2);
sc->sc_ethercom.ec_if.if_oerrors++;
sc->sc_intctl |= MSK_TX_EMPTY | MSK_TX;
} else {
/*
* This shouldn't have happened: IST_TX indicates
* the TX completion FIFO is not empty, but the
* status for the packet on the completion FIFO
* shows that the transmit was sucessful. Since
* AutoRelease is being used, a sucessful transmit
* should not result in a packet on the completion
* FIFO. Also, that packet doesn't seem to want
* to be acknowledged. If this occurs, just reset
* the TX FIFOs.
*/
if (inb(iobase + B2IST) & IST_TX_EMPTY) {
outl(iobase + B2MMUCR, MMUCR_RESET_TX);
sc->sc_intctl &= ~(MSK_TX_EMPTY | MSK_TX);
}
#ifdef ESDEBUG
++estxints; /* count IST_TX with TX enabled */
#endif
}
outb(iobase + B2PNR, save_pnr);
outl(iobase + B2PTR, save_ptr);
outb(iobase + B2IST, ACK_TX);
if ((inl(iobase + B2FIFO) & FIFO_TEMPTY) == 0 && n++ < 10) {
if (tx_pnr != (inl(iobase + B2FIFO) >> 8))
goto zzzz;
}
}
/* output packets */
estint(&sc->sc_ethercom.ec_if);
#ifdef ESDEBUG
while ((smc->b2.bsr & BSR_BANKMSK) != BSR_BANK2) {
printf("%s: intr+++ BSR not 2: %04x\n", sc->sc_dev.dv_xname,
smc->b2.bsr);
smc->b2.bsr = BSR_BANK2;
}
#endif
outb(iobase + B2MSK, sc->sc_intctl & 0xff);
#ifdef ESDEBUG
if (--sc->sc_intbusy) {
printf("%s: esintr busy on exit\n", sc->sc_dev.dv_xname);
panic("esintr busy on exit");
}
#endif
return (1); /* Claim interrupt */
}
#define NWAIT(n) \
{\
int nwait = n; \
while (nwait--) ; \
}
static void
esrint(sc)
struct es_softc *sc;
{
u_int iobase = sc->sc_base;
u_short len;
short cnt;
u_short pktctlw, pktlen, *buf;
struct ifnet *ifp;
struct mbuf *top, **mp, *m;
u_char *b, *pktbuf;
#ifdef ESDEBUG
if (esdebug)
printf ("%s: esrint fifo %04x", sc->sc_dev.dv_xname,
smc->b2.fifo);
if (sc->sc_smcbusy++) {
printf("%s: esrint re-entered\n", sc->sc_dev.dv_xname);
panic("esrint re-entered");
}
while ((smc->b2.bsr & BSR_BANKMSK) != BSR_BANK2) {
printf("%s: rint BSR not 2: %04x\n", sc->sc_dev.dv_xname,
smc->b2.bsr);
smc->b2.bsr = BSR_BANK2;
}
#endif
outl(iobase + B2PTR, (PTR_RCV | PTR_AUTOINCR | PTR_READ | 0x0000));
NWAIT(3);
pktctlw = (u_short) inl(iobase + B2DATA);
pktlen = (u_short) inl(iobase + B2DATA);
len = pktlen;
pktlen -= 6;
if (pktctlw & RFSW_ODDFRM)
pktlen++;
if (len > 1530) {
printf("%s: Corrupted packet length-sts %04x bytcnt %04x len %04x bank %04x\n",
sc->sc_dev.dv_xname, pktctlw, pktlen, len, inl(iobase + BANKSEL));
/* XXX ignore packet, or just truncate? */
#if defined(ESDEBUG) && defined(DDB)
if ((smc->b2.bsr & BSR_BANKMSK) != BSR_BANK2)
Debugger();
#endif
outl(iobase + BANKSEL, BSR_BANK2);
outl(iobase + B2MMUCR, MMUCR_REMRLS_RX);
while (inl(iobase + B2MMUCR) & MMUCR_BUSY)
;
++sc->sc_ethercom.ec_if.if_ierrors;
#ifdef ESDEBUG
if (--sc->sc_smcbusy) {
printf("%s: esrintr busy on bad packet exit\n",
sc->sc_dev.dv_xname);
panic("esrintr busy on exit");
}
#endif
return;
}
pktbuf = sc->pktbuf;
buf = (u_short *)pktbuf;
cnt = (len - 4) / 2;
while (cnt--) {
*buf = (u_short) (inl(iobase + B2DATA) & 0x0000ffff);
buf++;
}
outl(iobase + B2MMUCR, MMUCR_REMRLS_RX);
/*
* We will check MMUCR_BUSY later.
*/
#ifdef ESDEBUG
if (pktctlw & (RFSW_ALGNERR | RFSW_BADCRC | RFSW_TOOLNG | RFSW_TOOSHORT)) {
printf ("%s: Packet error %04x\n", sc->sc_dev.dv_xname, pktctlw);
/* count input error? */
}
if (esdebug) {
printf (" pktctlw %04x pktlen %04x fifo %04x\n", pktctlw, pktlen,
smc->b2.fifo);
for (i = 0; i < pktlen; ++i)
printf ("%02x%s", pktbuf[i], ((i & 31) == 31) ? "\n" :
"");
if (i & 31)
printf ("\n");
}
#endif
ifp = &sc->sc_ethercom.ec_if;
ifp->if_ipackets++;
MGETHDR(m, M_DONTWAIT, MT_DATA);
if (m == NULL)
return;
m->m_pkthdr.rcvif = ifp;
m->m_pkthdr.len = pktlen;
len = MHLEN;
top = NULL;
mp = &top;
b = pktbuf;
while (pktlen > 0) {
if (top) {
MGET(m, M_DONTWAIT, MT_DATA);
if (m == 0) {
m_freem(top);
return;
}
len = MLEN;
}
if (pktlen >= MINCLSIZE) {
MCLGET(m, M_DONTWAIT);
if (m->m_flags & M_EXT)
len = MCLBYTES;
}
m->m_len = len = min(pktlen, len);
bcopy((caddr_t)b, mtod(m, caddr_t), len);
b += len;
pktlen -= len;
*mp = m;
mp = &m->m_next;
}
#if NBPFILTER > 0
/*
* Check if there's a BPF listener on this interface. If so, hand off
* the raw packet to bpf.
*/
if (sc->sc_ethercom.ec_if.if_bpf)
bpf_mtap(sc->sc_ethercom.ec_if.if_bpf, top);
#endif
(*ifp->if_input)(ifp, top);
#ifdef ESDEBUG
if (--sc->sc_smcbusy) {
printf("%s: esintr busy on exit\n", sc->sc_dev.dv_xname);
panic("esintr busy on exit");
}
#endif
while (inl(iobase + B2MMUCR) & MMUCR_BUSY)
;
}
static void
estint(ifp)
struct ifnet *ifp;
{
int s;
s = splnet();
esstart(ifp);
(void)splx(s);
}
static void
esstart(ifp)
struct ifnet *ifp;
{
struct es_softc *sc = ifp->if_softc;
u_int iobase = sc->sc_base;
struct mbuf *m0, *m;
u_short *pktbuf;
u_short pktctlw, pktlen, len;
u_short *buf;
short cnt;
int i;
u_char active_pnr;
if ((sc->sc_ethercom.ec_if.if_flags & (IFF_RUNNING | IFF_OACTIVE)) !=
IFF_RUNNING) {
IF_DEQUEUE(&sc->sc_ethercom.ec_if.if_snd, m);
if (m)
m_freem(m);
return;
}
#ifdef ESDEBUG
if (sc->sc_smcbusy++) {
printf("%s: esstart re-entered\n", sc->sc_dev.dv_xname);
panic("esstart re-entred");
}
while ((smc->b2.bsr & BSR_BANKMSK) != BSR_BANK2) {
printf("%s: esstart BSR not 2: %04x\n", sc->sc_dev.dv_xname,
smc->b2.bsr);
smc->b2.bsr = BSR_BANK2;
}
#endif
IF_DEQUEUE(&sc->sc_ethercom.ec_if.if_snd, m);
if (!m)
return;
pktbuf = (u_short *) sc->pktbuf;
for (m0 = m, pktlen = 0; m; m = m->m_next) {
bcopy(mtod(m, caddr_t), (char *)pktbuf + pktlen, m->m_len);
pktlen += m->m_len;
}
len = pktlen;
m_freem(m0);
if (len & 1) { /* Figure out where to put control byte */
pktbuf[len/2] = (pktbuf[len/2] & 0x00ff) | CTLB_ODD;
pktlen++;
} else {
pktbuf[len/2] = 0;
pktlen += 2;
}
if (pktlen > (ETHERMTU + 18)) {
printf("es: packet too long = %d bytes\n", pktlen);
}
#if NBPFILTER > 0
if (sc->sc_ethercom.ec_if.if_bpf)
bpf_tap(sc->sc_ethercom.ec_if.if_bpf, (char *)pktbuf, len);
#endif
pktctlw = 0;
pktlen += 4;
outl(iobase + B2MMUCR, (MMUCR_ALLOC | (pktlen >> 8)));
for (i = 0; i <= 100; ++i) {
if ((inb(iobase + B2ARR) & ARR_FAILED) == 0)
break;
}
if (inb(iobase + B2ARR) & ARR_FAILED) {
sc->sc_ethercom.ec_if.if_flags |= IFF_OACTIVE;
sc->sc_intctl |= MSK_ALLOC;
goto esstart_out;
}
active_pnr = inb(iobase + B2ARR);
outb(iobase + B2PNR, active_pnr);
outl(iobase + B2PTR, PTR_AUTOINCR);
NWAIT(3);
outl(iobase + B2DATA, pktctlw);
outl(iobase + B2DATA, pktlen);
buf = pktbuf;
cnt = (pktlen - 4) / 2;
while (cnt--) {
outl(iobase + B2DATA, (u_short) *buf);
buf++;
}
outl(iobase + B2MMUCR, MMUCR_ENQ_TX);
if (inb(iobase + B2PNR) != active_pnr)
printf("%s: esstart - PNR changed %x->%x\n",
sc->sc_dev.dv_xname, active_pnr, inb(iobase + B2PNR));
sc->sc_ethercom.ec_if.if_opackets++; /* move to interrupt? */
sc->sc_intctl |= MSK_TX_EMPTY | MSK_TX;
esstart_out:
outb(iobase + B2MSK, sc->sc_intctl & 0xff);
#ifdef ESDEBUG
while ((smc->b2.bsr & BSR_BANKMSK) != BSR_BANK2) {
printf("%s: esstart++++ BSR not 2: %04x\n", sc->sc_dev.dv_xname,
smc->b2.bsr);
smc->b2.bsr = BSR_BANK2;
}
if (--sc->sc_smcbusy) {
printf("%s: esstart busy on exit\n", sc->sc_dev.dv_xname);
panic("esstart busy on exit");
}
#endif
}
static int
esioctl(ifp, command, data)
struct ifnet *ifp;
u_long command;
caddr_t data;
{
struct es_softc *sc = ifp->if_softc;
struct ifaddr *ifa = (struct ifaddr *)data;
struct ifreq *ifr = (struct ifreq *)data;
int s, error = 0;
s = splnet();
switch (command) {
case SIOCSIFADDR:
ifp->if_flags |= IFF_UP;
switch (ifa->ifa_addr->sa_family) {
#ifdef INET
case AF_INET:
esinit(sc);
arp_ifinit(ifp, ifa);
break;
#endif
#ifdef NS
case AF_NS:
{
struct ns_addr *ina = &IA_SNS(ifa)->sns_addr;
if (ns_nullhost(*ina))
ina->x_host =
*(union ns_host *)LLADDR(ifp->if_sadl);
else
bcopy(ina->x_host.c_host,
LLADDR(ifp->if_sadl), ETHER_ADDR_LEN));
/* Set new address. */
esinit(sc);
break;
#endif
default:
esinit(sc);
break;
}
break;
case SIOCSIFFLAGS:
/*
* If interface is marked down and it is running, then stop it
*/
if ((ifp->if_flags & IFF_UP) == 0 &&
(ifp->if_flags & IFF_RUNNING) != 0) {
/*
* If interface is marked down and it is running, then
* stop it.
*/
esstop(sc);
ifp->if_flags &= ~IFF_RUNNING;
} else if ((ifp->if_flags & IFF_UP) != 0 &&
(ifp->if_flags & IFF_RUNNING) == 0) {
/*
* If interface is marked up and it is stopped, then
* start it.
*/
esinit(sc);
} else {
/*
* Reset the interface to pick up changes in any other
* flags that affect hardware registers.
*/
esstop(sc);
esinit(sc);
}
#ifdef ESDEBUG
if (ifp->if_flags & IFF_DEBUG)
esdebug = sc->sc_debug = 1;
else
esdebug = sc->sc_debug = 0;
#endif
break;
case SIOCADDMULTI:
case SIOCDELMULTI:
error = (command == SIOCADDMULTI) ?
ether_addmulti(ifr, &sc->sc_ethercom) :
ether_delmulti(ifr, &sc->sc_ethercom);
if (error == ENETRESET) {
/*
* Multicast list has changed; set the hardware filter
* accordingly.
*/
/* XXX */
error = 0;
}
break;
default:
error = EINVAL;
}
(void)splx(s);
return (error);
}
static void
esreset(sc)
struct es_softc *sc;
{
int s;
s = splnet();
esstop(sc);
esinit(sc);
(void)splx(s);
}
static void
eswatchdog(ifp)
struct ifnet *ifp;
{
struct es_softc *sc = ifp->if_softc;
log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname);
++ifp->if_oerrors;
esreset(sc);
}

265
sys/arch/arm32/rc7500/if_esreg.h
View File

@ -1,265 +0,0 @@
/* $NetBSD: if_esreg.h,v 1.2 1997/10/14 21:45:24 mark Exp $ */
/*
* Copyright (c) 1996, Danny C Tsen.
* Copyright (c) 1996, VLSI Technology Inc. All Rights Reserved.
* Copyright (c) 1995 Michael L. Hitch
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Michael L. Hitch.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _IF_ESREG_H_
#define _IF_ESREG_H_
/*
* This file is modified from Amiga's es driver for RC7500 board.
* Each register of the SMC 91C92 is 16 bits wide and 4 bytes aligned.
*/
/*
* SMC 91C9x register definitions
*/
union smcregs {
struct {
volatile u_int tcr; /* Transmit Control Register */
volatile u_int ephsr; /* EPH Status Register */
volatile u_int rcr; /* Receive Control Register */
volatile u_int ecr; /* Counter Register */
volatile u_int mir; /* Memory Information Register */
volatile u_int mcr; /* Memory Configuration Register */
volatile u_int resv;
volatile u_int bsr; /* Bank Select Register */
} b0;
struct {
volatile u_int cr; /* Configuration Register */
volatile u_int bar; /* Base Address Register */
volatile u_int iar[3]; /* Individual Address Registers */
volatile u_int gpr; /* General Purpose Register */
volatile u_int ctr; /* Control Register */
volatile u_int bsr; /* Bank Select Register */
} b1;
struct {
volatile u_int mmucr; /* MMU Command Register */
volatile u_char pnr; /* Lo: Packet Number Register */
volatile u_char arr; /* Hi: Allocation Result Register */
volatile u_short pad0; /* padded to 4 bytes aligned */
volatile u_int fifo; /* FIFO Ports Register */
volatile u_int ptr; /* Pointer Register */
volatile u_int data; /* Data Register */
volatile u_int datax; /* Data Register (2nd mapping) */
volatile u_char ist; /* Lo: Interrupt Status Register */
volatile u_char msk; /* Hi: Interrupt Mask Register */
volatile u_short pad1; /* padded to 4 bytes aligned */
volatile u_int bsr; /* Bank Select Register */
} b2;
struct {
volatile u_int mt[4]; /* Multicast Table */
volatile u_int resv[3];
volatile u_int bsr; /* Bank Select Register */
} b3;
/*
* Bank 2 registers defined as u_int fields
*/
struct {
volatile u_int mmucr; /* MMU Command Register */
volatile u_int pnrarr;/* Packet Number/Allocation Result */
volatile u_int fifo; /* FIFO Ports Register */
volatile u_int ptr; /* Pointer Register */
volatile u_int data; /* Data Register */
volatile u_int datax; /* Data Register (2nd mapping) */
volatile u_int istmsk;/* Interrupt Status/Mask Register */
volatile u_int bsr; /* Bank Select Register */
} w2;
};
/* Transmit Control Register */
#define TCR_PAD_EN 0x0080 /* Pad short frames */
#define TCR_TXENA 0x0001 /* Transmit enabled */
#define TCR_MON_CSN 0x0400 /* Monitor carrier */
#define TCR_FDUPLX 0x0800 /* Full duplex */
/* EPH Status Register */
#define EPHSR_16COL 0x0010 /* 16 collisions reached */
#define EPHSR_MULCOL 0x0004 /* Multiple collsions */
#define EPHSR_TX_SUC 0x0001 /* Last transmit sucessful */
#define EPHSR_LOST_CAR 0x0400 /* Lost carrier */
/* Receive Control Register */
#define RCR_ALLMUL 0x0004 /* Accept all Multicast frames */
#define RCR_PRMS 0x0002 /* Promiscuous mode */
#define RCR_EPH_RST 0x8000 /* Software activated Reset */
#define RCR_FILT_CAR 0x4000 /* Filter carrier */
#define RCR_STRIP_CRC 0x0200 /* Strip CRC */
#define RCR_RXEN 0x0100 /* Receiver enabled */
/* Counter Register */
#define ECR_CCMSK 0x00ff
#define ECR_MCC 0x00f0 /* Multiple collision count */
#define ECR_SCC 0x000f /* Single collision count */
#define ECR_EDTX 0xf000 /* Excess deferred TX count */
#define ECR_DTX 0x0f00 /* Deferred TX count */
/* Configuration Register */
#define CR_ALLONES 0x0030 /* 32Kx16 RAM */
#define CR_RAM32K 0x0020 /* 32Kx16 RAM */
#define CR_16BIT 0x0080 /* 16 bit bus */
#define CR_NO_WAIT_ST 0x1000 /* No wait state */
#define CR_SET_SQLCH 0x0200 /* Squelch level 240mv */
/* Control Register */
#define CTR_AUTO_RLSE 0x0800 /* Auto Release */
/* MMU Command Register */
#define MMUCR_NOOP 0x0000 /* No operation */
#define MMUCR_ALLOC 0x0020 /* Allocate memory for TX */
#define MMUCR_RESET 0x0040 /* Reset to intitial state */
#define MMUCR_REM_RX 0x0060 /* Remove frame from top of RX FIFO */
#define MMUCR_REMRLS_RX 0x0080 /* Remove & release from top of RX FIFO */
#define MMUCR_RLSPKT 0x00a0 /* Release specific packet */
#define MMUCR_ENQ_TX 0x00c0 /* Enqueue packet into TX FIFO */
#define MMUCR_RESET_TX 0x00e0 /* Reset TX FIFOs */
#define MMUCR_BUSY 0x0001 /* MMU busy */
/* Allocation Result Register */
#define ARR_FAILED 0x80 /* Allocation failed */
#define ARR_APN 0x1f /* Allocated packet number */
/* FIFO Ports Register */
#define FIFO_TEMPTY 0x0080 /* TX queue empty */
#define FIFO_TXPNR 0x001f /* TX done packet number */
#define FIFO_REMPTY 0x8000 /* RX FIFO empty */
#define FIFO_RXPNR 0x1f00 /* RX FIFO packet number */
/* Pointer Register */
#define PTR_RCV 0x8000 /* Use Receive area */
#define PTR_AUTOINCR 0x4000 /* Auto increment pointer on access */
#define PTR_READ 0x2000 /* Read access */
/* Interrupt Status Register */
#define IST_EPHINT 0x20 /* EPH Interrupt */
#define IST_RX_OVRN 0x10 /* RX Overrun */
#define IST_ALLOC 0x08 /* MMU Allocation completed */
#define IST_TX_EMPTY 0x04 /* TX FIFO empty */
#define IST_TX 0x02 /* TX complete */
#define IST_RX 0x01 /* RX complete */
/* Interrupt Acknowlege Register */
#define ACK_RX_OVRN IST_RX_OVRN
#define ACK_TX_EMPTY IST_TX_EMPTY
#define ACK_TX IST_TX
/* Interrupt Mask Register */
#define MSK_EPHINT 0x20 /* EPH Interrupt */
#define MSK_RX_OVRN 0x10 /* RX Overrun */
#define MSK_ALLOC 0x08 /* MMU Allocation completed */
#define MSK_TX_EMPTY 0x04 /* TX FIFO empty */
#define MSK_TX 0x02 /* TX complete */
#define MSK_RX 0x01 /* RX complete */
/* Bank Select Register */
#define BSR_BANK0 0x0000 /* Select bank 0 */
#define BSR_BANK1 0x0001 /* Select bank 1 */
#define BSR_BANK2 0x0002 /* Select bank 2 */
#define BSR_BANK3 0x0003 /* Select bank 3 */
#define BSR_BANKMSK 0x0003
/* Packet Receive Frame Status Word */
#define RFSW_ALGNERR 0x8000 /* Alignment Error */
#define RFSW_BRDCST 0x4000 /* Broadcast frame */
#define RFSW_BADCRC 0x2000 /* Bad CRC */
#define RFSW_ODDFRM 0x1000 /* Odd number of bytes in frame */
#define RFSW_TOOLNG 0x0800 /* Frame was too long */
#define RFSW_TOOSHORT 0x0400 /* Frame was too short */
#define RFSW_HASH 0x007e /* Multicast hash value */
#define RFSW_MULTCAST 0x0001 /* Multicast frame */
/* Control byte */
#define CTLB_ODD 0x2000 /* Odd number of bytes in frame */
#define CTLB_CRC 0x1000 /* Append CRC to transmitted frame */
/*
* The SMC 92C9x Register Definitions
*/
#define BANKSEL 0x1c /* The Bank Select Register (Read/Write) */
#define BANK0 0x00
#define BANK1 0x01
#define BANK2 0x02
#define BANK3 0x03
/*
* Register Bank #0 Definitions
*/
#define B0TCR 0x00 /* Transmit Control Register (Read/Write) */
#define B0EPHSR 0x04 /* EPH Status Register (Read Only) */
#define B0RCR 0x08 /* Receive Control Register (Read/Write) */
#define B0ECR 0x0c /* Counter Register (Read Only) */
#define B0MIR 0x10 /* Memory Information Register (Read Only) */
#define B0MCR 0x14 /* Memory Configuration Register (Read/Write) */
/*
* Register Bank #1 Definitions
*/
#define B1CR 0x00 /* Configuration Register (Read/Write) */
#define B1BAR 0x04 /* Base Address Register (Read/Write) */
#define B1IAR1 0x08 /* Hi Individual Address Register #1 (R/W) */
#define B1IAR2 0x09 /* Lo Individual Address Register #2 (R/W) */
#define B1IAR3 0x0c /* Hi Individual Address Register #3 (R/W) */
#define B1IAR4 0x0d /* Lo Individual Address Register #4 (R/W) */
#define B1IAR5 0x10 /* Hi Individual Address Register #5 (R/W) */
#define B1IAR6 0x11 /* Lo Individual Address Register #6 (R/W) */
#define B1GPR 0x14 /* General Purpose Register (Read/Write) */
#define B1CTR 0x18 /* Control Register (Read/Write) */
/*
* Register Bank #2 Definitions
* NOTE: The Interrupt Mask Register occupies the upper byte of the
* halfword read from or written to the IST or ACK Registers
*/
#define B2MMUCR 0x00 /* MMU Command Register (Read/Write) */
#define B2PNR 0x04 /* Lo Packet Number Register (Read/Write) */
#define B2ARR 0x05 /* Hi Allocation Result Register (Read Only) */
#define B2FIFO 0x08 /* FIFO Ports Register (Read Only) */
#define B2PTR 0x0c /* Pointer Register (Read/Write) */
#define B2DATA 0x10 /* Data Register (Read/Write) */
#define B2IST 0x18 /* Interrupt Status Register (Read Only) */
#define B2ACK 0x18 /* Interrupt Acknowledge Register (Write) */
#define B2MSK 0x19 /* Interrupt mask register, R/W */
/*
* Register Bank #3 Definitions
*/
#define B3MT0 0x00 /* Lo MultiCast Table #0 Register (R/W) */
#define B3MT1 0x01 /* Hi MultiCast Table #1 Register (R/W) */
#define B3MT2 0x04 /* Lo MultiCast Table #2 Register (R/W) */
#define B3MT3 0x05 /* Hi MultiCast Table #3 Register (R/W) */
#define B3MT4 0x08 /* Lo MultiCast Table #4 Register (R/W) */
#define B3MT5 0x09 /* Hi MultiCast Table #5 Register (R/W) */
#define B3MT6 0x0c /* Lo MultiCast Table #6 Register (R/W) */
#define B3MT7 0x0d /* Hi MultiCast Table #7 Register (R/W) */
#endif /* _IF_ESREG_H_ */

509
sys/arch/arm32/rc7500/rc7500_kbd_map.c
View File

@ -1,509 +0,0 @@
/* $NetBSD: rc7500_kbd_map.c,v 1.1 1997/10/14 10:52:39 mark Exp $ */
/*
* Copyright (c) 1994-1997 Mark Brinicombe.
* Copyright (c) 1994 Brini.
* All rights reserved.
*
* This code is derived from software written for Brini by Mark Brinicombe
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Mark Brinicombe.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RiscBSD kernel project
*
* kbd.c
*
* Keyboard driver functions
*
* Created : 09/10/94
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/proc.h>
#include <sys/device.h>
#include <sys/tty.h>
#include <sys/select.h>
#include <machine/bus.h>
#include <arm32/dev/kbdvar.h>
/* Define mappings for each possible code */
key_struct keys[256] = {
/* 0x00 - 0x0f */
{ 0x00, 0x00, 0x00, 0x00, 0x80 },
{ 0x89, 0x99, 0x00, 0x489, 0x00 },
{ 0x8a, 0x9a, 0x00, 0x00, 0x00 },
{ 0x85, 0x95, 0x00, 0x485, 0x00 },
{ 0x83, 0x93, 0x00, 0x483, 0x00 },
{ 0x81, 0x91, 0x00, 0x481, 0x00 },
{ 0x82, 0x92, 0x00, 0x482, 0x00 },
{ 0x8c, 0x9c, 0x00, 0x48c, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x88, 0x98, 0x00, 0x488, 0x00 },
{ 0x86, 0x96, 0x00, 0x486, 0x00 },
{ 0x84, 0x94, 0x00, 0x484, 0x00 },
{ 0x09, 0x09, 0x09, 0x09, 0x00 },
#ifdef RC7500
{ 0x60, 0x7e, 0x00, 0x00, 0x00 },
#else
{ 0x60, 0x00, 0x00, 0x00, 0x00 },
#endif
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
/* 0x10 - 0x1f */
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x84 },
{ 0x00, 0x00, 0x00, 0x00, 0x82 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x81 },
{ 0x71, 0x51, 0x11, 0x00, 0x40 },
{ 0x31, 0x21, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x7a, 0x5a, 0x1a, 0x00, 0x40 },
{ 0x73, 0x53, 0x13, 0x00, 0x40 },
{ 0x61, 0x41, 0x01, 0x00, 0x40 },
{ 0x77, 0x57, 0x17, 0x00, 0x40 },
{ 0x32, 0x22, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
/* 0x20 - 0x2f */
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x63, 0x43, 0x03, 0x00, 0x40 },
{ 0x78, 0x58, 0x18, 0x00, 0x40 },
{ 0x64, 0x44, 0x04, 0x00, 0x40 },
{ 0x65, 0x45, 0x05, 0x00, 0x40 },
{ 0x34, 0x24, 0x00, 0x00, 0x00 },
{ 0x33, 0x23, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x20, 0x20, 0x20, 0x20, 0x00 },
{ 0x76, 0x56, 0x16, 0x00, 0x40 },
{ 0x66, 0x46, 0x06, 0x00, 0x40 },
{ 0x74, 0x54, 0x14, 0x00, 0x40 },
{ 0x72, 0x52, 0x12, 0x00, 0x40 },
{ 0x35, 0x25, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
/* 0x30 - 0x3f */
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x6e, 0x4e, 0x0e, 0x00, 0x40 },
{ 0x62, 0x42, 0x02, 0x00, 0x40 },
{ 0x68, 0x48, 0x08, 0x00, 0x40 },
{ 0x67, 0x47, 0x07, 0x00, 0x40 },
{ 0x79, 0x59, 0x19, 0x00, 0x40 },
{ 0x36, 0x5e, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x6d, 0x4d, 0x0d, 0x00, 0x40 },
{ 0x6a, 0x4a, 0x0a, 0x00, 0x40 },
{ 0x75, 0x55, 0x15, 0x00, 0x40 },
{ 0x37, 0x26, 0x00, 0x00, 0x00 },
{ 0x38, 0x2a, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
/* 0x40 - 0x4f */
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x2c, 0x3c, 0x00, 0x00, 0x00 },
{ 0x6b, 0x4b, 0x0b, 0x00, 0x40 },
{ 0x69, 0x49, 0x09, 0x00, 0x40 },
{ 0x6f, 0x4f, 0x0f, 0x00, 0x40 },
{ 0x30, 0x29, 0x00, 0x00, 0x00 },
{ 0x39, 0x28, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x2e, 0x3e, 0x00, 0x00, 0x00 },
{ 0x2f, 0x3f, 0x00, 0x00, 0x00 },
{ 0x6c, 0x4c, 0x0c, 0x00, 0x40 },
{ 0x3b, 0x3a, 0x00, 0x00, 0x00 },
{ 0x70, 0x50, 0x10, 0x00, 0x40 },
{ 0x2d, 0x5f, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
/* 0x50 - 0x5f */
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
#ifdef RC7500
{ 0x27, 0x22, 0x00, 0x00, 0x00 },
#else
{ 0x27, 0x40, 0x00, 0x00, 0x00 },
#endif
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x5b, 0x7b, 0x00, 0x00, 0x00 },
{ 0x3d, 0x2b, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0xa0 },
{ 0x00, 0x00, 0x00, 0x00, 0x82 },
{ 0x0d, 0x0d, 0x0d, 0x00, 0x00 },
{ 0x5d, 0x7d, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
#ifdef RC7500
{ 0x5c, 0x7c, 0x00, 0x00, 0x00 },
#else
{ 0x23, 0x7e, 0x00, 0x00, 0x00 },
#endif
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
/* 0x60 - 0x6f */
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x5c, 0x7c, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x08, 0x7f, 0x08, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x31, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x34, 0x00, 0x00, 0x00, 0x00 },
{ 0x37, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
/* 0x70 - 0x7f */
{ 0x30, 0x00, 0x00, 0x00, 0x00 },
{ 0x2e, 0x00, 0x00, 0x00, 0x00 },
{ 0x32, 0x00, 0x00, 0x00, 0x00 },
{ 0x35, 0x00, 0x00, 0x00, 0x00 },
{ 0x36, 0x00, 0x00, 0x00, 0x00 },
{ 0x38, 0x00, 0x00, 0x00, 0x00 },
{ 0x1b, 0x1b, 0x21b, 0x1b, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x90 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x2b, 0x00, 0x00, 0x22b, 0x00 },
{ 0x33, 0x00, 0x00, 0x00, 0x00 },
{ 0x2d, 0x00, 0x00, 0x22d, 0x00 },
{ 0x2a, 0x00, 0x00, 0x00, 0x00 },
{ 0x39, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x88 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
/* 0x80 - 0x8f */
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x87, 0x97, 0x00, 0x487, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
/* 0x90 - 0x9f */
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
/* 0xa0 - 0xaf */
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
/* 0xb0 - 0xbf */
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
/* 0xc0 - 0xcf */
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
/* 0xd0 - 0xdf */
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
/* 0xe0 - 0xef */
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
/* 0xf0 - 0xff */
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 }
};
/* Define mappings for each possible code */
key_struct E0keys[128] = {
/* 0x00 - 0x0f */
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
/* 0x10 - 0x1f */
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x84 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x81 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
/* 0x20 - 0x2f */
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
/* 0x30 - 0x3f */
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
/* 0x40 - 0x4f */
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x2f, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
/* 0x50 - 0x5f */
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x0d, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
/* 0x60 - 0x6f */
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x10b, 0x00, 0x00, 0x20b, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x102, 0x00, 0x00, 0x202, 0x00 },
{ 0x10a, 0x00, 0x00, 0x20a, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
/* 0x70 - 0x7f */
{ 0x108, 0x00, 0x00, 0x208, 0x00 },
{ 0x109, 0x00, 0x00, 0x209, 0x00 },
{ 0x101, 0x105, 0x00, 0x201, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x103, 0x00, 0x00, 0x203, 0x00 },
{ 0x100, 0x104, 0x00, 0x200, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x104, 0x100, 0x00, 0x204, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x105, 0x101, 0x00, 0x205, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
};
/* End of kbd_map.c */

977
sys/arch/arm32/rc7500/rc7500_machdep.c
View File

@ -1,977 +0,0 @@
/* $NetBSD: rc7500_machdep.c,v 1.34 2001/06/19 13:45:54 wiz Exp $ */
/*
* Copyright (c) 1994-1998 Mark Brinicombe.
* Copyright (c) 1994 Brini.
* All rights reserved.
*
* This code is derived from software written for Brini by Mark Brinicombe
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Brini.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RiscBSD kernel project
*
* machdep.c
*
* Machine dependant functions for kernel setup
*
* This file needs a lot of work.
*
* Created : 17/09/94
*/
#include "opt_ddb.h"
#include "opt_md.h"
#include "opt_pmap_debug.h"
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/reboot.h>
#include <sys/proc.h>
#include <sys/msgbuf.h>
#include <sys/exec.h>
#include <dev/cons.h>
#include <machine/db_machdep.h>
#include <ddb/db_sym.h>
#include <ddb/db_extern.h>
#include <machine/signal.h>
#include <machine/frame.h>
#include <machine/bootconfig.h>
#include <machine/cpu.h>
#include <machine/io.h>
#include <machine/irqhandler.h>
#include <machine/katelib.h>
#include <machine/pte.h>
#include <machine/vidc.h>
#include <machine/vconsole.h>
#include <machine/undefined.h>
#include <machine/rtc.h>
#include <arm32/iomd/iomdreg.h>
#include <arm32/iomd/iomdvar.h>
#include "opt_ipkdb.h"
#ifdef RC7500
#include <arm32/rc7500/rc7500_prom.h>
#endif
extern int *vidc_base;
extern int *iomd_base;
/*
* Address to call from cpu_reset() to reset the machine.
* This is machine architecture dependant as it varies depending
* on where the ROM appears when you turn the MMU off.
*/
u_int cpu_reset_address = 0;
/* Define various stack sizes in pages */
#define FIQ_STACK_SIZE 1
#define IRQ_STACK_SIZE 1
#define ABT_STACK_SIZE 1
#ifdef IPKDB
#define UND_STACK_SIZE 2
#else
#define UND_STACK_SIZE 1
#endif
BootConfig bootconfig; /* Boot config storage */
videomemory_t videomemory; /* Video memory descriptor */
vm_offset_t physical_start;
vm_offset_t physical_freestart;
vm_offset_t physical_freeend;
vm_offset_t physical_end;
u_int free_pages;
int physmem = 0;
#ifndef PMAP_STATIC_L1S
int max_processes = 64;
#endif /* !PMAP_STATIC_L1S */
u_int memory_disc_size; /* Memory disc size */
u_int videodram_size; /* Amount of DRAM to reserve for video */
vm_offset_t videodram_start;
vm_offset_t physical_pt_start;
vm_offset_t virtual_pt_end;
/* Physical and virtual addresses for some global pages */
pv_addr_t systempage;
pv_addr_t irqstack;
pv_addr_t undstack;
pv_addr_t abtstack;
pv_addr_t kernelstack;
#ifdef RC7500
pv_addr_t fiqstack;
#endif
char *boot_args = NULL;
char *boot_file = NULL;
vm_offset_t msgbufphys;
extern u_int data_abort_handler_address;
extern u_int prefetch_abort_handler_address;
extern u_int undefined_handler_address;
#ifdef PMAP_DEBUG
extern int pmap_debug_level;
#endif /* PMAP_DEBUG */
#define KERNEL_PT_VMEM 0 /* Page table for mapping video memory */
#define KERNEL_PT_SYS 1 /* Page table for mapping proc0 zero page */
#define KERNEL_PT_KERNEL 2 /* Page table for mapping kernel */
#define KERNEL_PT_VMDATA 3 /* Page tables for mapping kernel VM */
#define KERNEL_PT_VMDATA_NUM (KERNEL_VM_SIZE >> (PDSHIFT + 2))
#define NUM_KERNEL_PTS (KERNEL_PT_VMDATA + KERNEL_PT_VMDATA_NUM)
pt_entry_t kernel_pt_table[NUM_KERNEL_PTS];
struct user *proc0paddr;
/* Prototypes */
void physconputchar __P((char));
void physcon_display_base __P((u_int addr));
extern void consinit __P((void));
void map_section __P((vm_offset_t pt, vm_offset_t va, vm_offset_t pa,
int cacheable));
void map_pagetable __P((vm_offset_t pt, vm_offset_t va, vm_offset_t pa));
void map_entry __P((vm_offset_t pt, vm_offset_t va, vm_offset_t pa));
void map_entry_nc __P((vm_offset_t pt, vm_offset_t va, vm_offset_t pa));
void map_entry_ro __P((vm_offset_t pt, vm_offset_t va, vm_offset_t pa));
vm_size_t map_chunk __P((vm_offset_t pd, vm_offset_t pt, vm_offset_t va,
vm_offset_t pa, vm_size_t size, u_int acc,
u_int flg));
void data_abort_handler __P((trapframe_t *frame));
void prefetch_abort_handler __P((trapframe_t *frame));
void undefinedinstruction_bounce __P((trapframe_t *frame));
void zero_page_readonly __P((void));
void zero_page_readwrite __P((void));
static void process_kernel_args __P((void));
extern void dump_spl_masks __P((void));
extern void db_machine_init __P((void));
extern void console_flush __P((void));
extern void vidcrender_reinit __P((void));
extern int vidcrender_blank __P((struct vconsole *vc, int type));
extern void parse_mi_bootargs __P((char *args));
void parse_rc7500_bootargs __P((char *args));
extern void dumpsys __P((void));
/*
* void boot(int howto, char *bootstr)
*
* Reboots the system
*
* Deal with any syncing, unmounting, dumping and shutdown hooks,
* then reset the CPU.
*/
/* NOTE: These variables will be removed, well some of them */
extern u_int spl_mask;
extern u_int current_mask;
extern u_int arm700bugcount;
void
cpu_reboot(howto, bootstr)
int howto;
char *bootstr;
{
#ifdef DIAGNOSTIC
printf("boot: howto=%08x curproc=%p\n", howto, curproc);
printf("ipl_bio=%08x ipl_net=%08x ipl_tty=%08x ipl_imp=%08x\n",
irqmasks[IPL_BIO], irqmasks[IPL_NET], irqmasks[IPL_TTY],
irqmasks[IPL_IMP]);
printf("ipl_audio=%08x ipl_clock=%08x ipl_none=%08x\n",
irqmasks[IPL_AUDIO], irqmasks[IPL_CLOCK], irqmasks[IPL_NONE]);
dump_spl_masks();
/* Did we encounter the ARM700 bug we discovered ? */
if (arm700bugcount > 0)
printf("ARM700 PREFETCH/SWI bug count = %d\n", arm700bugcount);
#endif
/*
* If we are still cold then hit the air brakes
* and crash to earth fast
*/
if (cold) {
doshutdownhooks();
printf("Halted while still in the ICE age.\n");
printf("The operating system has halted.\n");
printf("Please press any key to reboot.\n\n");
cngetc();
printf("rebooting...\n");
cpu_reset();
/*NOTREACHED*/
}
/* Disable console buffering */
cnpollc(1);
/*
* If RB_NOSYNC was not specified sync the discs.
* Note: Unless cold is set to 1 here, syslogd will die during the unmount.
* It looks like syslogd is getting woken up only to find that it cannot
* page part of the binary in as the filesystem has been unmounted.
*/
if (!(howto & RB_NOSYNC))
bootsync();
/* Say NO to interrupts */
splhigh();
/* Do a dump if requested. */
if ((howto & (RB_DUMP | RB_HALT)) == RB_DUMP)
dumpsys();
/*
* Auto reboot overload protection
*
* This code stops the kernel entering an endless loop of reboot
* - panic cycles. This will have the effect of stopping further
* reboots after it has rebooted 8 times after panics. A clean
* halt or reboot will reset the counter.
*/
/*
* Have we done 8 reboots in a row ? If so halt rather than reboot
* since 8 panics in a row without 1 clean halt means something is
* seriously wrong.
*/
if (cmos_read(RTC_ADDR_REBOOTCNT) > 8)
howto |= RB_HALT;
/*
* If we are rebooting on a panic then up the reboot count
* otherwise reset.
* This will thus be reset if the kernel changes the boot action from
* reboot to halt due to too any reboots.
*/
if (((howto & RB_HALT) == 0) && panicstr)
cmos_write(RTC_ADDR_REBOOTCNT,
cmos_read(RTC_ADDR_REBOOTCNT) + 1);
else
cmos_write(RTC_ADDR_REBOOTCNT, 0);
/*
* If we need a RiscBSD reboot, request it buy setting a bit in
* the CMOS RAM. This can be detected by the RiscBSD boot loader
* during a RISCOS boot. No other way to do this as RISCOS is in ROM.
*/
if ((howto & RB_HALT) == 0)
cmos_write(RTC_ADDR_BOOTOPTS,
cmos_read(RTC_ADDR_BOOTOPTS) | 0x02);
/* Run any shutdown hooks */
doshutdownhooks();
/* Make sure IRQ's are disabled */
IRQdisable;
if (howto & RB_HALT) {
printf("The operating system has halted.\n");
printf("Please press any key to reboot.\n\n");
cngetc();
}
printf("rebooting...\n");
cpu_reset();
/*NOTREACHED*/
}
char bootstring[64];
char bootargs[32];
void setleds();
u_int
initarm(prom_id)
struct prom_id *prom_id;
{
int loop;
int loop1;
u_int kerneldatasize;
u_int l1pagetable;
u_int l2pagetable;
u_int vdrambase;
u_int reserv_mem;
extern char page0[], page0_end[];
/* struct exec *kernexec = (struct exec *)KERNEL_TEXT_BASE;*/
pv_addr_t kernel_l1pt;
pv_addr_t kernel_ptpt;
/*
* Heads up ... Setup the CPU / MMU / TLB functions
*/
set_cpufuncs();
/*
* XXXX - FIX ME
*/
/* cpu_cache = 0x03;*/
boothowto = 0;
#ifndef MEMORY_DISK_SIZE
#define MEMORY_DISK_SIZE 0
#endif
memory_disc_size = MEMORY_DISK_SIZE * 1024;
#ifdef MEMORY_DISK_HOOKS
boot_args = "root=/dev/md0a";
#else
if (strcmp(prom_id->bootdev, "fd") == 0) {
boot_args = "root=/dev/fd0a";
} else {
strcpy(bootstring, "root=/dev/");
strcat(bootstring, prom_id->bootdev);
if (((prom_id->bootdevnum >> B_UNITSHIFT) & B_UNITMASK) == 0)
strcat(bootstring, "0a");
else
strcat(bootstring, "1a");
boot_args = bootstring;
}
#endif
strcpy(bootargs, prom_id->bootargs);
process_kernel_args();
IRQdisable;
/*
* The old version of ROM did not set kstart field which
* will be 0. The ROM reserve 32K bytes of memory at
* low memory location. I need to fix this!!!
*/
if (prom_id->kstart == 0 || !(prom_id->kstart & 0x10000000))
reserv_mem = 0x8000;
else
reserv_mem = prom_id->kstart - prom_id->physmem_start;
bootconfig.kernvirtualbase = KERNEL_BASE;
bootconfig.kernphysicalbase = 0x10000000 + reserv_mem;
bootconfig.kernsize = (prom_id->ksize + NBPG - 1) & PG_FRAME;
bootconfig.display_start = 0x10000000 + prom_id->video_start;
bootconfig.display_size = prom_id->video_size;
bootconfig.width = prom_id->display_width - 1;
bootconfig.height = prom_id->display_height - 1;
bootconfig.bitsperpixel = 3; /* it's actually 8 */
bootconfig.dram[0].address = prom_id->physmem_start;
bootconfig.dram[0].pages = prom_id->ramsize / NBPG;
bootconfig.dramblocks = 1;
bootconfig.pagesize = 4096;
bootconfig.drampages = prom_id->ramsize / NBPG;
strcpy(&bootconfig.kernelname[0], prom_id->bootfile);
bootconfig.framerate = 0;
/*
videodram_size = 0x100000;
*/
videomemory.vidm_pbase = prom_id->physmem_end - videodram_size;
vdrambase = videomemory.vidm_pbase;
bootconfig.display_start = VMEM_VBASE;
/*
* Note: The video memory is not part of the managed memory.
* Exclude these memory off the available DRAM.
*/
bootconfig.dram[0].pages -= videodram_size / NBPG;
bootconfig.drampages -= videodram_size / NBPG;
#ifdef PROM_DEBUG
/*
* Initialise the prom console
*/
init_prom_interface();
/* Talk to the user */
printf("initarm...\n");
printf("Kernel loaded from file %s\n", bootconfig.kernelname);
#endif
/* Check to make sure the page size is correct */
if (NBPG != bootconfig.pagesize)
panic("Page size is not %d bytes\n", NBPG);
/*
* Ok now we have the hard bit.
* We have the kernel allocated up high. The rest of the memory map is
* available. We are still running on RISC OS page tables.
*
* We need to construct new page tables move the kernel in physical
* memory and switch to them.
*
* The booter will have left us 6 pages at the top of memory.
* Two of these are used as L2 page tables and the other 4 form the L1
* page table.
*/
/*
* Ok we must construct own own page table tables.
* Once we have these we can reorganise the memory as required
*/
/*
* We better check to make sure the booter has set up the scratch
* area for us correctly. We use this area to create temporary
* pagetables while we reorganise the memory map.
*/
/*
* Update the videomemory structure to reflect the mapping changes
*/
videomemory.vidm_vbase = VMEM_VBASE;
videomemory.vidm_pbase = vdrambase;
videomemory.vidm_type = VIDEOMEM_TYPE_DRAM;
videomemory.vidm_size = videodram_size;
vidc_base = (int *) VIDC_BASE;
iomd_base = (int *) IOMD_BASE;
kerneldatasize = bootconfig.kernsize + bootconfig.argsize;
/*
* Ok we have finished the primary boot strap. All this has done is to
* allow us to access all the physical memory from known virtual
* location. We also now know that all the used pages are at the top
* of the physical memory and where they are in the virtual memory map.
*
* This should be the stage we are at at the end of the bootstrap when
* we have a two stage booter.
*
* The secondary bootstrap has the responsibility to sort locating the
* kernel to the correct address and for creating the kernel page
* tables. It must also set up various memory pointers that are used
* by pmap etc.
*/
#ifdef PROM_DEBUG
printf("initarm: Secondary bootstrap ... ");
#endif
/*
* Set up the variables that define the availablilty of physcial
* memory
*/
physical_start = bootconfig.dram[0].address;
physical_freestart = physical_start + reserv_mem;
physical_end = bootconfig.dram[bootconfig.dramblocks - 1].address
+ bootconfig.dram[bootconfig.dramblocks - 1].pages * NBPG;
physical_freeend = physical_end;
free_pages = bootconfig.drampages - reserv_mem / NBPG;
bootconfig.dram[0].address += reserv_mem;
bootconfig.dram[0].pages -= reserv_mem / NBPG;
for (loop = 0; loop < bootconfig.dramblocks; ++loop)
physmem += bootconfig.dram[loop].pages;
#ifdef PROM_DEBUG
printf("physical_start=%lx, physical_freestart=%lx, physical_end=%x,"
" physical_freeend=%lx, free_pages=%x\n",
physical_start, physical_freestart,
physical_end, physical_freeend, free_pages);
#endif
/*
* Reserve some pages at the top of the memory for later use
*
* This area is not currently used but could be used for the allocation
* of L1 page tables for each process.
* The size of this memory would be determined by the maximum number of
* processes.
*
* For the moment we just reserve a few pages just to make sure the
* system copes.
*/
#if 0
/*
* Note: The DRAM video memory is already excluded from
* the free physical memory.
*/
physical_freeend -= videodram_size;
free_pages -= (videodram_size / NBPG);
videodram_start = physical_freeend;
#endif
#ifdef PROM_DEBUG
printf("physical_start=%lx, physical_freestart=%lx, physical_end=%lx,"
" physical_freeend=%lx, free_pages=%x\n",
physical_start, physical_freestart,
physical_end, physical_freeend, free_pages);
#endif
/* Right We have the bottom meg of memory mapped to 0x00000000
* so was can get at it. The kernel will ocupy the start of it.
* After the kernel/args we allocate some of the fixed page tables
* we need to get the system going.
* We allocate one page directory and 8 page tables and store the
* physical addresses in the kernel_pt_table array.
* Must remember that neither the page L1 or L2 page tables are the same
* size as a page !
*
* Ok the next bit of physical allocate may look complex but it is
* simple really. I have done it like this so that no memory gets wasted
* during the allocate of various pages and tables that are all different
* sizes.
* The start address will be page aligned.
* We allocate the kernel page directory on the first free 16KB boundry
* we find.
* We allocate the kernel page tables on the first 1KB boundry we find.
* We allocate 9 PT's. This means that in the process we
* KNOW that we will encounter at least 1 16KB boundry.
*
* Eventually if the top end of the memory gets used for process L1 page
* tables the kernel L1 page table may be moved up there.
*/
#ifdef VERBOSE_INIT_ARM
printf("Allocating page tables\n");
#endif
/* Update the address of the first free page of physical memory */
physical_freestart = physical_start + kerneldatasize + reserv_mem;
free_pages -= (physical_freestart - physical_start) / NBPG;
/* Define a macro to simplify memory allocation */
#define valloc_pages(var, np) \
alloc_pages((var).pv_pa, (np)); \
(var).pv_va = KERNEL_BASE + (var).pv_pa - physical_start;
#define alloc_pages(var, np) \
(var) = physical_freestart; \
physical_freestart += ((np) * NBPG); \
free_pages -= (np); \
memset((char *)(var) - physical_start, 0, ((np) * NBPG));
loop1 = 0;
kernel_l1pt.pv_pa = 0;
for (loop = 0; loop <= NUM_KERNEL_PTS; ++loop) {
/* Are we 16KB aligned for an L1 ? */
if ((physical_freestart & (PD_SIZE - 1)) == 0
&& kernel_l1pt.pv_pa == 0) {
valloc_pages(kernel_l1pt, PD_SIZE / NBPG);
} else {
alloc_pages(kernel_pt_table[loop1], PT_SIZE / NBPG);
++loop1;
}
}
#ifdef PROM_DEBUG
/* A bit of debugging info */
for (loop = 0; loop < 10; ++loop)
printf("%d - P%08x\n", loop, kernel_pt_table[loop]);
#endif
#ifdef DIAGNOSTIC
/* This should never be able to happen but better confirm that. */
if (!kernel_l1pt.pv_pa || (kernel_l1pt.pv_pa & (PD_SIZE-1)) != 0)
panic("initarm: Failed to align the kernel page directory\n");
#endif
#ifdef PROM_DEBUG
printf("physical_fs=%08lx next_phys=%08lx\n", physical_freestart,
pmap_next_phys_page(physical_freestart - NBPG));
#endif
/*
* Allocate a page for the system page mapped to V0x00000000
* This page will just contain the system vectors and can be
* shared by all processes.
*/
alloc_pages(systempage.pv_pa, 1);
#ifdef PROM_DEBUG
printf("(0)physical_fs=%08lx next_phys=%08lx\n", physical_freestart,
pmap_next_phys_page(physical_freestart - NBPG));
#endif
/* Allocate a page for the page table to map kernel page tables*/
valloc_pages(kernel_ptpt, PT_SIZE / NBPG);
/* Allocate stacks for all modes */
valloc_pages(fiqstack, FIQ_STACK_SIZE);
valloc_pages(irqstack, IRQ_STACK_SIZE);
valloc_pages(abtstack, ABT_STACK_SIZE);
valloc_pages(undstack, UND_STACK_SIZE);
valloc_pages(kernelstack, UPAGES);
#ifdef VERBOSE_INIT_ARM
printf("IRQ stack: p0x%08lx v0x%08lx\n", irqstack.pv_pa, irqstack.pv_va);
printf("ABT stack: p0x%08lx v0x%08lx\n", abtstack.pv_pa, abtstack.pv_va);
printf("UND stack: p0x%08lx v0x%08lx\n", undstack.pv_pa, undstack.pv_va);
printf("SVC stack: p0x%08lx v0x%08lx\n", kernelstack.pv_pa, kernelstack.pv_va);
#endif
#ifdef PROM_DEBUG
printf("(1)physical_fs=%08lx next_phys=%08lx\n", physical_freestart,
(pmap_next_phys_page(physical_freestart - NBPG));
#endif
alloc_pages(msgbufphys, round_page(MSGBUFSIZE) / NBPG);
#ifdef PROM_DEBUG
printf("physical_fs=%08lx next_phys=%08lx\n", physical_freestart,
pmap_next_phys_page(physical_freestart - NBPG));
#endif
/*
* Ok we have allocated physical pages for the primary kernel
* page tables
*/
#ifdef VERBOSE_INIT_ARM
printf("Creating L1 page table\n");
#endif
/*
* Now we start consturction of the L1 page table
* We start by mapping the L2 page tables into the L1.
* This means that we can replace L1 mappings later on if necessary
*/
l1pagetable = kernel_l1pt.pv_pa - physical_start;
/* Map the L2 pages tables in the L1 page table */
map_pagetable(l1pagetable, 0x00000000,
kernel_pt_table[KERNEL_PT_SYS]);
map_pagetable(l1pagetable, KERNEL_BASE,
kernel_pt_table[KERNEL_PT_KERNEL]);
for (loop = 0; loop < KERNEL_PT_VMDATA_NUM; ++loop)
map_pagetable(l1pagetable, KERNEL_VM_BASE + loop * 0x00400000,
kernel_pt_table[KERNEL_PT_VMDATA + loop]);
map_pagetable(l1pagetable, PROCESS_PAGE_TBLS_BASE,
kernel_ptpt.pv_pa);
map_pagetable(l1pagetable, VMEM_VBASE,
kernel_pt_table[KERNEL_PT_VMEM]);
#ifdef VERBOSE_INIT_ARM
printf("Mapping kernel\n");
#endif
/* Now we fill in the L2 pagetable for the kernel code/data */
l2pagetable = kernel_pt_table[KERNEL_PT_KERNEL] - physical_start;
map_chunk(0, l2pagetable, KERNEL_TEXT_BASE,
physical_start + reserv_mem, kerneldatasize,
AP_KRW, PT_CACHEABLE);
#ifdef VERBOSE_INIT_ARM
printf("Constructing L2 page tables\n");
#endif
/* Map the stack pages */
map_chunk(0, l2pagetable, fiqstack.pv_va, fiqstack.pv_pa,
FIQ_STACK_SIZE * NBPG, AP_KRW, PT_CACHEABLE);
map_chunk(0, l2pagetable, irqstack.pv_va, irqstack.pv_pa,
IRQ_STACK_SIZE * NBPG, AP_KRW, PT_CACHEABLE);
map_chunk(0, l2pagetable, abtstack.pv_va, abtstack.pv_pa,
ABT_STACK_SIZE * NBPG, AP_KRW, PT_CACHEABLE);
map_chunk(0, l2pagetable, undstack.pv_va, undstack.pv_pa,
UND_STACK_SIZE * NBPG, AP_KRW, PT_CACHEABLE);
map_chunk(0, l2pagetable, kernelstack.pv_va, kernelstack.pv_pa,
UPAGES * NBPG, AP_KRW, PT_CACHEABLE);
map_chunk(0, l2pagetable, kernel_l1pt.pv_va, kernel_l1pt.pv_pa,
PD_SIZE, AP_KRW, 0);
/* Map the page table that maps the kernel pages */
map_entry_nc(l2pagetable, kernel_ptpt.pv_pa - physical_start,
kernel_ptpt.pv_pa);
/* Now we fill in the L2 pagetable for the VRAM */
/*
* Current architectures mean that the VRAM is always in 1 continuous
* bank.
* This means that we can just map the 2 meg that the VRAM would occupy.
* In theory we don't need a page table for VRAM, we could section map
* it but we would need the page tables if DRAM was in use.
*/
l2pagetable = kernel_pt_table[KERNEL_PT_VMEM] - physical_start;
map_chunk(0, l2pagetable, VMEM_VBASE, vdrambase,
videodram_size, AP_KRW, PT_CACHEABLE);
map_chunk(0, l2pagetable, VMEM_VBASE + videodram_size, vdrambase,
videodram_size, AP_KRW, PT_CACHEABLE);
/*
* Map entries in the page table used to map PTE's
* Basically every kernel page table gets mapped here
*/
/* The -2 is slightly bogus, it should be -log2(sizeof(pt_entry_t)) */
l2pagetable = kernel_ptpt.pv_pa - physical_start;
map_entry(l2pagetable, (KERNEL_BASE >> (PGSHIFT-2)),
kernel_pt_table[KERNEL_PT_KERNEL]);
map_entry(l2pagetable, (PROCESS_PAGE_TBLS_BASE >> (PGSHIFT-2)),
kernel_ptpt.pv_pa);
map_entry(l2pagetable, (VMEM_VBASE >> (PGSHIFT-2)),
kernel_pt_table[KERNEL_PT_VMEM]);
map_entry(l2pagetable, (0x00000000 >> (PGSHIFT-2)),
kernel_pt_table[KERNEL_PT_SYS]);
for (loop = 0; loop < KERNEL_PT_VMDATA_NUM; ++loop) {
map_entry_nc(l2pagetable, ((KERNEL_VM_BASE +
(loop * 0x00400000)) >> (PGSHIFT-2)),
kernel_pt_table[KERNEL_PT_VMDATA + loop]);
}
/*
* Map the system page in the kernel page table for the bottom 1Meg
* of the virtual memory map.
*/
l2pagetable = kernel_pt_table[KERNEL_PT_SYS] - physical_start;
map_entry(l2pagetable, 0x0000000, systempage.pv_pa);
/* Map the VIDC20, IOMD, COMBO and podules */
/* Map the VIDC20 */
map_section(l1pagetable, VIDC_BASE, VIDC_HW_BASE, 0);
/* Map the IOMD (and SLOW and MEDIUM simple podules) */
map_section(l1pagetable, IOMD_BASE, IOMD_HW_BASE, 0);
/* Map the COMBO (and module space) */
map_section(l1pagetable, IO_BASE, IO_HW_BASE, 0);
#ifdef PROM_DEBUG
/* Bit more debugging info */
printf("page tables look like this ...\n");
printf("V0x00000000 - %08x\n", ReadWord(l1pagetable + 0x0000));
printf("V0x03200000 - %08x\n", ReadWord(l1pagetable + 0x00c8));
printf("V0x03500000 - %08x\n", ReadWord(l1pagetable + 0x00d4));
printf("V0xf0000000 - %08x\n", ReadWord(l1pagetable + 0x3c00));
printf("V0xf1000000 - %08x\n", ReadWord(l1pagetable + 0x3c40));
printf("V0xf2000000 - %08x\n", ReadWord(l1pagetable + 0x3c80));
printf("V0xf3000000 - %08x\n", ReadWord(l1pagetable + 0x3cc0));
printf("V0xf3300000 - %08x\n", ReadWord(l1pagetable + 0x3ccc));
printf("V0xf4000000 - %08x\n", ReadWord(l1pagetable + 0x3d00));
printf("V0xf6000000 - %08x\n", ReadWord(l1pagetable + 0x3d80));
printf("V0xefc00000 - %08x\n", ReadWord(l1pagetable + 0x3bf8));
printf("V0xef800000 - %08x\n", ReadWord(l1pagetable + 0x3bfc));
promcngetc();
#endif
/*
* Now we have the real page tables in place so we can switch to them.
* Once this is done we will be running with the REAL kernel page tables.
*/
/*
* The last thing we must do is copy the kernel down to the new memory.
* This copies all our kernel data structures and variables as well
* which is why it is left to the last moment.
*/
#if 0
memcpy((char *)0x00000000, (char *)KERNEL_TEXT_BASE, kerneldatasize);
#endif
cpu_domains(DOMAIN_CLIENT);
/*
* When we get here, the ROM is still running, we need to
* turn all the interrupts off before switching TTB.
*/
irq_init();
IRQdisable;
setleds(LEDOFF); /* turns off LEDs */
/* Switch tables */
#ifdef VERBOSE_INIT_ARM
printf("switching to new L1 page table\n");
#endif
setttb(kernel_l1pt.pv_pa);
/*
* We must now clean the cache again....
* Cleaning may be done by reading new data to displace any
* dirty data in the cache. This will have happened in setttb()
* but since we are boot strapping the addresses used for the read
* may have just been remapped and thus the cache could be out
* of sync. A re-clean after the switch will cure this.
* After booting there are no gross reloations of the kernel thus
* this problem wil not occur after initarm().
*/
cpu_cache_cleanID();
setleds(LEDALL);
consinit();
setleds(LEDOFF);
/* Right set up the vectors at the bottom of page 0 */
memcpy((char *)0x00000000, page0, page0_end - page0);
/* We have modified a text page so sync the icache */
cpu_cache_syncI_rng(0, page0_end - page0);
/*
* Pages were allocated during the secondary bootstrap for the
* stacks for different CPU modes.
* We must now set the r13 registers in the different CPU modes to
* point to these stacks.
* Since the ARM stacks use STMFD etc. we must set r13 to the top end
* of the stack memory.
*/
printf("init subsystems: stacks ");
set_stackptr(PSR_FIQ32_MODE, fiqstack.pv_va + FIQ_STACK_SIZE * NBPG);
set_stackptr(PSR_IRQ32_MODE, irqstack.pv_va + IRQ_STACK_SIZE * NBPG);
set_stackptr(PSR_ABT32_MODE, abtstack.pv_va + ABT_STACK_SIZE * NBPG);
set_stackptr(PSR_UND32_MODE, undstack.pv_va + UND_STACK_SIZE * NBPG);
/*
* Well we should set a data abort handler.
* Once things get going this will change as we will need a proper handler.
* Until then we will use a handler that just panics but tells us
* why.
* Initialisation of the vectors will just panic on a data abort.
* This just fills in a slighly better one.
*/
printf("vectors ");
data_abort_handler_address = (u_int)data_abort_handler;
prefetch_abort_handler_address = (u_int)prefetch_abort_handler;
undefined_handler_address = (u_int)undefinedinstruction_bounce;
#if 0
/* Diagnostic stuff. while writing the boot code */
for (loop = 0x0; loop < 0x1000; ++loop) {
if (ReadWord(PAGE_DIRS_BASE + loop * 4) != 0)
printf("Pagetable for V%08x = %08x\n", loop << 20,
ReadWord(0xf2000000 + loop * 4));
}
for (loop = 0x0; loop < 0x400; ++loop) {
if (ReadWord(kernel_pt_table[KERNEL_PT_PTE] + loop * 4) != 0)
printf("Pagetable for V%08x P%08x = %08x\n",
loop << 22, kernel_pt_table[KERNEL_PT_PTE]+loop*4,
ReadWord(kernel_pt_table[KERNEL_PT_PTE]+loop * 4));
}
#endif
/* At last !
* We now have the kernel in physical memory from the bottom upwards.
* Kernel page tables are physically above this.
* The kernel is mapped to 0xf0000000
* The kernel data PTs will handle the mapping of 0xf1000000-0xf1ffffff
* 2Meg of VRAM is mapped to 0xf4000000
* The page tables are mapped to 0xefc00000
* The IOMD is mapped to 0xf6000000
* The VIDC is mapped to 0xf6100000
*/
/* Initialise the undefined instruction handlers */
printf("undefined ");
undefined_init();
console_flush();
/* Boot strap pmap telling it where the kernel page table is */
printf("pmap ");
pmap_bootstrap((pd_entry_t *) kernel_l1pt.pv_va, kernel_ptpt);
console_flush();
/* Setup the IRQ system */
printf("irq ");
console_flush();
irq_init();
printf("done.\n");
#ifdef IPKDB
/* Initialise ipkdb */
ipkdb_init();
if (boothowto & RB_KDB)
ipkdb_connect(0);
#endif
#ifdef DDB
printf("ddb: ");
db_machine_init();
{
extern int end;
extern int *esym;
ddb_init(*(int *)&end, ((int *)&end) + 1, esym);
}
if (boothowto & RB_KDB)
Debugger();
#endif
/* We return the new stack pointer address */
return(kernelstack.pv_va + USPACE_SVC_STACK_TOP);
}
static void
process_kernel_args(void)
{
parse_mi_bootargs(bootargs);
parse_rc7500_bootargs(bootargs);
}
void
parse_rc7500_bootargs(args)
char *args;
{
int integer;
videodram_size = 0x100000;
if (get_bootconf_option(args, "m", BOOTOPT_TYPE_INT, &integer)) {
if (integer >= 2 || integer <= 4)
videodram_size *= integer;
}
}
void
setleds(led)
int led;
{
outb(LEDPORT, ~led & 0xff);
}
/* End of rc7500_machdep.c */

101
sys/arch/arm32/rc7500/rc7500_prom.c
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@ -1,101 +0,0 @@
/* $NetBSD: rc7500_prom.c,v 1.3 2000/03/06 21:36:06 thorpej Exp $ */
/*
* Copyright (c) 1992, 1994, 1995 Carnegie Mellon University
* All Rights Reserved.
*
* Permission to use, copy, modify and distribute this software and its
* documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
* ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie Mellon
* the rights to redistribute these changes.
*/
#include <sys/param.h>
#include <arm32/dev/rc7500_prom.h>
#include <dev/cons.h>
/* XXX this is to fake out the console routines, while booting. */
void promcnputc __P((dev_t, int));
int promcngetc __P((dev_t));
struct consdev promcons = { NULL, NULL, promcngetc, promcnputc,
nullcnpollc, NULL, makedev(23,0), 1 };
void
init_prom_interface()
{
/* XXX fake out the console routines, for now */
cn_tab = &promcons;
}
/*
* promcnputc:
*
* Remap char before passing off to prom.
*
* Prom only takes 32 bit addresses. Copy char somewhere prom can
* find it. This routine will stop working after pmap_rid_of_console
* is called in alpha_init. This is due to the hard coded address
* of the console area.
*/
void
promcnputc(dev, c)
dev_t dev;
int c;
{
prom_putchar(c);
}
/*
* promcngetc:
*
* Wait for the prom to get a real char and pass it back.
*/
int
promcngetc(dev)
dev_t dev;
{
int ret;
for (;;) {
ret = prom_getchar();
if (ret != -1)
return(ret);
}
}
/*
* promcnlookc:
*
* See if prom has a real char and pass it back.
*/
int
promcnlookc(dev, cp)
dev_t dev;
char *cp;
{
int ret;
ret = prom_getchar();
if (ret != -1) {
*cp = ret;
return 1;
} else
return 0;
}

81
sys/arch/arm32/rc7500/rc7500_prom.h
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@ -1,81 +0,0 @@
/* $NetBSD: rc7500_prom.h,v 1.2 1997/10/14 10:49:55 mark Exp $ */
/*
* Copyright (c) 1996, Danny C Tsen.
* Copyright (c) 1996, VLSI Technology Inc. All Rights Reserved.
* Copyright (c) 1995 Michael L. Hitch
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Michael L. Hitch.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _PROM_H_
#define _PROM_H_
#ifndef _LOCORE
/*
* This is the data returned in PROM_GETENV.
*/
struct prom_id {
u_int ramsize;
u_int physmem_start;
u_int physmem_end;
u_int video_start;
u_int video_size;
u_int display_width;
u_int display_height;
u_int tlb; /* translation table base */
u_int tlbsize;
u_int ksize; /* kernel size */
u_int kstart; /* kernel start address */
char bootdev[32];
char bootfile[32];
char bootargs[32];
u_int bootdevnum;
};
#endif /* _LOCORE */
#define PROM_REBOOT 0x06
#define PROM_GETENV 0x07
#define PROM_PUTCHAR 0x08
#define PROM_PUTS 0x09
#define PROM_GETCHAR 0x0A
#define PROM_OPEN 0x0B
#define PROM_CLOSE 0x0C
#define PROM_READ 0x0D
#ifndef _LOCORE
extern int prom_putchar(int c);
extern void prom_puts(char *s);
extern int prom_getchar(void);
extern char *prom_getenv(void);
extern int prom_open(char *dev_name, u_int devnum);
extern int prom_close(int dev);
extern int prom_read(int dev, char *io);
extern void prom_reboot(void);
#endif /* _LOCORE */
#endif /* _PROM_H_ */

76
sys/arch/arm32/rc7500/rc7500_promsys.S
View File

@ -1,76 +0,0 @@
/* $NetBSD: rc7500_promsys.S,v 1.3 1998/04/01 23:02:33 mark Exp $ */
/*
* Copyright (c) 1996, Danny C Tsen.
* Copyright (c) 1996, VLSI Technology Inc. All Rights Reserved.
* Copyright (c) 1995 Michael L. Hitch
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Michael L. Hitch.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <machine/asm.h>
ENTRY(prom_reboot)
stmdb sp!, {lr}
swi 0x06
ldmia sp!, {pc}
ENTRY(prom_getenv)
stmdb sp!, {lr}
swi 0x07
ldmia sp!, {pc}
ENTRY(prom_putchar)
stmdb sp!, {lr}
swi 0x08
ldmia sp!, {pc}
ENTRY(prom_puts)
stmdb sp!, {r0, lr}
swi 0x09
ldmia sp!, {r0, pc}
ENTRY(prom_getchar)
stmdb sp!, {lr}
swi 0x0a
ldmia sp!, {pc}
ENTRY(prom_open)
stmdb sp!, {lr}
swi 0x0b
ldmia sp!, {pc}
ENTRY(prom_close)
stmdb sp!, {lr}
swi 0x0c
ldmia sp!, {pc}
ENTRY(prom_read)
stmdb sp!, {lr}
swi 0x0d
ldmia sp!, {pc}

509
sys/arch/arm32/riscpc/rpc_kbd_map.c
View File

@ -1,509 +0,0 @@
/* $NetBSD: rpc_kbd_map.c,v 1.1 1997/10/14 10:55:48 mark Exp $ */
/*
* Copyright (c) 1994-1997 Mark Brinicombe.
* Copyright (c) 1994 Brini.
* All rights reserved.
*
* This code is derived from software written for Brini by Mark Brinicombe
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Mark Brinicombe.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RiscBSD kernel project
*
* kbd.c
*
* Keyboard driver functions
*
* Created : 09/10/94
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/proc.h>
#include <sys/device.h>
#include <sys/tty.h>
#include <sys/select.h>
#include <machine/bus.h>
#include <arm32/dev/kbdvar.h>
/* Define mappings for each possible code */
key_struct keys[256] = {
/* 0x00 - 0x0f */
{ 0x00, 0x00, 0x00, 0x00, 0x80 },
{ 0x89, 0x99, 0x00, 0x489, 0x00 },
{ 0x8a, 0x9a, 0x00, 0x00, 0x00 },
{ 0x85, 0x95, 0x00, 0x485, 0x00 },
{ 0x83, 0x93, 0x00, 0x483, 0x00 },
{ 0x81, 0x91, 0x00, 0x481, 0x00 },
{ 0x82, 0x92, 0x00, 0x482, 0x00 },
{ 0x8c, 0x9c, 0x00, 0x48c, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x88, 0x98, 0x00, 0x488, 0x00 },
{ 0x86, 0x96, 0x00, 0x486, 0x00 },
{ 0x84, 0x94, 0x00, 0x484, 0x00 },
{ 0x09, 0x09, 0x09, 0x09, 0x00 },
#ifdef RC7500
{ 0x60, 0x7e, 0x00, 0x00, 0x00 },
#else
{ 0x60, 0x00, 0x00, 0x00, 0x00 },
#endif
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
/* 0x10 - 0x1f */
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x84 },
{ 0x00, 0x00, 0x00, 0x00, 0x82 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x81 },
{ 0x71, 0x51, 0x11, 0x00, 0x40 },
{ 0x31, 0x21, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x7a, 0x5a, 0x1a, 0x00, 0x40 },
{ 0x73, 0x53, 0x13, 0x00, 0x40 },
{ 0x61, 0x41, 0x01, 0x00, 0x40 },
{ 0x77, 0x57, 0x17, 0x00, 0x40 },
{ 0x32, 0x22, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
/* 0x20 - 0x2f */
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x63, 0x43, 0x03, 0x00, 0x40 },
{ 0x78, 0x58, 0x18, 0x00, 0x40 },
{ 0x64, 0x44, 0x04, 0x00, 0x40 },
{ 0x65, 0x45, 0x05, 0x00, 0x40 },
{ 0x34, 0x24, 0x00, 0x00, 0x00 },
{ 0x33, 0x23, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x20, 0x20, 0x20, 0x20, 0x00 },
{ 0x76, 0x56, 0x16, 0x00, 0x40 },
{ 0x66, 0x46, 0x06, 0x00, 0x40 },
{ 0x74, 0x54, 0x14, 0x00, 0x40 },
{ 0x72, 0x52, 0x12, 0x00, 0x40 },
{ 0x35, 0x25, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
/* 0x30 - 0x3f */
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x6e, 0x4e, 0x0e, 0x00, 0x40 },
{ 0x62, 0x42, 0x02, 0x00, 0x40 },
{ 0x68, 0x48, 0x08, 0x00, 0x40 },
{ 0x67, 0x47, 0x07, 0x00, 0x40 },
{ 0x79, 0x59, 0x19, 0x00, 0x40 },
{ 0x36, 0x5e, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x6d, 0x4d, 0x0d, 0x00, 0x40 },
{ 0x6a, 0x4a, 0x0a, 0x00, 0x40 },
{ 0x75, 0x55, 0x15, 0x00, 0x40 },
{ 0x37, 0x26, 0x00, 0x00, 0x00 },
{ 0x38, 0x2a, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
/* 0x40 - 0x4f */
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x2c, 0x3c, 0x00, 0x00, 0x00 },
{ 0x6b, 0x4b, 0x0b, 0x00, 0x40 },
{ 0x69, 0x49, 0x09, 0x00, 0x40 },
{ 0x6f, 0x4f, 0x0f, 0x00, 0x40 },
{ 0x30, 0x29, 0x00, 0x00, 0x00 },
{ 0x39, 0x28, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x2e, 0x3e, 0x00, 0x00, 0x00 },
{ 0x2f, 0x3f, 0x00, 0x00, 0x00 },
{ 0x6c, 0x4c, 0x0c, 0x00, 0x40 },
{ 0x3b, 0x3a, 0x00, 0x00, 0x00 },
{ 0x70, 0x50, 0x10, 0x00, 0x40 },
{ 0x2d, 0x5f, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
/* 0x50 - 0x5f */
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
#ifdef RC7500
{ 0x27, 0x22, 0x00, 0x00, 0x00 },
#else
{ 0x27, 0x40, 0x00, 0x00, 0x00 },
#endif
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x5b, 0x7b, 0x00, 0x00, 0x00 },
{ 0x3d, 0x2b, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0xa0 },
{ 0x00, 0x00, 0x00, 0x00, 0x82 },
{ 0x0d, 0x0d, 0x0d, 0x00, 0x00 },
{ 0x5d, 0x7d, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
#ifdef RC7500
{ 0x5c, 0x7c, 0x00, 0x00, 0x00 },
#else
{ 0x23, 0x7e, 0x00, 0x00, 0x00 },
#endif
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
/* 0x60 - 0x6f */
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x5c, 0x7c, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x08, 0x7f, 0x08, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x31, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x34, 0x00, 0x00, 0x00, 0x00 },
{ 0x37, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
/* 0x70 - 0x7f */
{ 0x30, 0x00, 0x00, 0x00, 0x00 },
{ 0x2e, 0x00, 0x00, 0x00, 0x00 },
{ 0x32, 0x00, 0x00, 0x00, 0x00 },
{ 0x35, 0x00, 0x00, 0x00, 0x00 },
{ 0x36, 0x00, 0x00, 0x00, 0x00 },
{ 0x38, 0x00, 0x00, 0x00, 0x00 },
{ 0x1b, 0x1b, 0x21b, 0x1b, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x90 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x2b, 0x00, 0x00, 0x22b, 0x00 },
{ 0x33, 0x00, 0x00, 0x00, 0x00 },
{ 0x2d, 0x00, 0x00, 0x22d, 0x00 },
{ 0x2a, 0x00, 0x00, 0x00, 0x00 },
{ 0x39, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x88 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
/* 0x80 - 0x8f */
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x87, 0x97, 0x00, 0x487, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
/* 0x90 - 0x9f */
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
/* 0xa0 - 0xaf */
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
/* 0xb0 - 0xbf */
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
/* 0xc0 - 0xcf */
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
/* 0xd0 - 0xdf */
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
/* 0xe0 - 0xef */
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
/* 0xf0 - 0xff */
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 }
};
/* Define mappings for each possible code */
key_struct E0keys[128] = {
/* 0x00 - 0x0f */
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
/* 0x10 - 0x1f */
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x84 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x81 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
/* 0x20 - 0x2f */
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
/* 0x30 - 0x3f */
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
/* 0x40 - 0x4f */
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x2f, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
/* 0x50 - 0x5f */
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x0d, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
/* 0x60 - 0x6f */
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x10b, 0x00, 0x00, 0x20b, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x102, 0x00, 0x00, 0x202, 0x00 },
{ 0x10a, 0x00, 0x00, 0x20a, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
/* 0x70 - 0x7f */
{ 0x108, 0x00, 0x00, 0x208, 0x00 },
{ 0x109, 0x00, 0x00, 0x209, 0x00 },
{ 0x101, 0x105, 0x00, 0x201, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x103, 0x00, 0x00, 0x203, 0x00 },
{ 0x100, 0x104, 0x00, 0x200, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x104, 0x100, 0x00, 0x204, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x105, 0x101, 0x00, 0x205, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00 },
};
/* End of kbd_map.c */

1874
sys/arch/arm32/riscpc/rpc_machdep.c
View File

File diff suppressed because it is too large Load Diff

126
sys/arch/arm32/stand/BtNetBSD/FBInstall
View File

@ -1,126 +0,0 @@
$NetBSD: FBInstall,v 1.1 2001/02/19 14:09:01 reinoud Exp $
Note of FastBoot/AutoBoot Installation for !BtNetBSD V0.90
based on !BtRiscBSD
Updated by Reinoud Zandijk 18 Feb 2001
Author: Mark Brinicombe 12th May 1995
Updated: 20th June 1997
Installation
------------
Two patches are required to the standard boot files
The following lines should be added to the start of
!Boot.Choices.Boot.PreDesktop
----------------------- Cut here -----------------------
|Start NetBSD !Boot FastBoot
Run <Obey$Dir>.^.^.^.BtNetBSD.!BtNetBSD.!Boot
Run <BtNetBSD$Dir>.TestBoot
If "<NetBSD$FastBoot>" = "1" THEN Echo NetBSD FastBoot mode engaged
If "<NetBSD$FastBoot>" = "2" THEN Echo NetBSD ConfBoot mode engaged
If "<NetBSD$FastBoot>" = "3" THEN Echo NetBSD AutoBoot mode engaged
If "<NetBSD$FastBoot>" = "4" THEN Echo NetBSD FastConf mode engaged
|End
----------------------- Cut here -----------------------
These commands should be the first one run in the PreDesktop
file. They boot the boot loader application (primarily to set
BtNetBSD$Dir). The file <BtNetBSD$Dir>.TestBoot is then run
to test for the ALT or CTRL keys are being held down. In addition
it checks several CMOS RAM bits for boot configuration options.
The following lines should be added to the start of
!Boot.Choices.Boot.Desktop
----------------------- Cut here -----------------------
|Start NetBSD !Boot FastBoot
Iconsprites <BtNetBSD$Dir>.!Sprites22
If <NetBSD$FastBoot> = 4 THEN Run <BtNetBSD$Dir>.!Edit
If <NetBSD$FastBoot> > 0 AND <NetBSD$FastBoot> < 4 THEN Obey <BtNetBSD$Dir>.fastboot
|End
----------------------- Cut here -----------------------
This command should be the first one run in the Desktop file.
It runs the NetBSD Bootloader with the configured parameters.
There is a specific reason for not putting all the fastboot code in
one file. The PreDesktop patch is run very early in the boot up so
that the ALT and CTRL keys can be detected quickly. However, currently
the actually bootloader cannot be run at this point unless a lot of
memory is available in the module area (~1Meg) as currently the
module area is used for temporary storage of the kernel being
booted.
This means that the actual boot is prosponed until the start of
the Desktop file. At this point the desktop has been started and
the task manager is running so it will be possible to allocate
a large amount of module space.
Activation
----------
Once installed, to engage the fastboot hold ALT down immediately
after a reset. As soon as the "fastboot engaged" message is printed
the ALT key can be released.
To engage the fastconf mode hold CTRL down immediately
after a reset. As soon as the "fastconf engaged" message is printed
the CTRL key can be released.
Configuration
-------------
Configuration is done via the !BtNetBSD application.
When ever NetBSD is booted the commandline used to boot it is saved
by the bootloader to the file <BtNetBSD$Dir>.FastBoot
Rerunning this file will then boot NetBSD with the last parameters
used. It is this file that the fastboot uses so the fast boot will
boot NetBSD with the same parameters as were used for the last boot.
ConfBoot mode
-------------
This mode is identified by NetBSD$FastBoot being set to 2. This indicates
that the bootloader has been configured to always boot NetBSD. This is
down by setting a bit in the CMOS RAM (via !BtNetBSD).
If NetBSD boots are configured the action of the ALT is reversed so that
holding down ALT will allow a RISC OS boot instead.
AutoBoot mode
-------------
This mode is identified by NetBSD$FastBoot being set to 3. This indicates
that an automatic boot was requested by NetBSD before it rebooted. This
will happen when /sbin/reboot is used instead of /sbin/halt.
FastBoot mode
-------------
This is the behaviour when ALT is held down at boot time and ConfBoot mode
has not been configured. It just bypasses most of the normal startup and
boots NetBSD.
FastConf mode
-------------
This is the behaviour when CTRL is held down at boot time. This is similar to
FastBoot mode except that the !BtNetBSD is provided to allow boot parameters
to be changed.
Bugs
----
Well hopefully there are no bugs :-)

15
sys/arch/arm32/stand/BtNetBSD/README
View File

@ -1,15 +0,0 @@
$NetBSD: README,v 1.1 2001/02/19 14:09:01 reinoud Exp $
Welcome to NetBSD for the Acorn RiscPC/A7000/NC and Imago !
To get this distribution working run `settype' the file `Settype'
to Obey and run this file. It will set all file types in this
directory to the correct RISC OS types. Pity those file types get
lost after retrieving them from the source repository....
To read more about installing the bootloader, read the FBInstall file.
Enjoy your installation !
19 Februari 2001
Reinoud Zandijk

7
sys/arch/arm32/stand/BtNetBSD/Settype
View File

@ -1,7 +0,0 @@
| $NetBSD: Settype,v 1.1 2001/02/19 14:09:01 reinoud Exp $
|
| !!!! please *settype Obey me and run me
|
*Set rel$dir <Obey$dir>
*Exec <obey$Dir>.misc.SettScr

33
sys/arch/arm32/stand/BtNetBSD/misc/Mkrel/MkRelScr
View File

@ -1,33 +0,0 @@
| $NetBSD: MkRelScr,v 1.1 2001/02/19 14:09:02 reinoud Exp $
*BASIC
*DIR <rel$dir>.!BtNetBSD
TEXTLOAD "BtNetBSD"
TEXTSAVEO 8, "BtNetBSD"
TEXTLOAD "checkro403"
TEXTSAVEO 8, "checkro403"
TEXTLOAD "TestBoot"
TEXTSAVEO 8, "TestBoot"
*DIR <rel$dir>.!BtNetBSD.native
TEXTLOAD "MountUFS"
TEXTSAVEO 8, "MountUFS"
*DIR <rel$dir>.!BtNetBSD.src.Banner
TEXTLOAD "Banner"
TEXTSAVEO 8, "Banner"
TEXTLOAD "resutil"
TEXTSAVEO 8, "resutil"
*DIR <rel$dir>.misc
TEXTLOAD "bb_netbsd"
TEXTSAVEO 8, "bb_netbsd"
*DIR <rel$dir>.unixfs
TEXTLOAD "mountufs"
TEXTSAVEO 8, "mountufs"
CLS:VDU 7:PRINT "Please dont forget to uuencode the binaries in NetBSD!"
QUIT

5
sys/arch/arm32/stand/BtNetBSD/misc/Mkrel/MkRelease
View File

@ -1,5 +0,0 @@
| $NetBSD: MkRelease,v 1.1 2001/02/19 14:09:02 reinoud Exp $
*Set rel$dir <Obey$dir>.^.^
*Copy <rel$dir>.unixfs <rel$dir>.!BtNetBSD.native rfv~c
*Exec <obey$Dir>.MkRelScr

66
sys/arch/arm32/stand/BtNetBSD/misc/SettScr
View File

@ -1,66 +0,0 @@
| $NetBSD: SettScr,v 1.1 2001/02/19 14:09:01 reinoud Exp $
*BASIC
*DIR <rel$dir>
*Settype FBInstall text
*Settype README text
*DIR <rel$dir>.!BtNetBSD
TEXTLOAD "BtNetBSD"
SAVE "BtNetBSD"
TEXTLOAD "checkro403"
SAVE "checkro403"
TEXTLOAD "TestBoot"
SAVE "TestBoot"
*Settype !Boot Obey
*Settype !Edit Obey
*Settype !Run Obey
*Settype !Sprites Sprite
*Settype !Sprites22 Sprite
*Settype Banner Module
*Settype MemFix Module
*Settype PreBoot obey
*Settype fastboot Text
*Settype Files Text
*Settype Legal text
*DIR <rel$dir>.!BtNetBSD.native
TEXTLOAD "MountUFS"
SAVE "MountUFS"
*Settype KillUnixFS Obey
*Settype OpenRoot Obey
*Settype unixfs_res Module
*Settype wd0a obey
*Settype wd0d obey
*Settype wd0e obey
*Settype wd0f obey
*Settype wd0g obey
*DIR <rel$dir>.!BtNetBSD.src.Banner
TEXTLOAD "Banner"
SAVE "Banner"
TEXTLOAD "resutil"
SAVE "resutil"
*Settype !Path Obey
*Settype Sprite sprite
*DIR <rel$dir>.misc
TEXTLOAD "bb_netbsd"
SAVE "bb_netbsd"
*Settype SettScr text
*DIR <rel$dir>.unixfs
TEXTLOAD "mountufs"
SAVE "mountufs"
*Settype KillUnixFS Obey
*Settype OpenRoot Obey
*Settype unixfs_res module
*Settype wd0a Obey
*Settype wd0e Obey
*DIR <rel$dir>.misc.MkRel
*Settype MkRelease Obey
*Settype MkRelScr Obey
QUIT

140
sys/arch/arm32/stand/BtNetBSD/misc/bb_netbsd
View File

@ -1,140 +0,0 @@
REM > bb_NetBSD
REM $NetBSD: bb_netbsd,v 1.1 2001/02/19 14:09:01 reinoud Exp $
REM
REM Copyright (c) 1995 Mark Brinicombe
REM All rights reserved
REM
REM Redistribution and use in source and binary forms, with or without
REM modification, are permitted provided that the following conditions
REM are met:
REM 1. Redistributions of source code must retain the above copyright
REM notice, this list of conditions and the following disclaimer.
REM 2. Redistributions in binary form must reproduce the above copyright
REM notice, this list of conditions and the following disclaimer in the
REM documentation and/or other materials provided with the distribution.
REM 3. All advertising materials mentioning features or use of this software
REM must display the following acknowledgement:
REM This product includes software developed by Mark Brinicombe.
REM 4. The name of the company nor the name of the author may be used to
REM endorse or promote products derived from this software without specific
REM prior written permission.
REM
REM THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
REM IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
REM OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
REM IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
REM INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
REM BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
REM OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
REM ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
REM OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
REM THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
REM DAMAGE.
REM
REM NetBSD kernel project
REM
REM bb_NetBSD
REM
REM Modifies the filecore bootblock to point to a section of
REM the disc reserved for NetBSD.
REM
REM Created : 24/11/94
REM Last updated : 12/07/95
REM
DIM buf% 512
REM Get Filesystem type
REPEAT
PRINT "ADFS, ATAFS, IDEFS, SCSI or SCSIFS (A/T/I/S/F) ? ";
filesys% = GET AND &DF
PRINT CHR$(filesys%)
UNTIL filesys%=ASC"A" OR filesys%=ASC"T" OR filesys%=ASC"S" OR filesys%=ASC"I" OR filesys%=ASC"F"
CASE filesys% OF
WHEN ASC"A" : discop$="ADFS_DiscOp"
WHEN ASC"I" : discop$="IDEFS_DiscOp"
WHEN ASC"T" : discop$="ATAFS_DiscOp"
WHEN ASC"S" : discop$="SCSI_DiscOp"
WHEN ASC"F" : discop$="SCSIFS_DiscOp"
ENDCASE
REM Get the drive number
INPUT "Drive "d%
REM Read in current filecore bootblock
SYS discop$,, 1, &c00 + (d% << 29), buf%, 512
SYS "OS_File", 10, "<Wimp$ScrapDir>.OldBB", &FFD,, buf%, buf%+512
PRINT "Old boot block saved in <Wimp$ScrapDir>.OldBB"
REM Get the byte size of the filecore partition and the number
REM of bytes per cylinder
size%=buf%!&1d0
clsize%=buf%?&1c2 * buf%?&1c1 * (1 << buf%?&1c0)
REM A bit of info to the user
PRINT "Filecore partition size = ";~size%;" bytes"
REM Convert the size into cylinders
size% = (size% + clsize% - 1) / clsize%
PRINT "Filecore partition size = ";size%; " cylinders (0-";size%-1;")"
REM We should be clever about here and read the real geometry
REM of the disc so that we know the maximum cylinder number
REM Get the starting cylinder for the NetBSD part of the disc
INPUT "NetBSD Starting Cyl "c%
REM Make sure it is after the filecore partition
IF (c% < size%) THEN
PRINT "Filecore occupies cylinders upto ";size%-1
INPUT "Are you sure you mean this value "a$
IF (a$ <> "yes" AND a$ <> "YES") THEN END
PRINT "This will allow NetBSD to overwrite part of the ADFS partition"
INPUT "Are you really sure you mean this value "a$
IF (a$ <> "yes" AND a$ <> "YES") THEN END
ENDIF
PRINT "Initialising NetBSD partition offset at ";c%
PRINT "On drive ";d%;", using ";discop$;" to access drive"
PRINT "Press any key to continue, escape to abort"
dummy%=GET
REM Modifiy the non-ADFS partition descriptor to describe the
REM start of the NetBSD part of the disc
buf%?&1FC = &42 : REM NetBSD identifier
buf%?&1FD = c% AND 255 : REM low byte of start cylinder
buf%?&1FE = c% >> 8 : REM high byte of start cylinder
REM Recalculate the filecore boot block checksum
buf%?&1FF = FNCheckSum(buf%,511)
REM Write the boot block back to disc
SYS discop$,, 2, &c00 + (d% << 29), buf%, 512
END
DEF FNCheckSum(addr%, length%)
sum% = 0
FOR n% = 0 TO length% - 1
sum% += addr%?n%
IF sum% > 255 THEN
sum% -= 255
ENDIF
NEXT
= sum%

7
sys/arch/arm32/stand/BtNetBSD/pling.BtNetBSD/!Boot
View File

@ -1,7 +0,0 @@
|
| $NetBSD: !Boot,v 1.1 2001/02/19 14:09:02 reinoud Exp $
| boot file for !BtNetBSD application
|
IconSprites <Obey$Dir>.!Sprites
Set File$Type_fe6 Unix
Set BtNetBSD$Dir <Obey$Dir>

9
sys/arch/arm32/stand/BtNetBSD/pling.BtNetBSD/!Edit
View File

@ -1,9 +0,0 @@
| $NetBSD: !Edit,v 1.1 2001/02/19 14:09:02 reinoud Exp $
|
| !Edit file for !BtNetBSD application
|
Set BtNetBSD$Dir <Obey$Dir>
Filer_OpenDir <BtNetBSD$Dir>
Filer_Run <BtNetBSD$Dir>.fastboot

14
sys/arch/arm32/stand/BtNetBSD/pling.BtNetBSD/!Run
View File

@ -1,14 +0,0 @@
| $NetBSD: !Run,v 1.1 2001/02/19 14:09:02 reinoud Exp $
|
| run file for !BtNetBSD application
|
WimpSlot -min 64k -max 64k
IconSprites <Obey$Dir>.!Sprites
Set BtNetBSD$Dir <Obey$Dir>
| First, check if we are running the version of RISC OS 4.03 that
| needs the memfix module
Run <BtNetBSD$Dir>.checkro403
Obey <BtNetBSD$Dir>.fastboot

976
sys/arch/arm32/stand/BtNetBSD/pling.BtNetBSD/Banner,uue
View File

@ -1,976 +0,0 @@
begin 644 Banner
M`````"P````X````D````$@```!8````````````````````````````````
M0"WIE```ZP"`O>@'02WI`,"<Y90``.L'@;WH4FES8T)31%]"86YN97(``%)I
M<V-"4T0@0F%N;F5R"0DP+C(P("@Q,B!*=6QY(#$Y.34I(*D@36%R:R!"<FEN
M:6-O;6)E````?`!1XP(```I@`%'C@0``"P[PL.'_0RWI!0"@X_00C^((``+O
M.0``:@8`H.,0,(3B'@``[S4``&H"@*#A`3B@XP`P@N40`*#C"`""Y0D`H.,!
M#(#C`A"@X2X``N\*`*!S`0R`<ZP@CW(N``)_*`"@<P$,@',($*!QO2"/<BX`
M`G\&`*!Q!!"@<S4``G\3,J!Q!@"@<040H',U``)_%$*@<2<``'L6``!JH`"@
MX:$0H.&C,*#AI$"@X0,P0.`$0$'@,0``ZTT/H.,($*#A:2"/X@!0H.,`8*#C
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M`&=F!@``=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W
M=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W
M=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W
M=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=W=V=F!@``1$1F9F9F
M9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F
M9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F
M9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F
M9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F!@``1$1F9F9F9F9F9F9F9F9F9F9F
M9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F
M9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F
M9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F
M9F9F9F9F9F9F9F9F!@``1$1F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F
M9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F
M9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F
M9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F
M!@``1$1F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F
M9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F
M9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F
H9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F!@```````&9F
`
end

1119
sys/arch/arm32/stand/BtNetBSD/pling.BtNetBSD/BtNetBSD
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File diff suppressed because it is too large Load Diff

26
sys/arch/arm32/stand/BtNetBSD/pling.BtNetBSD/Files
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@ -1,26 +0,0 @@
$NetBSD: Files,v 1.1 2001/02/19 14:09:03 reinoud Exp $
FBInstall - describes how to install
Settype - types all file for RiscOS
List of files of !BtNetBSD :
!Run }
!Boot }
!Help }
!Sprites } Standard Application Files
!Sprites22 }
!Edit - Edits the `fastboot' file
Banner - RiscBSD banner module
BtNetBSD - RiscBSD bootloader
checkro403 - Tests if we're running RO4.03 for MemFix
MemFix - Module repairing memory layout reporting for Kinetic
TestBoot - Fastboot tester
PreBoot - Preboot obey file
native - Native filesystem support directory
native.mountufs - Frontend for mounting ffs partition
native.unixfs_res - Restricted write Unixfs module
fastboot - Fastboot (obey) file in text format
FBInstall - Doc on installing fastboot support
src - Source code
Legal - Contains copyright information

16
sys/arch/arm32/stand/BtNetBSD/pling.BtNetBSD/Legal
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@ -1,16 +0,0 @@
$NetBSD: Legal,v 1.1 2001/02/19 14:09:03 reinoud Exp $
Copyright acknowledgement of the !BtNetBSD application
------------------------------------------------------
The memfix module in the !BtRiscBSD directory is copyright
RISC OS ltd and Castle Technology Ltd. It is included in this
archive with the permission of the copyright holders.
This product is released under a BSD style licence.
This product includes software developed by Mark Brinicombe
This product includes software developed by Reinoud Zandijk
This product includes software developed by the University of California,
Berkeley and its contributors.

19
sys/arch/arm32/stand/BtNetBSD/pling.BtNetBSD/MemFix,uue
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@ -1,19 +0,0 @@
begin 644 MemFix
M`````$````!H`0```````!P````C`````````$UE;49I>`!-96U&:7@)"3`N
M,3$@*#$U($IU;B`R,#`P*0````!`+>F!`*#C`!"@X_\@H.,&``+O-0``:J@`
M,>,S```:"0"@XP$0H.-8``+O+P``:N`0C^(!(-#D`3#1Y`,`,N$J```:```R
MX_G__QH4$I_E``"1Y=P`C^7<`(_B``"!Y0!`H.-D!93E<!64Y0``,>,=```*
M5"*4Y0(0@>"A!(#@!""0Y0$F@N,$((#E#""0Y0$F@N,,((#E%""0Y0$F@N,4
M((#E'""0Y0$F@N,<((#E`#"@XW(OA.(($)+D`@)1X_S__ZH!`E'C`@``N@00
M$N4!,(/@]___ZJ,TH.$$,$/B`R"0YP$F@N,#((#G`("]Z`0`C^("`5_C`("]
MZ`````!);F-O<G)E8W0@3U,@=F5R<VEO;@`````R,#`P,#4P-RTP,#$`````
M.!&?Y00`G^4``('E#O"@X0`````&`##C!P`P$Q3P'Q4`0"WI!@`PXP0```L'
M`##C!0``"P!`O>@$P9_E#/"@X0(8H.,!*J#C#O"@X?Y'+>F`(*#C[#"?Y30`
M`.L.+:#CY#"?Y3$``.L`0*#C5$*4Y0``-..D)Z`1T#"?%2L``!L!1&3BI">@
MX;PPG^4G``#K`2R@X[@PG^4D``#K"2R@XZ0PG^4A``#K`2J@XZ`PG^4>``#K
M!BJ@XXPPG^4;``#K`!"=Y0`PH.,`4*#C!VV@XV1UD^4$<(?B:(63Y0`&MN@!
M`EGC*E:%,/O__SH`,*#C"$"@XR,RH.&%X9?G`08>XP$R@P,),H,3`5"%X@%`
M5.+W__\:J3:!YP*9B>("J5KB\?__B@4`6.'K__\J_H>]Z`0P@>0!(%+B_/__
=&@[PH.&<-?`!@#/P`;N[N[N(B(B(JJJJJLS,S,PJ
`
end

13
sys/arch/arm32/stand/BtNetBSD/pling.BtNetBSD/PreBoot
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@ -1,13 +0,0 @@
| Start EtherH setup
|
| Fix for the EtherH card. We need to do a *ehtest before booting RiscBSD
| Test to see if the EtherH module is present and if it is
| run *ehtest
|
set ETHERH$PRESENT 1
rmensure EtherH 0.0 set ETHERH$PRESENT 0
if <ETHERH$PRESENT> > 0 then ehtest { > null: }
| End EtherH setup
| Start User options
| End User options

96
sys/arch/arm32/stand/BtNetBSD/pling.BtNetBSD/TestBoot
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@ -1,96 +0,0 @@
REM >testboot
REM $NetBSD: TestBoot,v 1.1 2001/02/19 14:09:03 reinoud Exp $
REM
REM Copyright (c) 1995 Mark Brinicombe
REM All rights reserved
REM
REM Redistribution and use in source and binary forms, with or without
REM modification, are permitted provided that the following conditions
REM are met:
REM 1. Redistributions of source code must retain the above copyright
REM notice, this list of conditions and the following disclaimer.
REM 2. Redistributions in binary form must reproduce the above copyright
REM notice, this list of conditions and the following disclaimer in the
REM documentation and/or other materials provided with the distribution.
REM 3. All advertising materials mentioning features or use of this software
REM must display the following acknowledgement:
REM This product includes software developed by Mark Brinicombe.
REM 4. The name of the company nor the name of the author may be used to
REM endorse or promote products derived from this software without specific
REM prior written permission.
REM
REM THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
REM IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
REM OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
REM IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
REM INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
REM BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
REM OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
REM ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
REM OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
REM THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
REM DAMAGE.
REM
REM NetBSD kernel project
REM
REM testboot
REM
REM Sets the FastBoot flag as required
REM
REM Created : 12/05/95
REM Last updated : 03/09/95
REM
*Set NetBSD$FastBoot 0
REM Test for either ALT keys
IF (INKEY(-3) <> 0) THEN
alt% = TRUE
*Set NetBSD$FastBoot 1
ELSE
alt% = FALSE
ENDIF
REM Get byte 80 from the CMOS RAM. This is a RiscIX byte that we are using.
REM bits are as follows :
REM bit 0 - configure bootNetBSD
REM bit 1 - automatic reboot required.
SYS "OS_Byte", 161, 80 TO ,,value%
REM Has the user configured a NetBSD boot ?
REM If a NetBSD boot has been configured ALT can be used to
REM select a RISC OS boot
IF (value% AND &01) THEN
*Set NetBSD$FastBoot 2
ENDIF
REM Did the kernel request a automatic reboot ?
IF (value% AND &02) THEN
*Set NetBSD$FastBoot 3
REM Clear the automatic reboot flag
SYS "OS_Byte", 162, 80, value% AND &fd
ENDIF
REM If the CMOS bits dictate a reboot then allow ALT to override.
IF (value% AND &03) THEN
IF (alt% = TRUE) THEN
*Set NetBSD$FastBoot 0
ENDIF
ENDIF
REM Test for CTRL key - This does a fastconf and will override a reboot
IF (INKEY(-2) <> 0) THEN
*Set NetBSD$FastBoot 4
ENDIF
ON ERROR END
*If <NetBSD$FastBoot> > 0 then RMLoad <BtNetBSD$Dir>.Banner

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