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Merge forward matt-nb5-mips64 

Adapt to new interrupt/spl framework
This commit is contained in:
matt 2011-02-20 07:55:20 +00:00
parent c9fc40b4be
commit 996804a59b
37 changed files with 640 additions and 883 deletions
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3
sys/arch/ews4800mips/conf/files.ews4800mips
View File

@ -1,4 +1,4 @@
# $NetBSD: files.ews4800mips,v 1.4 2009/08/21 03:53:18 thorpej Exp $
# $NetBSD: files.ews4800mips,v 1.5 2011/02/20 07:55:20 matt Exp $
maxpartitions 16
@ -6,7 +6,6 @@ maxusers 2 8 64
include "arch/ews4800mips/conf/majors.ews4800mips"
file arch/mips/mips/softintr.c
file arch/mips/mips/mips3_clock.c
file arch/ews4800mips/ews4800mips/autoconf.c

7
sys/arch/ews4800mips/ews4800mips/autoconf.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: autoconf.c,v 1.7 2008/04/28 20:23:18 martin Exp $ */
/* $NetBSD: autoconf.c,v 1.8 2011/02/20 07:55:20 matt Exp $ */
/*-
* Copyright (c) 2001, 2004 The NetBSD Foundation, Inc.
@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.7 2008/04/28 20:23:18 martin Exp $");
__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.8 2011/02/20 07:55:20 matt Exp $");
#include "opt_sbd.h"
@ -35,6 +35,7 @@ __KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.7 2008/04/28 20:23:18 martin Exp $");
#include <sys/systm.h>
#include <sys/conf.h>
#include <sys/device.h>
#include <sys/intr.h>
#include <machine/sbdvar.h>
#include <machine/disklabel.h>
@ -50,7 +51,7 @@ cpu_configure(void)
splhigh();
if (config_rootfound("mainbus", NULL) == NULL)
panic("no mainbus found");
_splnone();
spl0();
}
void

27
sys/arch/ews4800mips/ews4800mips/bus_dma.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: bus_dma.c,v 1.10 2009/08/21 03:53:18 thorpej Exp $ */
/* $NetBSD: bus_dma.c,v 1.11 2011/02/20 07:55:20 matt Exp $ */
/*
* Copyright (c) 1998 The NetBSD Foundation, Inc.
@ -31,7 +31,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.10 2009/08/21 03:53:18 thorpej Exp $");
__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.11 2011/02/20 07:55:20 matt Exp $");
/* #define BUS_DMA_DEBUG */
#include <sys/param.h>
@ -502,22 +502,24 @@ _bus_dmamap_sync(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t offset,
mips_dcache_wbinv_range(start, minlen);
break;
case BUS_DMASYNC_PREREAD:
case BUS_DMASYNC_PREREAD: {
const struct mips_cache_info * const mci = &mips_cache_info;
end = start + minlen;
preboundary = start & ~mips_dcache_align_mask;
firstboundary = (start + mips_dcache_align_mask)
& ~mips_dcache_align_mask;
lastboundary = end & ~mips_dcache_align_mask;
preboundary = start & ~mci->mci_dcache_align_mask;
firstboundary = (start + mci->mci_dcache_align_mask)
& ~mci->mci_dcache_align_mask;
lastboundary = end & ~mci->mci_dcache_align_mask;
if (preboundary < start && preboundary < lastboundary)
mips_dcache_wbinv_range(preboundary,
mips_dcache_align);
mci->mci_dcache_align);
if (firstboundary < lastboundary)
mips_dcache_inv_range(firstboundary,
lastboundary - firstboundary);
if (lastboundary < end)
mips_dcache_wbinv_range(lastboundary,
mips_dcache_align);
mci->mci_dcache_align);
break;
}
case BUS_DMASYNC_PREWRITE:
mips_dcache_wb_range(start, minlen);
@ -540,12 +542,11 @@ _bus_dmamem_alloc(bus_dma_tag_t t, bus_size_t size, bus_size_t alignment,
bus_size_t boundary, bus_dma_segment_t *segs, int nsegs, int *rsegs,
int flags)
{
extern paddr_t avail_start, avail_end;
extern paddr_t mips_avail_start, mips_avail_end;
return (_bus_dmamem_alloc_range_common(t, size, alignment, boundary,
segs, nsegs, rsegs, flags,
avail_start /*low*/,
avail_end - PAGE_SIZE /*high*/));
segs, nsegs, rsegs, flags,
mips_avail_start /*low*/, mips_avail_end - PAGE_SIZE /*high*/));
}
/*

16
sys/arch/ews4800mips/ews4800mips/cpu.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpu.c,v 1.3 2008/04/04 16:33:05 tsutsui Exp $ */
/* $NetBSD: cpu.c,v 1.4 2011/02/20 07:55:20 matt Exp $ */
/*
* Copyright (c) 2000 Soren S. Jorvang. All rights reserved.
@ -26,18 +26,19 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.3 2008/04/04 16:33:05 tsutsui Exp $");
__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.4 2011/02/20 07:55:20 matt Exp $");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <sys/cpu.h>
#include <machine/autoconf.h>
#include "ioconf.h"
int cpumatch(device_t, cfdata_t, void *);
void cpuattach(device_t, device_t, void *);
static int cpumatch(device_t, cfdata_t, void *);
static void cpuattach(device_t, device_t, void *);
CFATTACH_DECL_NEW(cpu, 0,
cpumatch, cpuattach, NULL, NULL);
@ -60,8 +61,13 @@ void
cpuattach(device_t parent, device_t self, void *aux)
{
struct cpu_info * const ci = curcpu();
ci->ci_dev = self;
self->dv_private = ci;
aprint_normal(": ");
cpu_attached = 1;
cpu_identify();
cpu_identify(self);
}

26
sys/arch/ews4800mips/ews4800mips/interrupt.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: interrupt.c,v 1.7 2010/12/20 00:25:33 matt Exp $ */
/* $NetBSD: interrupt.c,v 1.8 2011/02/20 07:55:20 matt Exp $ */
/*-
* Copyright (c) 2004 The NetBSD Foundation, Inc.
@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.7 2010/12/20 00:25:33 matt Exp $");
__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.8 2011/02/20 07:55:20 matt Exp $");
#include <sys/param.h>
#include <sys/intr.h>
@ -38,8 +38,7 @@ __KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.7 2010/12/20 00:25:33 matt Exp $");
#include <machine/sbdvar.h>
const uint32_t *ipl_sr_bits;
static void (*platform_intr)(uint32_t, uint32_t, vaddr_t, uint32_t);
static void (*platform_intr)(int, vaddr_t, uint32_t);
void
intr_init(void)
@ -64,22 +63,9 @@ intr_disestablish(void *arg)
}
void
cpu_intr(uint32_t status, uint32_t cause, vaddr_t pc, uint32_t ipending)
cpu_intr(int ppl, vaddr_t pc, uint32_t status)
{
struct cpu_info *ci;
curcpu()->ci_data.cpu_nintr++;
ci = curcpu();
ci->ci_data.cpu_nintr++;
ci->ci_idepth++;
(*platform_intr)(status, cause, pc, ipending);
ci->ci_idepth--;
#ifdef __HAVE_FAST_SOFTINTS
ipending &= (MIPS_SOFT_INT_MASK_1 | MIPS_SOFT_INT_MASK_0);
if (ipending == 0)
return;
_clrsoftintr(ipending);
softintr_dispatch(ipending);
#endif
(*platform_intr)(ppl, pc, status);
}

15
sys/arch/ews4800mips/ews4800mips/machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: machdep.c,v 1.23 2010/05/04 15:32:31 tsutsui Exp $ */
/* $NetBSD: machdep.c,v 1.24 2011/02/20 07:55:20 matt Exp $ */
/*-
* Copyright (c) 2001, 2004, 2005 The NetBSD Foundation, Inc.
@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.23 2010/05/04 15:32:31 tsutsui Exp $");
__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.24 2011/02/20 07:55:20 matt Exp $");
#include "opt_ddb.h"
@ -88,7 +88,7 @@ void
mach_init(int argc, char *argv[], struct bootinfo *bi)
{
extern char kernel_text[], edata[], end[];
vaddr_t v;
void *v;
int i;
/* Clear BSS */
@ -115,7 +115,7 @@ mach_init(int argc, char *argv[], struct bootinfo *bi)
sbd_init();
__asm volatile("move %0, $29" : "=r"(v));
printf("kernel_text=%p edata=%p end=%p sp=%" PRIxVADDR "\n",
printf("kernel_text=%p edata=%p end=%p sp=%p\n",
kernel_text, edata, end, v);
option(argc, argv, bi);
@ -133,7 +133,7 @@ mach_init(int argc, char *argv[], struct bootinfo *bi)
*/
cn_tab = NULL;
mips_vector_init();
mips_vector_init(NULL, false);
memcpy((void *)0x80000200, ews4800mips_nmi_vec, 32); /* NMI */
mips_dcache_wbinv_all();
@ -143,7 +143,7 @@ mach_init(int argc, char *argv[], struct bootinfo *bi)
curcpu()->ci_cycles_per_hz = (curcpu()->ci_cpu_freq + hz / 2) / hz;
curcpu()->ci_divisor_delay =
((curcpu()->ci_cpu_freq + 500000) / 1000000);
if (mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT) {
if (mips_options.mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT) {
curcpu()->ci_cycles_per_hz /= 2;
curcpu()->ci_divisor_delay /= 2;
}
@ -254,8 +254,7 @@ cpu_reboot(int howto, char *bootstr)
static int waittime = -1;
/* Take a snapshot before clobbering any registers. */
if (curlwp)
savectx(curpcb);
savectx(curpcb);
if (cold) {
howto |= RB_HALT;

6
sys/arch/ews4800mips/ews4800mips/mainbus.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: mainbus.c,v 1.4 2008/04/28 20:23:18 martin Exp $ */
/* $NetBSD: mainbus.c,v 1.5 2011/02/20 07:55:20 matt Exp $ */
/*-
* Copyright (c) 2001, 2004, 2005 The NetBSD Foundation, Inc.
@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.4 2008/04/28 20:23:18 martin Exp $");
__KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.5 2011/02/20 07:55:20 matt Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -59,7 +59,7 @@ void
mainbus_attach(device_t parent, device_t self, void *aux)
{
struct mainbus_attach_args ma;
const char **p;
const char * const *p;
mainbus_found = 1;
aprint_normal("\n");

11
sys/arch/ews4800mips/ews4800mips/tr2.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: tr2.c,v 1.4 2010/11/15 06:23:05 uebayasi Exp $ */
/* $NetBSD: tr2.c,v 1.5 2011/02/20 07:55:20 matt Exp $ */
/*-
* Copyright (c) 2004, 2005 The NetBSD Foundation, Inc.
@ -30,8 +30,9 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: tr2.c,v 1.4 2010/11/15 06:23:05 uebayasi Exp $");
__KERNEL_RCSID(0, "$NetBSD: tr2.c,v 1.5 2011/02/20 07:55:20 matt Exp $");
#define __INTR_PRIVATE
#include "fb_sbdio.h"
#include "kbms_sbdio.h"
#include "zsc_sbdio.h"
@ -60,7 +61,7 @@ __KERNEL_RCSID(0, "$NetBSD: tr2.c,v 1.4 2010/11/15 06:23:05 uebayasi Exp $");
SBD_DECL(tr2);
/* EWS4800/350 mainbus device list */
static const char *tr2_mainbusdevs[] =
static const char * const tr2_mainbusdevs[] =
{
"sbdio",
#ifdef notyet
@ -103,7 +104,7 @@ tr2_init(void)
platform.mainbusdevs = tr2_mainbusdevs;
platform.sbdiodevs = tr2_sbdiodevs;
ipl_sr_bits = tr2_sr_bits;
ipl_sr_map = tr2_ipl_sr_map;
kseg2iobufsize = 0x02000000; /* 32MB for VME and framebuffer */
@ -122,7 +123,7 @@ void
tr2_cache_config(void)
{
mips_sdcache_size = 1024 * 1024; /* 1MB L2-cache */
mips_cache_info.mci_sdcache_size = 1024 * 1024; /* 1MB L2-cache */
}
void

213
sys/arch/ews4800mips/ews4800mips/tr2_intr.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: tr2_intr.c,v 1.10 2008/04/28 20:23:18 martin Exp $ */
/* $NetBSD: tr2_intr.c,v 1.11 2011/02/20 07:55:20 matt Exp $ */
/*-
* Copyright (c) 2004, 2005 The NetBSD Foundation, Inc.
@ -30,12 +30,15 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: tr2_intr.c,v 1.10 2008/04/28 20:23:18 martin Exp $");
__KERNEL_RCSID(0, "$NetBSD: tr2_intr.c,v 1.11 2011/02/20 07:55:20 matt Exp $");
#define __INTR_PRIVATE
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/device.h>
#include <sys/evcnt.h>
#include <sys/cpu.h>
#include <sys/lwp.h>
#include <sys/intr.h>
#include <machine/locore.h> /* mips3_cp0* */
@ -47,23 +50,24 @@ __KERNEL_RCSID(0, "$NetBSD: tr2_intr.c,v 1.10 2008/04/28 20:23:18 martin Exp $")
SBD_DECL(tr2);
const uint32_t tr2_sr_bits[_IPL_N] = {
[IPL_NONE] = 0,
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
[IPL_SOFTNET] =
MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1,
[IPL_VM] =
MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 |
MIPS_INT_MASK_0 |
MIPS_INT_MASK_2 |
MIPS_INT_MASK_4,
[IPL_SCHED] =
MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 |
MIPS_INT_MASK_0 |
MIPS_INT_MASK_2 |
MIPS_INT_MASK_4 |
MIPS_INT_MASK_5,
const struct ipl_sr_map tr2_ipl_sr_map = {
{
[IPL_NONE] = 0,
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
[IPL_SOFTNET] = MIPS_SOFT_INT_MASK,
[IPL_VM] = MIPS_SOFT_INT_MASK
| MIPS_INT_MASK_0
| MIPS_INT_MASK_2
| MIPS_INT_MASK_4,
[IPL_SCHED] = MIPS_SOFT_INT_MASK
| MIPS_INT_MASK_0
| MIPS_INT_MASK_2
| MIPS_INT_MASK_4
| MIPS_INT_MASK_5,
[IPL_DDB] = MIPS_INT_MASK,
[IPL_HIGH] = MIPS_INT_MASK,
/* !!! TEST !!! VME INTERRUPT IS NOT MASKED */
},
};
#define NIRQ 8
@ -139,121 +143,116 @@ tr2_intr_disestablish(void *arg)
}
void
tr2_intr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending)
tr2_intr(int ppl, vaddr_t pc, uint32_t status)
{
struct tr2_intr_handler *ih;
struct clockframe cf;
uint32_t r, handled;
uint32_t r, ipending;
int ipl;
handled = 0;
while (ppl < (ipl = splintr(&ipending))) {
if (ipending & MIPS_INT_MASK_5) { /* CLOCK */
cf.pc = pc;
cf.sr = status;
cf.intr = (curcpu()->ci_idepth > 0);
if (ipending & MIPS_INT_MASK_5) { /* CLOCK */
cf.pc = pc;
cf.sr = status;
*PICNIC_INT5_STATUS_REG = 0;
r = *PICNIC_INT5_STATUS_REG;
*PICNIC_INT5_STATUS_REG = 0;
r = *PICNIC_INT5_STATUS_REG;
hardclock(&cf);
timer_tr2_ev.ev_count++;
handled |= MIPS_INT_MASK_5;
}
_splset((status & handled) | MIPS_SR_INT_IE);
if (ipending & MIPS_INT_MASK_4) { /* KBD, MOUSE, SERIAL */
r = *PICNIC_INT4_STATUS_REG;
if (r & PICNIC_INT_KBMS) {
ih = &tr2_intr_handler[0];
if (ih->func) {
ih->func(ih->arg);
ih->evcnt.ev_count++;
}
r &= ~PICNIC_INT_KBMS;
hardclock(&cf);
timer_tr2_ev.ev_count++;
}
if (r & PICNIC_INT_SERIAL) {
if (ipending & MIPS_INT_MASK_4) { /* KBD, MOUSE, SERIAL */
r = *PICNIC_INT4_STATUS_REG;
if (r & PICNIC_INT_KBMS) {
ih = &tr2_intr_handler[0];
if (ih->func) {
ih->func(ih->arg);
ih->evcnt.ev_count++;
}
r &= ~PICNIC_INT_KBMS;
}
if (r & PICNIC_INT_SERIAL) {
#if 0
printf("SIO interrupt\n");
printf("SIO interrupt\n");
#endif
ih = &tr2_intr_handler[2];
if (ih->func) {
ih->func(ih->arg);
ih->evcnt.ev_count++;
ih = &tr2_intr_handler[2];
if (ih->func) {
ih->func(ih->arg);
ih->evcnt.ev_count++;
}
r &= ~PICNIC_INT_SERIAL;
}
r &= ~PICNIC_INT_SERIAL;
}
handled |= MIPS_INT_MASK_4;
}
_splset((status & handled) | MIPS_SR_INT_IE);
if (ipending & MIPS_INT_MASK_3) { /* VME */
printf("VME interrupt\n");
if (ipending & MIPS_INT_MASK_3) { /* VME */
printf("VME interrupt\n");
r = *(volatile uint32_t *)0xbfb00018; /* NABI? */
if ((r & 0x10) != 0) {
/* vme high interrupt */
} else if ((r & 0x4) != 0) {
/* vme lo interrupt */
} else {
/* error */
}
}
if (ipending & MIPS_INT_MASK_2) { /* ETHER, SCSI */
r = *PICNIC_INT2_STATUS_REG;
if (r & PICNIC_INT_ETHER) {
ih = &tr2_intr_handler[6];
if (ih->func) {
ih->func(ih->arg);
ih->evcnt.ev_count++;
r = *(volatile uint32_t *)0xbfb00018; /* NABI? */
if ((r & 0x10) != 0) {
/* vme high interrupt */
} else if ((r & 0x4) != 0) {
/* vme lo interrupt */
} else {
/* error */
}
r &= ~PICNIC_INT_ETHER;
}
if (r & PICNIC_INT_SCSI) {
ih = &tr2_intr_handler[5];
if (ih->func) {
ih->func(ih->arg);
ih->evcnt.ev_count++;
if (ipending & MIPS_INT_MASK_2) { /* ETHER, SCSI */
r = *PICNIC_INT2_STATUS_REG;
if (r & PICNIC_INT_ETHER) {
ih = &tr2_intr_handler[6];
if (ih->func) {
ih->func(ih->arg);
ih->evcnt.ev_count++;
}
r &= ~PICNIC_INT_ETHER;
}
r &= ~PICNIC_INT_SCSI;
}
if ((r & PICNIC_INT_FDDLPT) &&
((cause & status) & MIPS_INT_MASK_5)) {
if (r & PICNIC_INT_SCSI) {
ih = &tr2_intr_handler[5];
if (ih->func) {
ih->func(ih->arg);
ih->evcnt.ev_count++;
}
r &= ~PICNIC_INT_SCSI;
}
if ((r & PICNIC_INT_FDDLPT) &&
(ipending & MIPS_INT_MASK_5)) {
#ifdef DEBUG
printf("FDD LPT interrupt\n");
printf("FDD LPT interrupt\n");
#endif
ih = &tr2_intr_handler[7];
if (ih->func) {
ih->func(ih->arg);
ih->evcnt.ev_count++;
ih = &tr2_intr_handler[7];
if (ih->func) {
ih->func(ih->arg);
ih->evcnt.ev_count++;
}
r &= ~PICNIC_INT_FDDLPT;
}
r &= ~PICNIC_INT_FDDLPT;
}
handled |= MIPS_INT_MASK_2;
}
_splset((status & handled) | MIPS_SR_INT_IE);
if (ipending & MIPS_INT_MASK_1)
panic("unknown interrupt INT1\n");
if (ipending & MIPS_INT_MASK_1)
panic("unknown interrupt INT1\n");
if (ipending & MIPS_INT_MASK_0) { /* FDD, PRINTER */
printf("printer, printer interrupt\n");
r = *PICNIC_INT0_STATUS_REG;
if (r & PICNIC_INT_FDDLPT) {
printf("FDD, Printer interrupt.\n");
} else {
printf("unknown interrupt INT0\n");
if (ipending & MIPS_INT_MASK_0) { /* FDD, PRINTER */
#ifdef DEBUG
printf("printer, printer interrupt\n");
#endif
r = *PICNIC_INT0_STATUS_REG;
if (r & PICNIC_INT_FDDLPT) {
#ifdef DEBUG
printf("FDD, Printer interrupt.\n");
#endif
} else {
printf("unknown interrupt INT0\n");
}
}
handled |= MIPS_INT_MASK_0;
}
cause &= ~handled;
_splset(((status & ~cause) & MIPS_HARD_INT_MASK) | MIPS_SR_INT_IE);
}
void

11
sys/arch/ews4800mips/ews4800mips/tr2a.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: tr2a.c,v 1.4 2010/11/15 06:23:05 uebayasi Exp $ */
/* $NetBSD: tr2a.c,v 1.5 2011/02/20 07:55:20 matt Exp $ */
/*-
* Copyright (c) 2004, 2005 The NetBSD Foundation, Inc.
@ -30,8 +30,9 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: tr2a.c,v 1.4 2010/11/15 06:23:05 uebayasi Exp $");
__KERNEL_RCSID(0, "$NetBSD: tr2a.c,v 1.5 2011/02/20 07:55:20 matt Exp $");
#define __INTR_PRIVATE
#include "fb_sbdio.h"
#include "kbms_sbdio.h"
#include "zsc_sbdio.h"
@ -60,7 +61,7 @@ __KERNEL_RCSID(0, "$NetBSD: tr2a.c,v 1.4 2010/11/15 06:23:05 uebayasi Exp $");
SBD_DECL(tr2a);
/* EWS4800/360 bus list */
static const char *tr2a_mainbusdevs[] = {
static const char * const tr2a_mainbusdevs[] = {
"sbdio",
#ifdef notyet
"apbus",
@ -152,7 +153,7 @@ tr2a_init(void)
if (have_fb_sbdio)
platform.sbdiodevs = tr2a_sbdiodevs;
ipl_sr_bits = tr2a_sr_bits;
ipl_sr_map = tr2a_ipl_sr_map;
kseg2iobufsize = 0x02000000; /* 32MB for APbus and framebuffer */
@ -171,7 +172,7 @@ void
tr2a_cache_config(void)
{
mips_sdcache_size = 1024 * 1024; /* 1MB L2-cache */
mips_cache_info.mci_sdcache_size = 1024 * 1024; /* 1MB L2-cache */
}
void

254
sys/arch/ews4800mips/ews4800mips/tr2a_intr.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: tr2a_intr.c,v 1.12 2008/04/28 20:23:18 martin Exp $ */
/* $NetBSD: tr2a_intr.c,v 1.13 2011/02/20 07:55:20 matt Exp $ */
/*-
* Copyright (c) 2004, 2005 The NetBSD Foundation, Inc.
@ -30,12 +30,15 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: tr2a_intr.c,v 1.12 2008/04/28 20:23:18 martin Exp $");
__KERNEL_RCSID(0, "$NetBSD: tr2a_intr.c,v 1.13 2011/02/20 07:55:20 matt Exp $");
#define __INTR_PRIVATE
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/evcnt.h>
#include <sys/lwp.h>
#include <sys/cpu.h>
#include <sys/intr.h>
#include <machine/locore.h> /* mips3_cp0* */
@ -45,27 +48,16 @@ __KERNEL_RCSID(0, "$NetBSD: tr2a_intr.c,v 1.12 2008/04/28 20:23:18 martin Exp $"
SBD_DECL(tr2a);
const uint32_t tr2a_sr_bits[_IPL_N] = {
const struct ipl_sr_map tr2a_ipl_sr_map = {
.sr_bits = {
[IPL_NONE] = 0,
[IPL_SOFTCLOCK] =
MIPS_SOFT_INT_MASK_0,
[IPL_SOFTNET] =
MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1,
[IPL_VM] =
MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 |
MIPS_INT_MASK_0 |
MIPS_INT_MASK_1 |
MIPS_INT_MASK_2 |
MIPS_INT_MASK_3 |
MIPS_INT_MASK_4,
[IPL_SCHED] =
MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 |
MIPS_INT_MASK_0 |
MIPS_INT_MASK_1 |
MIPS_INT_MASK_2 |
MIPS_INT_MASK_3 |
MIPS_INT_MASK_4 |
MIPS_INT_MASK_5,
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
[IPL_SOFTNET] = MIPS_SOFT_INT_MASK,
[IPL_VM] = MIPS_INT_MASK & ~MIPS_INT_MASK_5,
[IPL_SCHED] = MIPS_INT_MASK,
[IPL_DDB] = MIPS_INT_MASK,
[IPL_HIGH] = MIPS_INT_MASK,
},
};
#define NIRQ 16
@ -178,134 +170,124 @@ tr2a_intr_disestablish(void *arg)
}
void
tr2a_intr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending)
tr2a_intr(int ppl, vaddr_t pc, uint32_t status)
{
struct tr2a_intr_handler *ih;
struct clockframe cf;
uint32_t r, intc_cause, handled;
uint32_t r, intc_cause, ipending;
int ipl;
handled = 0;
intc_cause = *INTC_STATUS_REG & *INTC_MASK_REG;
if ((ipending & MIPS_INT_MASK_5) && (intc_cause & INTC_INT5)) {
cf.pc = pc;
cf.sr = status;
tr2a_wbflush();
*INTC_CLEAR_REG = 0x7c;
*INTC_STATUS_REG;
while (ppl < (ipl = splintr(&ipending))) {
if ((ipending & MIPS_INT_MASK_5) && (intc_cause & INTC_INT5)) {
cf.pc = pc;
cf.sr = status;
cf.intr = (curcpu()->ci_idepth > 0);
tr2a_wbflush();
*INTC_CLEAR_REG = 0x7c;
*INTC_STATUS_REG;
hardclock(&cf);
timer_tr2a_ev.ev_count++;
handled |= MIPS_INT_MASK_5;
}
_splset((status & handled) | MIPS_SR_INT_IE);
if ((ipending & MIPS_INT_MASK_4) && (intc_cause & INTC_INT4)) {
/* KBD, MOUSE, SERIAL */
r = *ASO_INT_STATUS_REG;
if (r & 0x300010) {
ih = &tr2a_intr_handler[4];
if (ih->func) {
ih->func(ih->arg);
ih->evcnt.ev_count++;
}
} else if (r & 0x40) {
/* kbms */
ih = &tr2a_intr_handler[9];
if (ih->func) {
ih->func(ih->arg);
ih->evcnt.ev_count++;
}
} else if (r & 0x20) {
printf("INT4 (1)\n");
} else if (r & 0x00800000) {
printf("INT4 (2)\n");
} else if (r & 0x00400000) {
printf("INT4 (3)\n");
} else if (r != 0) {
printf("not for INT4 %x\n", r);
hardclock(&cf);
timer_tr2a_ev.ev_count++;
}
tr2a_wbflush();
*INTC_CLEAR_REG = 0x68;
*INTC_STATUS_REG;
handled |= MIPS_INT_MASK_4;
}
_splset((status & handled) | MIPS_SR_INT_IE);
if ((ipending & MIPS_INT_MASK_3) && (intc_cause & INTC_INT3)) {
/* APbus HI */
printf("APbus HI\n");
tr2a_wbflush();
*INTC_CLEAR_REG = 0x54;
*INTC_STATUS_REG;
handled |= MIPS_INT_MASK_3;
}
if ((ipending & MIPS_INT_MASK_2) && (intc_cause & INTC_INT2)) {
/* SCSI, ETHER */
r = *ASO_INT_STATUS_REG;
if (r & 0x100) { /* SCSI-A */
ih = &tr2a_intr_handler[6];
if (ih->func) {
ih->func(ih->arg);
ih->evcnt.ev_count++;
if ((ipending & MIPS_INT_MASK_4) && (intc_cause & INTC_INT4)) {
/* KBD, MOUSE, SERIAL */
r = *ASO_INT_STATUS_REG;
if (r & 0x300010) {
ih = &tr2a_intr_handler[4];
if (ih->func) {
ih->func(ih->arg);
ih->evcnt.ev_count++;
}
} else if (r & 0x40) {
/* kbms */
ih = &tr2a_intr_handler[9];
if (ih->func) {
ih->func(ih->arg);
ih->evcnt.ev_count++;
}
} else if (r & 0x20) {
printf("INT4 (1)\n");
} else if (r & 0x00800000) {
printf("INT4 (2)\n");
} else if (r & 0x00400000) {
printf("INT4 (3)\n");
} else if (r != 0) {
printf("not for INT4 %x\n", r);
}
} else if (r & 0x200) { /* SCSI-B */
ih = &tr2a_intr_handler[10];
if (ih->func) {
ih->func(ih->arg);
ih->evcnt.ev_count++;
}
} else if (r & 0x1) { /* LANCE */
ih = &tr2a_intr_handler[0];
if (ih->func) {
ih->func(ih->arg);
ih->evcnt.ev_count++;
}
} else if (r != 0) {
printf("not for INT2 %x %x\n", r,
*ASO_DMAINT_STATUS_REG);
tr2a_wbflush();
*INTC_CLEAR_REG = 0x68;
*INTC_STATUS_REG;
}
tr2a_wbflush();
*INTC_CLEAR_REG = 0x40;
*INTC_STATUS_REG;
handled |= MIPS_INT_MASK_2;
}
_splset((status & handled) | MIPS_SR_INT_IE);
if ((ipending & MIPS_INT_MASK_1) && (intc_cause & INTC_INT1)) {
/* APbus LO */
printf("APbus LO\n");
tr2a_wbflush();
*INTC_CLEAR_REG = 0x2c;
*INTC_STATUS_REG;
handled |= MIPS_INT_MASK_1;
}
if ((ipending & MIPS_INT_MASK_0) && (intc_cause & INTC_INT0)) {
/* NMI etc. */
r = *ASO_INT_STATUS_REG;
printf("INT0 %08x\n", r);
if (r & 0x8000) {
printf("INT0(1) NMI\n");
} else if (r & 0x8) {
printf("INT0(2)\n");
} else if (r & 0x4) {
printf("INT0(3)\n");
} else if (r != 0) {
printf("not for INT0 %x\n", r);
if ((ipending & MIPS_INT_MASK_3) && (intc_cause & INTC_INT3)) {
/* APbus HI */
printf("APbus HI\n");
tr2a_wbflush();
*INTC_CLEAR_REG = 0x54;
*INTC_STATUS_REG;
}
if ((ipending & MIPS_INT_MASK_2) && (intc_cause & INTC_INT2)) {
/* SCSI, ETHER */
r = *ASO_INT_STATUS_REG;
if (r & 0x100) { /* SCSI-A */
ih = &tr2a_intr_handler[6];
if (ih->func) {
ih->func(ih->arg);
ih->evcnt.ev_count++;
}
} else if (r & 0x200) { /* SCSI-B */
ih = &tr2a_intr_handler[10];
if (ih->func) {
ih->func(ih->arg);
ih->evcnt.ev_count++;
}
} else if (r & 0x1) { /* LANCE */
ih = &tr2a_intr_handler[0];
if (ih->func) {
ih->func(ih->arg);
ih->evcnt.ev_count++;
}
} else if (r != 0) {
printf("not for INT2 %x %x\n", r,
*ASO_DMAINT_STATUS_REG);
}
tr2a_wbflush();
*INTC_CLEAR_REG = 0x40;
*INTC_STATUS_REG;
}
if ((ipending & MIPS_INT_MASK_1) && (intc_cause & INTC_INT1)) {
/* APbus LO */
printf("APbus LO\n");
tr2a_wbflush();
*INTC_CLEAR_REG = 0x2c;
*INTC_STATUS_REG;
}
if ((ipending & MIPS_INT_MASK_0) && (intc_cause & INTC_INT0)) {
/* NMI etc. */
r = *ASO_INT_STATUS_REG;
printf("INT0 %08x\n", r);
if (r & 0x8000) {
printf("INT0(1) NMI\n");
} else if (r & 0x8) {
printf("INT0(2)\n");
} else if (r & 0x4) {
printf("INT0(3)\n");
} else if (r != 0) {
printf("not for INT0 %x\n", r);
}
tr2a_wbflush();
*INTC_CLEAR_REG = 0x14;
*INTC_STATUS_REG;
}
tr2a_wbflush();
*INTC_CLEAR_REG = 0x14;
*INTC_STATUS_REG;
handled |= MIPS_INT_MASK_0;
}
cause &= ~handled;
_splset(((status & ~cause) & MIPS_HARD_INT_MASK) | MIPS_SR_INT_IE);
}
void

61
sys/arch/ews4800mips/include/intr.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: intr.h,v 1.10 2008/04/28 20:23:18 martin Exp $ */
/* $NetBSD: intr.h,v 1.11 2011/02/20 07:55:21 matt Exp $ */
/*-
* Copyright (c) 2000, 2001, 2004 The NetBSD Foundation, Inc.
@ -32,59 +32,18 @@
#ifndef _EWS4800MIPS_INTR_H_
#define _EWS4800MIPS_INTR_H_
#define IPL_NONE 0 /* disable only this interrupt */
#define IPL_SOFTCLOCK 1 /* clock software interrupts (SI 0) */
#define IPL_SOFTBIO 1 /* bio software interrupts (SI 0) */
#define IPL_SOFTNET 2 /* network software interrupts (SI 1) */
#define IPL_SOFTSERIAL 2 /* serial software interrupts (SI 1) */
#define IPL_VM 3
#define IPL_SCHED 4 /* disable clock interrupts */
#define IPL_HIGH 4 /* disable all interrupts */
#define _IPL_N 5
#define _IPL_SI0_FIRST IPL_SOFTCLOCK
#define _IPL_SI0_LAST IPL_SOFTBIO
#define _IPL_SI1_FIRST IPL_SOFTNET
#define _IPL_SI1_LAST IPL_SOFTSERIAL
#define IST_UNUSABLE -1 /* interrupt cannot be used */
#define IST_NONE 0 /* none (dummy) */
#define IST_PULSE 1 /* pulsed */
#define IST_EDGE 2 /* edge-triggered */
#define IST_LEVEL 3 /* level-triggered */
#include <mips/locore.h>
extern const uint32_t *ipl_sr_bits;
#define spl0() (void) _spllower(0)
#define splx(s) (void) _splset(s)
typedef int ipl_t;
typedef struct {
ipl_t _sr;
} ipl_cookie_t;
static inline ipl_cookie_t
makeiplcookie(ipl_t ipl)
{
return (ipl_cookie_t){._sr = ipl_sr_bits[ipl]};
}
static inline int
splraiseipl(ipl_cookie_t icookie)
{
return _splraise(icookie._sr);
}
#include <sys/spl.h>
#include <mips/intr.h>
#ifdef _KERNEL
void intr_init(void);
void intr_establish(int, int (*)(void *), void *);
void intr_disestablish(void *);
#ifdef __INTR_PRIVATE
extern const struct ipl_sr_map tr2_ipl_sr_map;
extern const struct ipl_sr_map tr2a_ipl_sr_map;
#endif
#endif
#endif /* !_EWS4800MIPS_INTR_H_ */

9
sys/arch/ews4800mips/include/sbdvar.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: sbdvar.h,v 1.5 2009/12/14 00:46:03 matt Exp $ */
/* $NetBSD: sbdvar.h,v 1.6 2011/02/20 07:55:21 matt Exp $ */
/*-
* Copyright (c) 2004, 2005 The NetBSD Foundation, Inc.
@ -47,7 +47,7 @@ struct sbd {
int cpu_clock;
/* mainbus node table */
const char **mainbusdevs;
const char * const *mainbusdevs;
/* System Board I/O device table */
const struct sbdiodevdesc *sbdiodevs;
@ -68,7 +68,7 @@ struct sbd {
void (*intr_init)(void);
void *(*intr_establish)(int, int (*)(void *), void *);
void (*intr_disestablish)(void *);
void (*intr)(uint32_t, uint32_t, vaddr_t, uint32_t);
void (*intr)(int, vaddr_t, uint32_t);
/* Interval timer helper routines */
void (*initclocks)(void);
@ -88,14 +88,13 @@ void x ## _mem_init(void *, void *); \
void x ## _intr_init(void); \
void *x ## _intr_establish(int, int (*)(void *), void *); \
void x ## _intr_disestablish(void *); \
void x ## _intr(uint32_t, uint32_t, vaddr_t, uint32_t); \
void x ## _intr(int, vaddr_t, uint32_t); \
void x ## _initclocks(void); \
void x ## _consinit(void); \
int x ## _ipl_bootdev(void); \
void x ## _reboot(void); \
void x ## _poweroff(void); \
void x ## _ether_addr(uint8_t *); \
extern const uint32_t x ## _sr_bits[]
#define _SBD_OPS_SET(m, x) platform . x = m ## _ ## x

81
sys/arch/mipsco/include/intr.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: intr.h,v 1.18 2009/04/13 09:37:50 he Exp $ */
/* $NetBSD: intr.h,v 1.19 2011/02/20 07:56:16 matt Exp $ */
/*
* Copyright (c) 1998 Jonathan Stone. All rights reserved.
@ -33,42 +33,12 @@
#ifndef _MACHINE_INTR_H_
#define _MACHINE_INTR_H_
#define IPL_NONE 0 /* disable only this interrupt */
#define IPL_SOFTCLOCK 1 /* generic software interrupts */
#define IPL_SOFTBIO 1 /* clock software interrupts */
#define IPL_SOFTNET 2 /* network software interrupts */
#define IPL_SOFTSERIAL 2 /* serial software interrupts */
#define IPL_VM 3
#define IPL_SCHED 4
#define IPL_HIGH 4 /* disable all interrupts */
#define IPL_N 5
/* Interrupt sharing types. */
#define IST_NONE 0 /* none */
#define IST_PULSE 1 /* pulsed */
#define IST_EDGE 2 /* edge-triggered */
#define IST_LEVEL 3 /* level-triggered */
#include <mips/intr.h>
#ifdef _KERNEL
#ifndef _LOCORE
#include <sys/types.h>
#ifdef __INTR_PRIVATE
#include <sys/evcnt.h>
#include <sys/queue.h>
#include <mips/locore.h>
/*
* software simulated interrupt
*/
#define setsoft(x) do { \
extern u_int ssir; \
int _s; \
\
_s = splhigh(); \
ssir |= 1 << (x); \
_setsoftintr(MIPS_SOFT_INT_MASK_1); \
splx(_s); \
} while (0)
#include <mips/cpuregs.h>
/*
* nesting interrupt masks.
@ -82,34 +52,8 @@
#define MIPS_INT_MASK_SPL4 (MIPS_INT_MASK_4|MIPS_INT_MASK_SPL3)
#define MIPS_INT_MASK_SPL5 (MIPS_INT_MASK_5|MIPS_INT_MASK_SPL4)
#define spl0() (void)_spllower(0)
#define splx(s) (void)_splset(s)
#define splvm() _splraise(MIPS_INT_MASK_SPL2)
#define splsched() _splraise(MIPS_INT_MASK_SPL2)
#define splhigh() _splraise(MIPS_INT_MASK_SPL2)
#define splsoftclock() _splraise(MIPS_INT_MASK_SPL_SOFT0)
#define splsoftbio() _splraise(MIPS_INT_MASK_SPL_SOFT0)
#define splsoftnet() _splraise(MIPS_INT_MASK_SPL_SOFT1)
#define splsoftserial() _splraise(MIPS_INT_MASK_SPL_SOFT1)
typedef int ipl_t;
typedef struct {
int _sr;
} ipl_cookie_t;
ipl_cookie_t makeiplcookie(ipl_t ipl);
static inline int
splraiseipl(ipl_cookie_t icookie)
{
return _splraise(icookie._sr);
}
struct mipsco_intrhand {
LIST_ENTRY(mipsco_intrhand)
ih_q;
LIST_ENTRY(mipsco_intrhand) ih_q;
int (*ih_fun)(void *);
void *ih_arg;
struct mipsco_intr *ih_intrhead;
@ -117,14 +61,18 @@ struct mipsco_intrhand {
};
struct mipsco_intr {
LIST_HEAD(,mipsco_intrhand)
intr_q;
LIST_HEAD(,mipsco_intrhand) intr_q;
struct evcnt ih_evcnt;
unsigned long intr_siq;
};
extern const struct ipl_sr_map mipsco_ipl_sr_map;
extern struct mipsco_intrhand intrtab[];
#define CALL_INTR(lev) ((*intrtab[lev].ih_fun)(intrtab[lev].ih_arg))
#define MAX_INTR_COOKIES 16
#endif /* __INTR_PRIVATE */
#define SYS_INTR_LEVEL0 0
#define SYS_INTR_LEVEL1 1
@ -139,10 +87,5 @@ extern struct mipsco_intrhand intrtab[];
#define SYS_INTR_FDC 10
#define SYS_INTR_ATBUS 11
#define MAX_INTR_COOKIES 16
#define CALL_INTR(lev) ((*intrtab[lev].ih_fun)(intrtab[lev].ih_arg))
#endif /* !_LOCORE */
#endif /* _KERNEL */
#endif /* _MACHINE_INTR_H_ */

4
sys/arch/mipsco/include/sysconf.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: sysconf.h,v 1.5 2009/03/14 14:46:02 dsl Exp $ */
/* $NetBSD: sysconf.h,v 1.6 2011/02/20 07:56:16 matt Exp $ */
/*
* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
@ -54,7 +54,7 @@ struct platform {
* clkinit - Initialize clocks
*/
void (*cons_init)(void);
void (*iointr)(unsigned, unsigned, unsigned, unsigned);
void (*iointr)(uint32_t, vaddr_t, uint32_t);
int (*memsize)(void *);
void (*intr_establish)(int, int (*)(void *), void *);
void (*clkinit)(void);

5
sys/arch/mipsco/mipsco/autoconf.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: autoconf.c,v 1.23 2011/02/08 20:20:19 rmind Exp $ */
/* $NetBSD: autoconf.c,v 1.24 2011/02/20 07:56:16 matt Exp $ */
/*
* Copyright (c) 1988 University of Utah.
@ -46,8 +46,9 @@
* and the drivers are initialized.
*/
#define __INTR_PRIVATE
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.23 2011/02/08 20:20:19 rmind Exp $");
__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.24 2011/02/20 07:56:16 matt Exp $");
#include <sys/param.h>
#include <sys/systm.h>

10
sys/arch/mipsco/mipsco/bus_dma.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: bus_dma.c,v 1.25 2009/08/21 04:00:57 thorpej Exp $ */
/* $NetBSD: bus_dma.c,v 1.26 2011/02/20 07:56:16 matt Exp $ */
/*-
* Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
@ -31,7 +31,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.25 2009/08/21 04:00:57 thorpej Exp $");
__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.26 2011/02/20 07:56:16 matt Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -54,8 +54,6 @@ static int _bus_dmamap_load_buffer(bus_dma_tag_t, bus_dmamap_t,
void *, bus_size_t, struct vmspace *, int, paddr_t *,
int *, int);
extern paddr_t avail_start, avail_end; /* from pmap.c */
void
_bus_dma_tag_init(bus_dma_tag_t t)
{
@ -447,7 +445,7 @@ _bus_dmamap_sync(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t offset, bus_size_
* NOTE: Even though this is `wbinv_all', since the cache is
* write-through, it just invalidates it.
*/
if (len >= mips_pdcache_size) {
if (len >= mips_cache_info.mci_pdcache_size) {
mips_dcache_wbinv_all();
return;
}
@ -493,7 +491,7 @@ _bus_dmamem_alloc(bus_dma_tag_t t, bus_size_t size, bus_size_t alignment, bus_si
{
return (_bus_dmamem_alloc_range(t, size, alignment, boundary,
segs, nsegs, rsegs, flags, avail_start, trunc_page(avail_end)));
segs, nsegs, rsegs, flags, mips_avail_start, trunc_page(mips_avail_end)));
}
/*

26
sys/arch/mipsco/mipsco/cpu.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpu.c,v 1.9 2009/03/14 15:36:10 dsl Exp $ */
/* $NetBSD: cpu.c,v 1.10 2011/02/20 07:56:16 matt Exp $ */
/*
* Copyright (c) 1994, 1995 Carnegie-Mellon University.
@ -28,30 +28,28 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.9 2009/03/14 15:36:10 dsl Exp $");
__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.10 2011/02/20 07:56:16 matt Exp $");
#include <sys/param.h>
#include <sys/device.h>
#include <sys/cpu.h>
#include <sys/systm.h>
#include <machine/cpu.h>
#include <machine/autoconf.h>
#include <mips/locore.h>
/* Definition of the driver for autoconfig. */
static int cpumatch(struct device *, struct cfdata *, void *);
static void cpuattach(struct device *, struct device *, void *);
static int cpumatch(device_t, cfdata_t, void *);
static void cpuattach(device_t, device_t, void *);
CFATTACH_DECL(cpu, sizeof(struct device),
CFATTACH_DECL(cpu, 0,
cpumatch, cpuattach, NULL, NULL);
extern struct cfdriver cpu_cd;
extern void cpu_identify(void);
static int
cpumatch(struct device *parent, struct cfdata *cfdata, void *aux)
cpumatch(device_t parent, cfdata_t cfdata, void *aux)
{
struct confargs *ca = aux;
@ -63,9 +61,13 @@ cpumatch(struct device *parent, struct cfdata *cfdata, void *aux)
}
static void
cpuattach(struct device *parent, struct device *dev, void *aux)
cpuattach(device_t parent, device_t self, void *aux)
{
struct cpu_info * const ci = curcpu();
printf(": ");
cpu_identify();
ci->ci_dev = self;
self->dv_private = ci;
aprint_normal(": ");
cpu_identify(self);
}

42
sys/arch/mipsco/mipsco/interrupt.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: interrupt.c,v 1.10 2010/12/20 00:25:38 matt Exp $ */
/* $NetBSD: interrupt.c,v 1.11 2011/02/20 07:56:16 matt Exp $ */
/*
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@ -29,50 +29,40 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#define __INTR_PRIVATE
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.10 2010/12/20 00:25:38 matt Exp $");
__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.11 2011/02/20 07:56:16 matt Exp $");
#include <sys/param.h>
#include <sys/malloc.h>
#include <sys/intr.h>
#include <sys/lwp.h>
#include <sys/cpu.h>
#include <machine/sysconf.h>
void
cpu_intr(uint32_t status, uint32_t cause, vaddr_t pc, uint32_t ipending)
cpu_intr(int ppl, vaddr_t pc, uint32_t status)
{
struct cpu_info *ci;
uint32_t ipending;
int ipl;
ci = curcpu();
ci->ci_data.cpu_nintr++;
curcpu()->ci_data.cpu_nintr++;
/* device interrupts */
ci->ci_idepth++;
(*platform.iointr)(status, cause, pc, ipending);
ci->ci_idepth--;
#ifdef __HAVE_FAST_SOFTINTS
/* software simulated interrupt */
if ((ipending & MIPS_SOFT_INT_MASK_1)
|| (ssir && (status & MIPS_SOFT_INT_MASK_1))) {
_clrsoftintr(MIPS_SOFT_INT_MASK_1);
softintr_dispatch();
while (ppl < (ipl = splintr(&ipending))) {
/* device interrupts */
(*platform.iointr)(status, pc, ipending);
}
#endif
}
static const int ipl_sr_bits[] = {
const struct ipl_sr_map mipsco_ipl_sr_map = {
.sr_bits = {
[IPL_NONE] = 0,
[IPL_SOFTCLOCK] = MIPS_INT_MASK_SPL_SOFT0,
[IPL_SOFTNET] = MIPS_INT_MASK_SPL_SOFT1,
[IPL_VM] = MIPS_INT_MASK_SPL2,
[IPL_SCHED] = MIPS_INT_MASK_SPL2,
[IPL_HIGH] = MIPS_INT_MASK,
},
};
ipl_cookie_t
makeiplcookie(ipl_t ipl)
{
return (ipl_cookie_t){._sr = ipl_sr_bits[ipl]};
}

41
sys/arch/mipsco/mipsco/machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: machdep.c,v 1.73 2011/02/08 20:20:19 rmind Exp $ */
/* $NetBSD: machdep.c,v 1.74 2011/02/20 07:56:16 matt Exp $ */
/*
* Copyright (c) 1988 University of Utah.
@ -39,7 +39,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.73 2011/02/08 20:20:19 rmind Exp $");
__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.74 2011/02/20 07:56:16 matt Exp $");
/* from: Utah Hdr: machdep.c 1.63 91/04/24 */
@ -112,8 +112,8 @@ char *bootinfo = NULL; /* pointer to bootinfo structure */
phys_ram_seg_t mem_clusters[VM_PHYSSEG_MAX];
int mem_cluster_cnt;
void to_monitor(int) __attribute__((__noreturn__));
void prom_halt(int) __attribute__((__noreturn__));
void to_monitor(int) __dead;
void prom_halt(int) __dead;
#ifdef KGDB
void zs_kgdb_init(void);
@ -134,22 +134,13 @@ int memsize_scan(void *);
extern void stacktrace(void); /*XXX*/
#endif
/*
* safepri is a safe priority for sleep to set for a spin-wait
* during autoconfiguration or after a panic. Used as an argument to splx().
* XXX disables interrupt 5 to disable mips3 on-chip clock, which also
* disables mips1 FPU interrupts.
*/
int safepri = MIPS3_PSL_LOWIPL; /* XXX */
/* locore callback-vector setup */
extern void mips_vector_init(void);
extern void prom_init(void);
extern void pizazz_init(void);
/* platform-specific initialization vector */
static void unimpl_cons_init(void);
static void unimpl_iointr(unsigned, unsigned, unsigned, unsigned);
static void unimpl_iointr(uint32_t, vaddr_t, uint32_t);
static int unimpl_memsize(void *);
static void unimpl_intr_establish(int, int (*)(void *), void *);
@ -202,7 +193,6 @@ mach_init(int argc, char *argv[], char *envp[], u_int bim, char *bip)
struct btinfo_symtab *bi_syms;
#endif
/* Check for valid bootinfo passed from bootstrap */
if (bim == BOOTINFO_MAGIC) {
struct btinfo_magic *bi_magic;
@ -220,7 +210,14 @@ mach_init(int argc, char *argv[], char *envp[], u_int bim, char *bip)
kernend = (void *)mips_round_page(end);
memset(edata, 0, end - edata);
#if NKSYMS || defined(DDB) || defined(MODULAR)
/*
* Copy exception-dispatch code down to exception vector.
* Initialize locore-function vector.
* Clear out the I and D caches.
*/
mips_vector_init(NULL, false);
#if NKSYMS || defined(DDB) || defined(LKM)
bi_syms = lookup_bootinfo(BTINFO_SYMTAB);
/* Load sysmbol table if present */
@ -254,13 +251,6 @@ mach_init(int argc, char *argv[], char *envp[], u_int bim, char *bip)
mem_clusters[0].size = ctob(physmem);
mem_cluster_cnt = 1;
/*
* Copy exception-dispatch code down to exception vector.
* Initialize locore-function vector.
* Clear out the I and D caches.
*/
mips_vector_init();
/* Look at argv[0] and compute bootdev */
makebootdev(argv[0]);
@ -423,8 +413,7 @@ void
cpu_reboot(volatile int howto, char *bootstr)
{
/* take a snap shot before clobbering any registers */
if (curlwp)
savectx(curpcb);
savectx(curpcb);
#ifdef DEBUG
if (panicstr)
@ -498,7 +487,7 @@ unimpl_cons_init(void)
}
static void
unimpl_iointr(u_int mask, u_int pc, u_int statusreg, u_int causereg)
unimpl_iointr(uint32_t status, vaddr_t pc, uint32_t ipending)
{
panic("sysconf.init didn't set intr");

32
sys/arch/mipsco/mipsco/mainbus.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: mainbus.c,v 1.9 2009/03/14 15:36:10 dsl Exp $ */
/* $NetBSD: mainbus.c,v 1.10 2011/02/20 07:56:16 matt Exp $ */
/*
* Copyright (c) 1994, 1995 Carnegie-Mellon University.
@ -29,7 +29,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.9 2009/03/14 15:36:10 dsl Exp $");
__KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.10 2011/02/20 07:56:16 matt Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -38,43 +38,35 @@ __KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.9 2009/03/14 15:36:10 dsl Exp $");
#include <machine/autoconf.h>
struct mainbus_softc {
struct device sc_dev;
};
/* Definition of the mainbus driver. */
static int mbmatch(struct device *, struct cfdata *, void *);
static void mbattach(struct device *, struct device *, void *);
static int mbmatch(device_t, cfdata_t, void *);
static void mbattach(device_t, device_t, void *);
static int mbprint(void *, const char *);
CFATTACH_DECL(mainbus, sizeof(struct mainbus_softc),
CFATTACH_DECL_NEW(mainbus, 0,
mbmatch, mbattach, NULL, NULL);
static int mb_attached;
static bool mb_attached;
static int
mbmatch(struct device *parent, struct cfdata *cfdata, void *aux)
mbmatch(device_t parent, cfdata_t cfdata, void *aux)
{
if (mb_attached)
return 0;
return 1;
return !mb_attached;
}
static void
mbattach(struct device *parent, struct device *self, void *aux)
mbattach(device_t parent, device_t self, void *aux)
{
register struct device *mb = self;
struct confargs nca;
mb_attached = 1;
mb_attached = true;
printf("\n");
aprint_normal("\n");
nca.ca_name = "cpu";
nca.ca_addr = 0;
config_found(mb, &nca, mbprint);
config_found(self, &nca, mbprint);
nca.ca_name = "obio";
nca.ca_addr = 0;

57
sys/arch/mipsco/mipsco/mips_3x30.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: mips_3x30.c,v 1.12 2009/03/14 21:04:12 dsl Exp $ */
/* $NetBSD: mips_3x30.c,v 1.13 2011/02/20 07:56:16 matt Exp $ */
/*
* Copyright (c) 2000 The NetBSD Foundation, Inc.
@ -29,30 +29,30 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#define __INTR_PRIVATE
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: mips_3x30.c,v 1.12 2009/03/14 21:04:12 dsl Exp $");
__KERNEL_RCSID(0, "$NetBSD: mips_3x30.c,v 1.13 2011/02/20 07:56:16 matt Exp $");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <sys/proc.h>
#include <sys/kernel.h>
#include <sys/cpu.h>
#include <sys/intr.h>
#include <machine/locore.h>
#include <machine/trap.h>
#include <machine/psl.h>
#include <machine/cpu.h>
#include <machine/intr.h>
#include <machine/mainboard.h>
#include <machine/sysconf.h>
extern void MachFPInterrupt (u_int, u_int, u_int, struct frame *);
/* Local functions */
void pizazz_init (void);
void pizazz_intr (u_int, u_int, u_int, u_int);
int pizazz_level0_intr (void *);
void pizazz_level5_intr (int, int, int);
void pizazz_intr_establish (int, int (*)(void *), void *);
void pizazz_init(void);
void pizazz_intr(uint32_t, vaddr_t, uint32_t);
int pizazz_level0_intr(void *);
void pizazz_level5_intr(uint32_t, vaddr_t);
void pizazz_intr_establish (int, int (*)(void *), void *);
#define INT_MASK_FPU MIPS_INT_MASK_3
@ -64,6 +64,8 @@ pizazz_init(void)
platform.iointr = pizazz_intr;
platform.intr_establish = pizazz_intr_establish;
ipl_sr_map = mipsco_ipl_sr_map;
pizazz_intr_establish(SYS_INTR_LEVEL0, pizazz_level0_intr, NULL);
strcpy(cpu_model, "Mips 3230 Magnum (Pizazz)");
@ -78,10 +80,7 @@ pizazz_init(void)
} while (0)
void
pizazz_intr(u_int status, u_int cause, u_int pc, u_int ipending)
/* status: status register at time of the exception */
/* cause: cause register at time of exception */
/* pc: program counter where to continue */
pizazz_intr(uint32_t status, vaddr_t pc, uint32_t ipending)
{
/* handle clock interrupts ASAP */
if (ipending & MIPS_INT_MASK_2) { /* Timer Interrupt */
@ -90,37 +89,27 @@ pizazz_intr(u_int status, u_int cause, u_int pc, u_int ipending)
cf.pc = pc;
cf.sr = status;
cf.intr = (curcpu()->ci_idepth > 0);
rambo_clkintr(&cf);
/* keep clock interrupts enabled when we return */
cause &= ~MIPS_INT_MASK_2;
}
/* If clock interrupts were enabled, re-enable them ASAP. */
_splset(MIPS_SR_INT_IE | (status & MIPS_INT_MASK_2));
if (ipending & MIPS_INT_MASK_5) /* level 5 interrupt */
pizazz_level5_intr(pc, cause, status);
pizazz_level5_intr(status, pc);
HANDLE_INTR(SYS_INTR_FDC, MIPS_INT_MASK_4);
HANDLE_INTR(SYS_INTR_SCSI, MIPS_INT_MASK_1);
HANDLE_INTR(SYS_INTR_LEVEL0, MIPS_INT_MASK_0);
/* XXX: Keep FDC interrupt masked off */
cause &= ~(MIPS_INT_MASK_0 | MIPS_INT_MASK_1 | MIPS_INT_MASK_5);
_splset((status & ~cause & MIPS_HARD_INT_MASK) | MIPS_SR_INT_IE);
#if !defined(NOFPU)
/* FPU nofiticaition */
if (ipending & INT_MASK_FPU) {
if (!USERMODE(status))
panic("kernel used FPU: PC %x, CR %x, SR %x",
pc, cause, status);
#if !defined(SOFTFLOAT)
MachFPInterrupt(status, cause, pc, curlwp->l_md.md_regs);
#endif
panic("kernel used FPU: PC %x, SR %x",
pc, status);
mips_fpu_intr(pc, curlwp->l_md.md_utf);
}
#endif
}
/*
@ -153,13 +142,13 @@ pizazz_level0_intr(void *arg)
* Motherboard Parity Error
*/
void
pizazz_level5_intr(int pc, int cause, int status)
pizazz_level5_intr(uint32_t status, vaddr_t pc)
{
u_int32_t ereg;
ereg = *(u_int32_t *)RAMBO_ERREG;
printf("interrupt: pc=%p cr=%x sr=%x\n", (void *)pc, cause, status);
printf("interrupt: pc=%p sr=%x\n", (void *)pc, status);
printf("parity error: %p mask: 0x%x\n", (void *)ereg, ereg & 0xf);
panic("memory fault");
}

15
sys/arch/newsmips/apbus/apbus.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: apbus.c,v 1.21 2008/04/09 15:40:30 tsutsui Exp $ */
/* $NetBSD: apbus.c,v 1.22 2011/02/20 07:56:31 matt Exp $ */
/*-
* Copyright (C) 1999 SHIMIZU Ryo. All rights reserved.
@ -27,13 +27,16 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: apbus.c,v 1.21 2008/04/09 15:40:30 tsutsui Exp $");
__KERNEL_RCSID(0, "$NetBSD: apbus.c,v 1.22 2011/02/20 07:56:31 matt Exp $");
#define __INTR_PRIVATE
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/malloc.h>
#include <sys/device.h>
#include <sys/proc.h>
#include <sys/intr.h>
#include <uvm/uvm_extern.h>
@ -41,7 +44,6 @@ __KERNEL_RCSID(0, "$NetBSD: apbus.c,v 1.21 2008/04/09 15:40:30 tsutsui Exp $");
#include <machine/autoconf.h>
#define _NEWSMIPS_BUS_DMA_PRIVATE
#include <machine/bus.h>
#include <machine/intr.h>
#include <newsmips/apbus/apbusvar.h>
static int apbusmatch(device_t, cfdata_t, void *);
@ -97,6 +99,8 @@ apbusattach(device_t parent, device_t self, void *aux)
struct newsmips_intr *ip;
int i;
mips_set_wbflush(apbus_wbflush);
*(volatile uint32_t *)(NEWS5000_APBUS_INTST) = 0xffffffff;
*(volatile uint32_t *)(NEWS5000_APBUS_INTMSK) = 0xffffffff;
*(volatile uint32_t *)(NEWS5000_APBUS_CTRL) = 0x00000004;
@ -176,9 +180,10 @@ aptokseg0(void *va)
void
apbus_wbflush(void)
{
volatile int32_t *wbflush = (uint32_t *)NEWS5000_WBFLUSH;
volatile int32_t * const our_wbflush = (int32_t *)NEWS5000_WBFLUSH;
(void)*wbflush;
(*mips_locore_jumpvec.ljv_wbflush)();
(void)*our_wbflush;
}
/*

10
sys/arch/newsmips/apbus/if_snvar.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: if_snvar.h,v 1.12 2008/04/09 15:40:30 tsutsui Exp $ */
/* $NetBSD: if_snvar.h,v 1.13 2011/02/20 07:56:31 matt Exp $ */
/*
* Copyright (c) 1991 Algorithmics Ltd (http://www.algor.co.uk)
@ -32,14 +32,6 @@
#define SN_REGSIZE (SN_NREGS * 4)
#include <mips/locore.h>
#undef wbflush /* XXX */
static inline void
wbflush(void)
{
mips3_wbflush();
apbus_wbflush();
};
/*
* buffer sizes in 32 bit mode

12
sys/arch/newsmips/apbus/if_tlp_ap.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: if_tlp_ap.c,v 1.11 2009/04/17 14:48:17 tsutsui Exp $ */
/* $NetBSD: if_tlp_ap.c,v 1.12 2011/02/20 07:56:31 matt Exp $ */
/*
* Copyright (c) 2000 The NetBSD Foundation, Inc.
@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: if_tlp_ap.c,v 1.11 2009/04/17 14:48:17 tsutsui Exp $");
__KERNEL_RCSID(0, "$NetBSD: if_tlp_ap.c,v 1.12 2011/02/20 07:56:31 matt Exp $");
#include <sys/param.h>
#include <sys/device.h>
@ -155,10 +155,10 @@ tlp_ap_attach(device_t parent, device_t self, void *aux)
/*
* Initialize bus specific parameters.
*/
if (mips_sdcache_line_size > 0)
sc->sc_cacheline = mips_sdcache_line_size / 4;
else if (mips_pdcache_line_size > 0)
sc->sc_cacheline = mips_pdcache_line_size / 4;
if (mips_cache_info.mci_sdcache_line_size > 0)
sc->sc_cacheline = mips_cache_info.mci_sdcache_line_size / 4;
else if (mips_cache_info.mci_pdcache_line_size > 0)
sc->sc_cacheline = mips_cache_info.mci_pdcache_line_size / 4;
else
sc->sc_cacheline = 4;
sc->sc_maxburst = sc->sc_cacheline; /* XXX */

4
sys/arch/newsmips/conf/files.newsmips
View File

@ -1,4 +1,4 @@
# $NetBSD: files.newsmips,v 1.27 2009/08/21 04:03:01 thorpej Exp $
# $NetBSD: files.newsmips,v 1.28 2011/02/20 07:56:31 matt Exp $
# NEWSMIPS-specific configuration info
@ -98,8 +98,6 @@ file dev/cons.c
file common/bus_dma/bus_dmamem_common.c
file arch/mips/mips/softintr.c
#
# Machine-independent SCSI driver.
#

7
sys/arch/newsmips/dev/hb.c
View File

@ -1,15 +1,16 @@
/* $NetBSD: hb.c,v 1.18 2008/04/09 15:40:30 tsutsui Exp $ */
/* $NetBSD: hb.c,v 1.19 2011/02/20 07:56:31 matt Exp $ */
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: hb.c,v 1.18 2008/04/09 15:40:30 tsutsui Exp $");
__KERNEL_RCSID(0, "$NetBSD: hb.c,v 1.19 2011/02/20 07:56:31 matt Exp $");
#define __INTR_PRIVATE
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <sys/malloc.h>
#include <sys/intr.h>
#include <machine/autoconf.h>
#include <machine/intr.h>
#include <newsmips/dev/hbvar.h>

6
sys/arch/newsmips/dev/scsi_1185.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: scsi_1185.c,v 1.19 2008/04/09 15:40:30 tsutsui Exp $ */
/* $NetBSD: scsi_1185.c,v 1.20 2011/02/20 07:56:31 matt Exp $ */
/*
* Copyright (c) 1992, 1993
@ -53,11 +53,13 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: scsi_1185.c,v 1.19 2008/04/09 15:40:30 tsutsui Exp $");
__KERNEL_RCSID(0, "$NetBSD: scsi_1185.c,v 1.20 2011/02/20 07:56:31 matt Exp $");
#define __INTR_PRIVATE
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <sys/intr.h>
#include <uvm/uvm_extern.h>

61
sys/arch/newsmips/include/intr.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: intr.h,v 1.24 2009/04/10 13:29:30 tsutsui Exp $ */
/* $NetBSD: intr.h,v 1.25 2011/02/20 07:56:31 matt Exp $ */
/*-
* Copyright (c) 2000, 2001 The NetBSD Foundation, Inc.
@ -32,56 +32,15 @@
#ifndef _MACHINE_INTR_H_
#define _MACHINE_INTR_H_
#define IPL_NONE 0 /* disable only this interrupt */
#define IPL_SOFTCLOCK 1 /* clock software interrupts (SI 0) */
#define IPL_SOFTBIO 1 /* bio software interrupts (SI 0) */
#define IPL_SOFTNET 2 /* network software interrupts (SI 1) */
#define IPL_SOFTSERIAL 2 /* serial software interrupts (SI 1) */
#define IPL_VM 3
#define IPL_SCHED 4 /* disable clock interrupts */
#define IPL_HIGH 4 /* disable all interrupts */
#define _IPL_N 5
#define _IPL_SI0_FIRST IPL_SOFTCLOCK
#define _IPL_SI0_LAST IPL_SOFTBIO
#define _IPL_SI1_FIRST IPL_SOFTNET
#define _IPL_SI1_LAST IPL_SOFTSERIAL
#include <mips/intr.h>
#ifdef _KERNEL
#ifndef _LOCORE
#ifdef __INTR_PRIVATE
#include <sys/evcnt.h>
#include <mips/locore.h>
extern const uint32_t ipl_sr_bits[_IPL_N];
#define spl0() (void)_spllower(0)
#define splx(s) (void)_splset(s)
#define splsoft() _splraise(ipl_sr_bits[IPL_SOFT])
typedef int ipl_t;
typedef struct {
ipl_t _sr;
} ipl_cookie_t;
static inline ipl_cookie_t
makeiplcookie(ipl_t ipl)
{
return (ipl_cookie_t){._sr = ipl_sr_bits[ipl]};
}
static inline int
splraiseipl(ipl_cookie_t icookie)
{
return _splraise(icookie._sr);
}
#include <sys/spl.h>
extern const struct ipl_sr_map newmips_ipl_sr_map;
struct newsmips_intrhand {
LIST_ENTRY(newsmips_intrhand) ih_q;
@ -117,18 +76,14 @@ struct newsmips_intr {
extern u_int intrcnt[];
/* handle i/o device interrupts */
#ifdef news3400
void news3400_intr(uint32_t, uint32_t, uint32_t, uint32_t);
#endif
#ifdef news5000
void news5000_intr(uint32_t, uint32_t, uint32_t, uint32_t);
#endif
extern void (*hardware_intr)(uint32_t, uint32_t, uint32_t, uint32_t);
void news3400_intr(int, vaddr_t, uint32_t);
void news5000_intr(int, vaddr_t, uint32_t);
extern void (*hardware_intr)(int, vaddr_t, uint32_t);
extern void (*enable_intr)(void);
extern void (*disable_intr)(void);
extern void (*enable_timer)(void);
#endif /* !_LOCORE */
#endif /* __INTR_PRIVATE */
#endif /* _KERNEL */
#endif /* _MACHINE_INTR_H_ */

13
sys/arch/newsmips/newsmips/autoconf.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: autoconf.c,v 1.33 2011/02/08 20:20:21 rmind Exp $ */
/* $NetBSD: autoconf.c,v 1.34 2011/02/20 07:56:31 matt Exp $ */
/*
* Copyright (c) 1988 University of Utah.
@ -46,8 +46,10 @@
* and the drivers are initialized.
*/
#define __INTR_PRIVATE
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.33 2011/02/08 20:20:21 rmind Exp $");
__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.34 2011/02/20 07:56:31 matt Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -55,12 +57,13 @@ __KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.33 2011/02/08 20:20:21 rmind Exp $");
#include <sys/conf.h>
#include <sys/reboot.h>
#include <sys/device.h>
#include <sys/intr.h>
#include <sys/cpu.h>
#include <dev/scsipi/scsi_all.h>
#include <dev/scsipi/scsipi_all.h>
#include <dev/scsipi/scsiconf.h>
#include <machine/cpu.h>
#include <machine/adrsmap.h>
#include <machine/romcall.h>
@ -91,7 +94,7 @@ cpu_configure(void)
/*
* Kick off autoconfiguration
*/
_splnone(); /* enable all interrupts */
spl0(); /* enable all interrupts */
splhigh(); /* ...then disable device interrupts */
if (systype == NEWS3400) {
@ -106,7 +109,7 @@ cpu_configure(void)
enable_intr();
/* Configuration is finished, turn on interrupts. */
_splnone(); /* enable all source forcing SOFT_INTs cleared */
spl0(); /* enable all source forcing SOFT_INTs cleared */
}
void

13
sys/arch/newsmips/newsmips/bus.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: bus.c,v 1.30 2009/12/14 00:46:09 matt Exp $ */
/* $NetBSD: bus.c,v 1.31 2011/02/20 07:56:31 matt Exp $ */
/*
* Copyright (c) 1998 The NetBSD Foundation, Inc.
@ -31,7 +31,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: bus.c,v 1.30 2009/12/14 00:46:09 matt Exp $");
__KERNEL_RCSID(0, "$NetBSD: bus.c,v 1.31 2011/02/20 07:56:31 matt Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -515,7 +515,7 @@ _bus_dmamap_sync_r3k(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t offset,
* NOTE: Even though this is `wbinv_all', since the cache is
* write-though, it just invalidates it.
*/
if (len >= mips_pdcache_size) {
if (len >= mips_cache_info.mci_pdcache_size) {
mips_dcache_wbinv_all();
return;
}
@ -703,12 +703,9 @@ _bus_dmamem_alloc(bus_dma_tag_t t, bus_size_t size, bus_size_t alignment,
bus_size_t boundary, bus_dma_segment_t *segs, int nsegs, int *rsegs,
int flags)
{
extern paddr_t avail_start, avail_end;
return (_bus_dmamem_alloc_range_common(t, size, alignment, boundary,
segs, nsegs, rsegs, flags,
avail_start /*low*/,
avail_end - PAGE_SIZE /*high*/));
segs, nsegs, rsegs, flags,
mips_avail_start /*low*/, mips_avail_end - PAGE_SIZE /*high*/));
}
/*

10
sys/arch/newsmips/newsmips/clock.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: clock.c,v 1.15 2006/09/04 20:33:24 tsutsui Exp $ */
/* $NetBSD: clock.c,v 1.16 2011/02/20 07:56:31 matt Exp $ */
/*
* Copyright (c) 1992, 1993
@ -41,15 +41,15 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: clock.c,v 1.15 2006/09/04 20:33:24 tsutsui Exp $");
__KERNEL_RCSID(0, "$NetBSD: clock.c,v 1.16 2011/02/20 07:56:31 matt Exp $");
#define __INTR_PRIVATE
#include <sys/param.h>
#include <sys/kernel.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <machine/cpu.h>
#include <machine/intr.h>
#include <sys/cpu.h>
#include <sys/intr.h>
/*
* Set up the real-time and statistics clocks. Leave stathz 0 only

24
sys/arch/newsmips/newsmips/cpu.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpu.c,v 1.11 2005/12/11 12:18:25 christos Exp $ */
/* $NetBSD: cpu.c,v 1.12 2011/02/20 07:56:31 matt Exp $ */
/*
* Copyright (c) 1994, 1995 Carnegie-Mellon University.
@ -28,28 +28,28 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.11 2005/12/11 12:18:25 christos Exp $");
__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.12 2011/02/20 07:56:31 matt Exp $");
#include <sys/param.h>
#include <sys/device.h>
#include <sys/cpu.h>
#include <sys/systm.h>
#include <mips/locore.h>
#include <machine/cpu.h>
#include <machine/autoconf.h>
/* Definition of the driver for autoconfig. */
static int cpumatch(struct device *, struct cfdata *, void *);
static void cpuattach(struct device *, struct device *, void *);
static int cpumatch(device_t, cfdata_t, void *);
static void cpuattach(device_t, device_t, void *);
CFATTACH_DECL(cpu, sizeof(struct device),
CFATTACH_DECL_NEW(cpu, 0,
cpumatch, cpuattach, NULL, NULL);
extern struct cfdriver cpu_cd;
static int
cpumatch(struct device *parent, struct cfdata *cfdata, void *aux)
cpumatch(device_t parent, cfdata_t cfdata, void *aux)
{
struct confargs *ca = aux;
@ -61,9 +61,13 @@ cpumatch(struct device *parent, struct cfdata *cfdata, void *aux)
}
static void
cpuattach(struct device *parent, struct device *dev, void *aux)
cpuattach(device_t parent, device_t self, void *aux)
{
struct cpu_info * const ci = curcpu();
printf(": ");
cpu_identify();
ci->ci_dev = self;
self->dv_private = ci;
aprint_normal(": ");
cpu_identify(self);
}

12
sys/arch/newsmips/newsmips/locore_machdep.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: locore_machdep.S,v 1.15 2009/12/17 05:29:56 matt Exp $ */
/* $NetBSD: locore_machdep.S,v 1.16 2011/02/20 07:56:31 matt Exp $ */
/*
* Copyright (c) 1992, 1993
@ -133,9 +133,7 @@ outofworld:
/*
* Interrupt counters for vmstat.
*/
.data
.globl _C_LABEL(intrcnt)
.globl _C_LABEL(eintrcnt)
.rdata
.globl _C_LABEL(intrnames)
.globl _C_LABEL(eintrnames)
_C_LABEL(intrnames):
@ -155,7 +153,11 @@ _C_LABEL(intrnames):
.asciiz "nmi"
.asciiz "lostclock"
_C_LABEL(eintrnames):
.align 2
.data
.globl _C_LABEL(intrcnt)
.globl _C_LABEL(eintrcnt)
.p2align 2
_C_LABEL(intrcnt):
.word 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0
_C_LABEL(eintrcnt):

78
sys/arch/newsmips/newsmips/machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: machdep.c,v 1.111 2011/02/08 20:20:21 rmind Exp $ */
/* $NetBSD: machdep.c,v 1.112 2011/02/20 07:56:31 matt Exp $ */
/*
* Copyright (c) 1988 University of Utah.
@ -39,7 +39,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.111 2011/02/08 20:20:21 rmind Exp $");
__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.112 2011/02/20 07:56:31 matt Exp $");
/* from: Utah Hdr: machdep.c 1.63 91/04/24 */
@ -47,6 +47,8 @@ __KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.111 2011/02/08 20:20:21 rmind Exp $");
#include "opt_execfmt.h"
#include "opt_modular.h"
#define __INTR_PRIVATE
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/signalvar.h>
@ -66,13 +68,13 @@ __KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.111 2011/02/08 20:20:21 rmind Exp $");
#include <sys/syscallargs.h>
#include <sys/kcore.h>
#include <sys/ksyms.h>
#include <sys/cpu.h>
#include <sys/intr.h>
#include <uvm/uvm_extern.h>
#include <ufs/mfs/mfs_extern.h> /* mfs_initminiroot() */
#include <machine/cpu.h>
#include <machine/intr.h>
#include <machine/reg.h>
#include <machine/psl.h>
#include <machine/pte.h>
@ -116,7 +118,7 @@ phys_ram_seg_t mem_clusters[VM_PHYSSEG_MAX];
int mem_cluster_cnt;
struct idrom idrom;
void (*hardware_intr)(uint32_t, uint32_t, uint32_t, uint32_t);
void (*hardware_intr)(int, vaddr_t, uint32_t);
void (*enable_intr)(void);
void (*disable_intr)(void);
void (*enable_timer)(void);
@ -136,33 +138,25 @@ void to_monitor(int) __attribute__((__noreturn__));
extern void stacktrace(void); /*XXX*/
#endif
/*
* safepri is a safe priority for sleep to set for a spin-wait
* during autoconfiguration or after a panic. Used as an argument to splx().
* XXX disables interrupt 5 to disable mips3 on-chip clock, which also
* disables mips1 FPU interrupts.
*/
int safepri = MIPS3_PSL_LOWIPL; /* XXX */
/*
* This is a mask of bits to clear in the SR when we go to a
* given interrupt priority level.
*/
const uint32_t ipl_sr_bits[_IPL_N] = {
[IPL_NONE] = 0,
[IPL_SOFTCLOCK] =
MIPS_SOFT_INT_MASK_0,
[IPL_SOFTNET] =
MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1,
[IPL_VM] =
MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 |
MIPS_INT_MASK_0 |
MIPS_INT_MASK_1,
[IPL_SCHED] =
MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 |
MIPS_INT_MASK_0 |
MIPS_INT_MASK_1 |
MIPS_INT_MASK_2,
const struct ipl_sr_map newsmips_ipl_sr_map = {
.sr_bits = {
[IPL_NONE] = 0,
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
[IPL_SOFTNET] = MIPS_SOFT_INT_MASK,
[IPL_VM] = MIPS_SOFT_INT_MASK
| MIPS_INT_MASK_0
| MIPS_INT_MASK_1,
[IPL_SCHED] = MIPS_SOFT_INT_MASK
| MIPS_INT_MASK_0
| MIPS_INT_MASK_1
| MIPS_INT_MASK_2,
[IPL_DDB] = MIPS_INT_MASK,
[IPL_HIGH] = MIPS_INT_MASK,
},
};
extern u_long bootdev;
@ -290,7 +284,8 @@ mach_init(int x_boothowto, int x_bootdev, int x_bootname, int x_maxmem)
* Initialize locore-function vector.
* Clear out the I and D caches.
*/
mips_vector_init();
ipl_sr_map = newsmips_ipl_sr_map;
mips_vector_init(NULL, false);
/*
* We know the CPU type now. Initialize our DMA tags (might
@ -389,7 +384,7 @@ mips_machdep_cache_config(void)
{
/* All r4k news boxen have a 1MB L2 cache. */
if (CPUISMIPS3)
mips_sdcache_size = 1024 * 1024;
mips_cache_info.mci_sdcache_size = 1024 * 1024;
}
/*
@ -487,8 +482,7 @@ cpu_reboot(volatile int howto, char *bootstr)
{
/* take a snap shot before clobbering any registers */
if (curlwp)
savectx(curpcb);
savectx(curpcb);
#ifdef DEBUG
if (panicstr)
@ -557,24 +551,10 @@ delay(int n)
}
void
cpu_intr(uint32_t status, uint32_t cause, vaddr_t pc, uint32_t ipending)
cpu_intr(int ppl, vaddr_t pc, uint32_t status)
{
struct cpu_info *ci;
ci = curcpu();
ci->ci_data.cpu_nintr++;
curcpu()->ci_data.cpu_nintr++;
/* device interrupts */
ci->ci_idepth++;
(*hardware_intr)(status, cause, pc, ipending);
ci->ci_idepth--;
#ifdef __HAVE_FAST_SOFTINTS
/* software interrupts */
ipending &= (MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0);
if (ipending == 0)
return;
_clrsoftintr(ipending);
softintr_dispatch(ipending);
#endif
(*hardware_intr)(ppl, pc, status);
}

116
sys/arch/newsmips/newsmips/news3400.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: news3400.c,v 1.19 2007/12/03 15:34:05 ad Exp $ */
/* $NetBSD: news3400.c,v 1.20 2011/02/20 07:56:31 matt Exp $ */
/*-
* Copyright (C) 1999 Tsubai Masanari. All rights reserved.
@ -27,25 +27,24 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: news3400.c,v 1.19 2007/12/03 15:34:05 ad Exp $");
__KERNEL_RCSID(0, "$NetBSD: news3400.c,v 1.20 2011/02/20 07:56:31 matt Exp $");
#define __INTR_PRIVATE
#include <sys/param.h>
#include <sys/kernel.h>
#include <sys/proc.h>
#include <sys/systm.h>
#include <sys/cpu.h>
#include <sys/intr.h>
#include <mips/locore.h>
#include <machine/adrsmap.h>
#include <machine/cpu.h>
#include <machine/intr.h>
#include <machine/psl.h>
#include <newsmips/newsmips/machid.h>
#include <newsmips/dev/hbvar.h>
#if !defined(SOFTFLOAT)
extern void MachFPInterrupt(unsigned, unsigned, unsigned, struct frame *);
#endif
int news3400_badaddr(void *, u_int);
static void news3400_level0_intr(void);
@ -63,76 +62,67 @@ static volatile int badaddr_flag;
* Handle news3400 interrupts.
*/
void
news3400_intr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending)
news3400_intr(int ppl, uint32_t pc, uint32_t status)
{
struct clockframe cf;
struct cpu_info *ci;
uint32_t ipending;
int ipl;
ci = curcpu();
ci->ci_idepth++;
while (ppl < (ipl = splintr(&ipending))) {
/* handle clock interrupts ASAP */
if (ipending & MIPS_INT_MASK_2) {
int stat;
if (ipending & MIPS_INT_MASK_2) {
int stat;
stat = *(volatile uint8_t *)INTST0;
stat &= INTST0_TIMINT|INTST0_KBDINT|INTST0_MSINT;
stat = *(volatile uint8_t *)INTST0;
stat &= INTST0_TIMINT|INTST0_KBDINT|INTST0_MSINT;
*(volatile uint8_t *)INTCLR0 = stat;
if (stat & INTST0_TIMINT) {
struct clockframe cf = {
.pc = pc,
.sr = status,
.intr = (curcpu()->ci_idepth > 0),
};
hardclock(&cf);
intrcnt[HARDCLOCK_INTR]++;
}
if (stat)
hb_intr_dispatch(2, stat);
*(volatile uint8_t *)INTCLR0 = stat;
if (stat & INTST0_TIMINT) {
cf.pc = pc;
cf.sr = status;
hardclock(&cf);
intrcnt[HARDCLOCK_INTR]++;
stat &= ~INTST0_TIMINT;
}
if (stat)
hb_intr_dispatch(2, stat);
if (ipending & MIPS_INT_MASK_5) {
*(volatile uint8_t *)INTCLR0 = INTCLR0_PERR;
printf("Memory error interrupt(?) at 0x%x\n", pc);
}
cause &= ~MIPS_INT_MASK_2;
}
/* If clock interrupts were enabled, re-enable them ASAP. */
_splset(MIPS_SR_INT_IE | (status & MIPS_INT_MASK_2));
/* asynchronous bus error */
if (ipending & MIPS_INT_MASK_4) {
*(volatile uint8_t *)INTCLR0 = INTCLR0_BERR;
badaddr_flag = 1;
}
if (ipending & MIPS_INT_MASK_5) {
*(volatile uint8_t *)INTCLR0 = INTCLR0_PERR;
printf("Memory error interrupt(?) at 0x%x\n", pc);
cause &= ~MIPS_INT_MASK_5;
}
if (ipending & MIPS_INT_MASK_1) {
news3400_level1_intr();
}
/* asynchronous bus error */
if (ipending & MIPS_INT_MASK_4) {
*(volatile uint8_t *)INTCLR0 = INTCLR0_BERR;
cause &= ~MIPS_INT_MASK_4;
badaddr_flag = 1;
}
if (ipending & MIPS_INT_MASK_0) {
news3400_level0_intr();
}
if (ipending & MIPS_INT_MASK_1) {
news3400_level1_intr();
cause &= ~MIPS_INT_MASK_1;
}
/* FPU nofiticaition */
if (ipending & INT_MASK_FPU) {
if (!USERMODE(status))
panic("kernel used FPU: PC %x, SR %x",
pc, status);
if (ipending & MIPS_INT_MASK_0) {
news3400_level0_intr();
cause &= ~MIPS_INT_MASK_0;
}
_splset((status & ~cause & MIPS_HARD_INT_MASK) | MIPS_SR_INT_IE);
/* FPU nofiticaition */
if (ipending & INT_MASK_FPU) {
if (!USERMODE(status))
panic("kernel used FPU: PC %x, CR %x, SR %x",
pc, cause, status);
intrcnt[FPU_INTR]++;
#if !defined(SOFTFLOAT)
MachFPInterrupt(status, cause, pc, curlwp->l_md.md_regs);
intrcnt[FPU_INTR]++;
#if !defined(FPEMUL)
mips_fpu_intr(pc, curlwp->l_md.md_utf);
#endif
}
}
ci->ci_idepth--;
}
#define LEVEL0_MASK \

185
sys/arch/newsmips/newsmips/news5000.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: news5000.c,v 1.17 2007/12/03 15:34:05 ad Exp $ */
/* $NetBSD: news5000.c,v 1.18 2011/02/20 07:56:32 matt Exp $ */
/*-
* Copyright (C) 1999 SHIMIZU Ryo. All rights reserved.
@ -27,16 +27,17 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: news5000.c,v 1.17 2007/12/03 15:34:05 ad Exp $");
__KERNEL_RCSID(0, "$NetBSD: news5000.c,v 1.18 2011/02/20 07:56:32 matt Exp $");
#define __INTR_PRIVATE
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/timetc.h>
#include <sys/cpu.h>
#include <sys/intr.h>
#include <machine/adrsmap.h>
#include <machine/intr.h>
#include <newsmips/apbus/apbusvar.h>
#include <newsmips/newsmips/machid.h>
@ -55,112 +56,102 @@ static uint32_t news5000_getfreerun(struct timecounter *);
* Handle news5000 interrupts.
*/
void
news5000_intr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending)
news5000_intr(int ppl, vaddr_t pc, uint32_t status)
{
struct cpu_info *ci;
uint32_t ipending;
int ipl;
ci = curcpu();
ci->ci_idepth++;
while (ppl < (ipl = splintr(&ipending))) {
if (ipending & MIPS_INT_MASK_2) {
if (ipending & MIPS_INT_MASK_2) {
#ifdef DEBUG
static int l2cnt = 0;
static int l2cnt = 0;
#endif
uint32_t int2stat;
struct clockframe cf;
uint32_t int2stat;
struct clockframe cf;
int2stat = *(volatile uint32_t *)NEWS5000_INTST2;
int2stat = *(volatile uint32_t *)NEWS5000_INTST2;
#ifdef DEBUG
l2cnt++;
if (l2cnt == 50) {
*(volatile uint32_t *)NEWS5000_LED_SEC = 1;
}
if (l2cnt == 100) {
*(volatile uint32_t *)NEWS5000_LED_SEC = 0;
l2cnt = 0;
}
#endif
if (int2stat & NEWS5000_INT2_TIMER0) {
*(volatile uint32_t *)NEWS5000_TIMER0 = 1;
cf.pc = pc;
cf.sr = status;
hardclock(&cf);
intrcnt[HARDCLOCK_INTR]++;
}
apbus_wbflush();
cause &= ~MIPS_INT_MASK_2;
}
/* If clock interrupts were enabled, re-enable them ASAP. */
_splset(MIPS_SR_INT_IE | (status & MIPS_INT_MASK_2));
if (ipending & MIPS_INT_MASK_5) {
uint32_t int5stat;
int5stat = *(volatile u_int *)NEWS5000_INTST5;
printf("level5 interrupt (%08x)\n", int5stat);
apbus_wbflush();
cause &= ~MIPS_INT_MASK_5;
}
if (ipending & MIPS_INT_MASK_4) {
uint32_t int4stat;
int4stat = *(volatile uint32_t *)NEWS5000_INTST4;
printf("level4 interrupt (%08x)\n", int4stat);
if (int4stat & NEWS5000_INT4_APBUS) {
uint32_t stat;
stat = *(volatile uint32_t *)NEWS5000_APBUS_INTST;
printf("APbus error 0x%04x\n", stat & 0xffff);
if (stat & NEWS5000_APBUS_INT_DMAADDR) {
printf("DMA Address Error: "
"slot=%x, addr=0x%08x\n",
*(volatile uint32_t *)NEWS5000_APBUS_DER_S,
*(volatile uint32_t *)NEWS5000_APBUS_DER_A);
l2cnt++;
if (l2cnt == 50) {
*(volatile uint32_t *)NEWS5000_LED_SEC = 1;
}
if (stat & NEWS5000_APBUS_INT_RDTIMEO)
printf("IO Read Timeout: addr=0x%08x\n",
*(volatile uint32_t *)NEWS5000_APBUS_BER_A);
if (stat & NEWS5000_APBUS_INT_WRTIMEO)
printf("IO Write Timeout: addr=0x%08x\n",
*(volatile uint32_t *)NEWS5000_APBUS_BER_A);
*(volatile uint32_t *)0xb4c00014 = stat;
if (l2cnt == 100) {
*(volatile uint32_t *)NEWS5000_LED_SEC = 0;
l2cnt = 0;
}
#endif
if (int2stat & NEWS5000_INT2_TIMER0) {
*(volatile uint32_t *)NEWS5000_TIMER0 = 1;
cf.pc = pc;
cf.sr = status;
hardclock(&cf);
intrcnt[HARDCLOCK_INTR]++;
}
apbus_wbflush();
}
apbus_wbflush();
cause &= ~MIPS_INT_MASK_4;
if (ipending & MIPS_INT_MASK_5) {
uint32_t int5stat;
int5stat = *(volatile u_int *)NEWS5000_INTST5;
printf("level5 interrupt (%08x)\n", int5stat);
apbus_wbflush();
}
if (ipending & MIPS_INT_MASK_4) {
uint32_t int4stat;
int4stat = *(volatile uint32_t *)NEWS5000_INTST4;
printf("level4 interrupt (%08x)\n", int4stat);
if (int4stat & NEWS5000_INT4_APBUS) {
uint32_t stat;
stat = *(volatile uint32_t *)NEWS5000_APBUS_INTST;
printf("APbus error 0x%04x\n", stat & 0xffff);
if (stat & NEWS5000_APBUS_INT_DMAADDR) {
printf("DMA Address Error: "
"slot=%x, addr=0x%08x\n",
*(volatile uint32_t *)NEWS5000_APBUS_DER_S,
*(volatile uint32_t *)NEWS5000_APBUS_DER_A);
}
if (stat & NEWS5000_APBUS_INT_RDTIMEO)
printf("IO Read Timeout: addr=0x%08x\n",
*(volatile uint32_t *)NEWS5000_APBUS_BER_A);
if (stat & NEWS5000_APBUS_INT_WRTIMEO)
printf("IO Write Timeout: addr=0x%08x\n",
*(volatile uint32_t *)NEWS5000_APBUS_BER_A);
*(volatile uint32_t *)0xb4c00014 = stat;
}
apbus_wbflush();
}
if (ipending & MIPS_INT_MASK_3) {
uint32_t int3stat;
int3stat = *(volatile uint32_t *)NEWS5000_INTST3;
printf("level3 interrupt (%08x)\n", int3stat);
apbus_wbflush();
}
if (ipending & MIPS_INT_MASK_1) {
news5000_level1_intr();
apbus_wbflush();
}
if (ipending & MIPS_INT_MASK_0) {
news5000_level0_intr();
apbus_wbflush();
}
}
if (ipending & MIPS_INT_MASK_3) {
uint32_t int3stat;
int3stat = *(volatile uint32_t *)NEWS5000_INTST3;
printf("level3 interrupt (%08x)\n", int3stat);
apbus_wbflush();
cause &= ~MIPS_INT_MASK_3;
}
if (ipending & MIPS_INT_MASK_1) {
news5000_level1_intr();
apbus_wbflush();
cause &= ~MIPS_INT_MASK_1;
}
if (ipending & MIPS_INT_MASK_0) {
news5000_level0_intr();
apbus_wbflush();
cause &= ~MIPS_INT_MASK_0;
}
ci->ci_idepth--;
_splset((status & ~cause & MIPS_HARD_INT_MASK) | MIPS_SR_INT_IE);
}