For each major "module", define a separate set of MMU control register bits.
This commit is contained in:
pk
parent
7d3520e146
commit
8d0c0fd49b
@ -1,4 +1,4 @@
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/* $NetBSD: ctlreg.h,v 1.12 1996/05/16 15:57:00 abrown Exp $ */
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/* $NetBSD: ctlreg.h,v 1.13 1997/03/22 19:15:53 pk Exp $ */
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/*
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* Copyright (c) 1996
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@ -201,35 +201,95 @@
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#define SRMMU_AFADDR 0x00000600 /* Asynchronous fault address reg (HS)*/
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#define SRMMU_TLBCTRL 0x00001000 /* TLB replacement control reg */
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/* [4m] Bits in SRMMU control register */
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#define SRMMU_PCR_ME 0x00000001 /* MMU Enable */
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#define SRMMU_PCR_NF 0x00000002 /* Fault inhibit bit */
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#define SRMMU_PCR_PSO 0x00000080 /* Partial Store Ordering enable */
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#define SRMMU_PCR_CE 0x00000100 /* HS: Cache enable bit (HyperSPARC) */
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#define SRMMU_PCR_DCE 0x00000100 /* SS: Data cache enable bit */
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#define SRMMU_PCR_ICE 0x00000200 /* SS: SuperSPARC instr. cache enable */
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#define SRMMU_PCR_CM 0x00000400 /* HS: Cache mode: 1 == write-back */
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#define SRMMU_PCR_SB 0x00000400 /* SS: Store buffer enable bit */
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#define SRMMU_PCR_MR 0x00000800 /* HS: Memory reflection: 1 == on */
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#define SRMMU_PCR_MB 0x00000800 /* SS: MBus mode: 0=MXCC, 1=no MXCC */
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#define SRMMU_PCR_CS 0x00001000 /* HS: cache size: 1==256k, 0==128k */
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#define SRMMU_PCR_PE 0x00001000 /* SS: Enable memory parity checking */
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#define SRMMU_PCR_C 0x00002000 /* HS: enable cache when MMU off */
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#define SRMMU_PCR_SSBM 0x00002000 /* SS: 1 iff booting */
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#define SRMMU_PCR_HSBM 0x00004000 /* HS: 1 iff booting */
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#define SRMMU_PCR_SSSE 0x00004000 /* SS: Coherent bus snoop enable */
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#define SRMMU_PCR_AC 0x00008000 /* SS: 1=cache non-MMU accesses */
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#define SRMMU_PCR_TC 0x00010000 /* SS: 1=cache table walks */
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#define SRMMU_PCR_MID 0x00078000 /* HS: MBus module ID MID<3:0> */
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#define SRMMU_PCR_WBE 0x00080000 /* HS: Write buffer enable */
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#define SRMMU_PCR_HSSE 0x00100000 /* HS: Coherent bus snoop enable */
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#define SRMMU_PCR_CWR 0x00200000 /* HS: Cache wrap enable */
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/*
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* [4m] Bits in SRMMU control register. One set per module.
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*/
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#define VIKING_PCR_ME 0x00000001 /* MMU Enable */
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#define VIKING_PCR_NF 0x00000002 /* Fault inhibit bit */
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#define VIKING_PCR_PSO 0x00000080 /* Partial Store Ordering enable */
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#define VIKING_PCR_DCE 0x00000100 /* Data cache enable bit */
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#define VIKING_PCR_ICE 0x00000200 /* SuperSPARC instr. cache enable */
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#define VIKING_PCR_SB 0x00000400 /* Store buffer enable bit */
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#define VIKING_PCR_MB 0x00000800 /* MBus mode: 0=MXCC, 1=no MXCC */
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#define VIKING_PCR_PE 0x00001000 /* Enable memory parity checking */
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#define VIKING_PCR_BM 0x00002000 /* 1 iff booting */
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#define VIKING_PCR_SE 0x00004000 /* Coherent bus snoop enable */
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#define VIKING_PCR_AC 0x00008000 /* 1=cache non-MMU accesses */
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#define VIKING_PCR_TC 0x00010000 /* 1=cache table walks */
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#define HYPERSPARC_PCR_ME 0x00000001 /* MMU Enable */
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#define HYPERSPARC_PCR_NF 0x00000002 /* Fault inhibit bit */
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#define HYPERSPARC_PCR_CE 0x00000100 /* Cache enable bit */
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#define HYPERSPARC_PCR_CM 0x00000400 /* Cache mode: 1=write-back */
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#define HYPERSPARC_PCR_MR 0x00000800 /* Memory reflection: 1 = on */
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#define HYPERSPARC_PCR_CS 0x00001000 /* cache size: 1=256k, 0=128k */
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#define HYPERSPARC_PCR_C 0x00002000 /* enable cache when MMU off */
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#define HYPERSPARC_PCR_BM 0x00004000 /* 1 iff booting */
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#define HYPERSPARC_PCR_MID 0x00078000 /* MBus module ID MID<3:0> */
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#define HYPERSPARC_PCR_WBE 0x00080000 /* Write buffer enable */
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#define HYPERSPARC_PCR_SE 0x00100000 /* Coherent bus snoop enable */
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#define HYPERSPARC_PCR_CWR 0x00200000 /* Cache wrap enable */
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#define CYPRESS_PCR_ME 0x00000001 /* MMU Enable */
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#define CYPRESS_PCR_NF 0x00000002 /* Fault inhibit bit */
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#define CYPRESS_PCR_CE 0x00000100 /* Cache enable bit */
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#define CYPRESS_PCR_CL 0x00000200 /* Cache Lock (604 only) */
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#define CYPRESS_PCR_CM 0x00000400 /* Cache mode: 1=write-back */
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#define CYPRESS_PCR_MR 0x00000800 /* Memory reflection: 1=on (605 only) */
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#define CYPRESS_PCR_C 0x00002000 /* enable cache when MMU off */
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#define CYPRESS_PCR_BM 0x00004000 /* 1 iff booting */
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#define CYPRESS_PCR_MID 0x00078000 /* MBus module ID MID<3:0> (605 only) */
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#define CYPRESS_PCR_MV 0x00080000 /* Multichip Valid */
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#define CYPRESS_PCR_MCM 0x00300000 /* Multichip Mask */
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#define CYPRESS_PCR_MCA 0x00c00000 /* Multichip Address */
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#define MS1_PCR_ME 0x00000001 /* MMU Enable */
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#define MS1_PCR_NF 0x00000002 /* Fault inhibit bit */
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#define MS1_PCR_DCE 0x00000100 /* Data cache enable */
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#define MS1_PCR_ICE 0x00000200 /* Instruction cache enable */
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#define MS1_PCR_RC 0x00000c00 /* DRAM Refresh control */
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#define MS1_PCR_PE 0x00001000 /* Enable memory parity checking */
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#define MS1_PCR_BM 0x00004000 /* 1 iff booting */
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#define MS1_PCR_AC 0x00008000 /* 1=cache if ME==0 (and [ID]CE on) */
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#define MS1_PCR_ID 0x00010000 /* 1=disable ITBR */
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#define MS1_PCR_PC 0x00020000 /* Parity control: 0=even,1=odd */
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#define MS1_PCR_MV 0x00100000 /* Memory data View (diag) */
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#define MS1_PCR_DV 0x00200000 /* Data View (diag) */
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#define MS1_PCR_AV 0x00400000 /* Address View (diag) */
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#define MS1_PCR_STW 0x00800000 /* Software Tablewalk enable */
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#define SWIFT_PCR_ME 0x00000001 /* MMU Enable */
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#define SWIFT_PCR_NF 0x00000002 /* Fault inhibit bit */
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#define SWIFT_PCR_DCE 0x00000100 /* Data cache enable */
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#define SWIFT_PCR_ICE 0x00000200 /* Instruction cache enable */
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#define SWIFT_PCR_RC 0x00003c00 /* DRAM Refresh control */
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#define SWIFT_PCR_BM 0x00004000 /* 1 iff booting */
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#define SWIFT_PCR_AC 0x00008000 /* 1=cache if ME=0 (and [ID]CE on) */
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#define SWIFT_PCR_PA 0x00010000 /* TCX/SX control */
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#define SWIFT_PCR_PC 0x00020000 /* Parity control: 0=even,1=odd */
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#define SWIFT_PCR_PE 0x00040000 /* Enable memory parity checking */
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#define SWIFT_PCR_PMC 0x00180000 /* Page mode control */
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#define SWIFT_PCR_BF 0x00200000 /* Branch Folding */
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#define SWIFT_PCR_WP 0x00400000 /* Watch point enable */
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#define SWIFT_PCR_STW 0x00800000 /* Software Tablewalk enable */
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#define TURBOSPARC_PCR_ME 0x00000001 /* MMU Enable */
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#define TURBOSPARC_PCR_NF 0x00000002 /* Fault inhibit bit */
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#define TURBOSPARC_PCR_ICS 0x00000004 /* I-cache snoop enable */
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#define TURBOSPARC_PCR_PSO 0x00000008 /* Partial Store order (ro!) */
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#define TURBOSPARC_PCR_DCE 0x00000100 /* Data cache enable */
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#define TURBOSPARC_PCR_ICE 0x00000200 /* Instruction cache enable */
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#define TURBOSPARC_PCR_RC 0x00003c00 /* DRAM Refresh control */
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#define TURBOSPARC_PCR_BM 0x00004000 /* 1 iff booting */
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#define TURBOSPARC_PCR_PC 0x00020000 /* Parity ctrl: 0=even,1=odd */
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#define TURBOSPARC_PCR_PE 0x00040000 /* Enable parity checking */
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#define TURBOSPARC_PCR_PMC 0x00180000 /* Page mode control */
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/* Implementation and Version fields are common to all modules */
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#define SRMMU_PCR_VER 0x0f000000 /* Version of MMU implementation */
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#define SRMMU_PCR_IMPL 0xf0000000 /* Implementation number of MMU */
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#ifdef notyet
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#define SRMMU_PCR_INITIAL (SRMMU_PCR_ME | SRMMU_PCR_TC)
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#endif
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/* [4m] Bits in the Synchronous Fault Status Register */
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#define SFSR_EM 0x00020000 /* Error mode watchdog reset occurred */
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@ -1,4 +1,4 @@
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/* $NetBSD: cache.c,v 1.21 1997/03/21 15:35:51 pk Exp $ */
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/* $NetBSD: cache.c,v 1.22 1997/03/22 19:17:03 pk Exp $ */
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/*
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* Copyright (c) 1996
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@ -123,7 +123,7 @@ ms1_cache_enable()
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/* Turn on caches via MMU */
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sta(SRMMU_PCR, ASI_SRMMU,
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lda(SRMMU_PCR,ASI_SRMMU) | SRMMU_PCR_DCE | SRMMU_PCR_ICE);
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lda(SRMMU_PCR,ASI_SRMMU) | MS1_PCR_DCE | MS1_PCR_ICE);
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CACHEINFO.c_enabled = CACHEINFO.dc_enabled = 1;
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@ -147,7 +147,7 @@ viking_cache_enable()
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/* Turn on caches via MMU */
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sta(SRMMU_PCR, ASI_SRMMU,
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lda(SRMMU_PCR,ASI_SRMMU) | SRMMU_PCR_DCE | SRMMU_PCR_ICE);
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lda(SRMMU_PCR,ASI_SRMMU) | VIKING_PCR_DCE | VIKING_PCR_ICE);
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CACHEINFO.c_enabled = CACHEINFO.dc_enabled = 1;
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@ -176,7 +176,7 @@ hypersparc_cache_enable()
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* First we determine what type of cache we have, and
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* setup the anti-aliasing constants appropriately.
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*/
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if (i & SRMMU_PCR_CS) {
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if (i & HYPERSPARC_PCR_CS) {
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cache_alias_bits = CACHE_ALIAS_BITS_HS256k;
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cache_alias_dist = CACHE_ALIAS_DIST_HS256k;
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} else {
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@ -188,7 +188,7 @@ hypersparc_cache_enable()
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sta(i, ASI_DCACHETAG, 0);
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sta(SRMMU_PCR, ASI_SRMMU, /* Enable write-back cache */
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lda(SRMMU_PCR, ASI_SRMMU) | SRMMU_PCR_CE | SRMMU_PCR_CM);
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lda(SRMMU_PCR, ASI_SRMMU) | HYPERSPARC_PCR_CE | HYPERSPARC_PCR_CM);
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CACHEINFO.c_enabled = 1;
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CACHEINFO.c_vactype = VAC_NONE;
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@ -219,11 +219,11 @@ cypress_cache_enable()
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cache_alias_bits = (cache_alias_dist - 1) & ~PGOFSET;
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scr = lda(SRMMU_PCR, ASI_SRMMU);
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scr &= ~(SRMMU_PCR_CE | SRMMU_PCR_CM);
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scr |= SRMMU_PCR_CE;
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scr &= ~(CYPRESS_PCR_CE | CYPRESS_PCR_CM);
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scr |= CYPRESS_PCR_CE;
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/* If put in write-back mode, turn it on */
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if (CACHEINFO.c_vactype == VAC_WRITEBACK)
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scr |= SRMMU_PCR_CM;
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scr |= CYPRESS_PCR_CM;
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sta(SRMMU_PCR, ASI_SRMMU, scr);
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CACHEINFO.c_enabled = 1;
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printf("cache enabled\n");
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@ -1,4 +1,4 @@
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/* $NetBSD: cpu.c,v 1.34 1997/03/21 14:30:20 pk Exp $ */
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/* $NetBSD: cpu.c,v 1.35 1997/03/22 19:17:05 pk Exp $ */
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/*
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* Copyright (c) 1996
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@ -787,7 +787,7 @@ viking_hotfix(sc)
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struct cpu_softc *sc;
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{
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/* Test if we're directly on the MBus */
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if (!(lda(SRMMU_PCR, ASI_SRMMU) & SRMMU_PCR_MB)) {
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if (!(lda(SRMMU_PCR, ASI_SRMMU) & VIKING_PCR_MB)) {
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sc->mxcc = 1;
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sc->flags |= CPUFLG_CACHEPAGETABLES;
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sc->flags |= CPUFLG_CACHE_MANDATORY;
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@ -816,9 +816,9 @@ viking_mmu_enable()
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pcr = lda(SRMMU_PCR, ASI_SRMMU);
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if (cpuinfo.mxcc)
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pcr |= SRMMU_PCR_TC;
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pcr |= VIKING_PCR_TC;
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else
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pcr &= ~SRMMU_PCR_TC;
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pcr &= ~VIKING_PCR_TC;
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sta(SRMMU_PCR, ASI_SRMMU, pcr);
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}
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@ -852,8 +852,13 @@ cpumatch_hypersparc(sc, mp, node)
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void
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hypersparc_mmu_enable()
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{
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int pcr = lda(SRMMU_PCR, ASI_SRMMU);
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sta(SRMMU_PCR, ASI_SRMMU, (pcr | SRMMU_PCR_C) & ~SRMMU_PCR_CE);
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int pcr;
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pcr = lda(SRMMU_PCR, ASI_SRMMU);
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pcr |= HYPERSPARC_PCR_C;
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pcr &= ~HYPERSPARC_PCR_CE;
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sta(SRMMU_PCR, ASI_SRMMU, pcr);
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}
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/* Cypress 605 */
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@ -1,4 +1,4 @@
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/* $NetBSD: iommu.c,v 1.9 1997/03/10 23:13:59 pk Exp $ */
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/* $NetBSD: iommu.c,v 1.10 1997/03/22 19:17:06 pk Exp $ */
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/*
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* Copyright (c) 1996
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@ -122,12 +122,12 @@ iommu_attach(parent, self, aux)
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register int node;
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register char *name;
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register u_int pbase, pa;
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register int i, mmupcrsav, s, wierdviking = 0;
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register int i, mmupcrsave, s;
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register iopte_t *tpte_p;
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extern u_int *kernel_iopte_table;
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extern u_int kernel_iopte_table_pa;
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/*XXX-GCC!*/mmupcrsav=0;
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/*XXX-GCC!*/mmupcrsave=0;
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iommu_sc = sc;
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/*
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* XXX there is only one iommu, for now -- do not know how to
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@ -194,10 +194,10 @@ iommu_attach(parent, self, aux)
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*
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* XXX: PGOFSET, NBPG assume same page size as SRMMU
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*/
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if ((getpsr() & 0x40000000) && (!(lda(SRMMU_PCR,ASI_SRMMU) & 0x800))) {
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wierdviking = 1;
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sta(SRMMU_PCR, ASI_SRMMU, /* set MMU AC bit */
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((mmupcrsav = lda(SRMMU_PCR,ASI_SRMMU)) | SRMMU_PCR_AC));
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if (cpuinfo.cpu_vers == 4 && cpuinfo.mxcc) {
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/* set MMU AC bit */
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sta(SRMMU_PCR, ASI_SRMMU,
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((mmupcrsave = lda(SRMMU_PCR, ASI_SRMMU)) | VIKING_PCR_AC));
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}
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for (tpte_p = &sc->sc_ptes[((0 - DVMA4M_BASE)/NBPG) - 1],
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@ -210,8 +210,9 @@ iommu_attach(parent, self, aux)
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(tpte_p - &sc->sc_ptes[0])*NBPG + DVMA4M_BASE);
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*tpte_p = lda(pa, ASI_BYPASS);
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}
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if (wierdviking) { /* restore mmu after bug-avoidance */
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sta(SRMMU_PCR, ASI_SRMMU, mmupcrsav);
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if (cpuinfo.cpu_vers == 4 && cpuinfo.mxcc) {
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/* restore mmu after bug-avoidance */
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sta(SRMMU_PCR, ASI_SRMMU, mmupcrsave);
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}
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/*
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@ -1,4 +1,4 @@
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/* $NetBSD: memreg.c,v 1.18 1996/12/10 23:17:45 pk Exp $ */
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/* $NetBSD: memreg.c,v 1.19 1997/03/22 19:17:07 pk Exp $ */
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/*
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* Copyright (c) 1992, 1993
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@ -56,6 +56,7 @@
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#include <sparc/sparc/memreg.h>
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#include <sparc/sparc/vaddrs.h>
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#include <sparc/sparc/asm.h>
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#include <sparc/sparc/cpuvar.h>
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#include <machine/reg.h> /* for trapframe */
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#include <machine/trap.h> /* for trap types */
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@ -265,9 +266,12 @@ memerr4m(type, sfsr, sfva, afsr, afva, tf)
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addrold = afva;
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addroldtop = afsr & AFSR_AFA;
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} else if (type == T_STOREBUFFAULT) {
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/* We try to reenable the store buffers to force a retry */
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} else if (type == T_STOREBUFFAULT && cpuinfo.cpu_vers == 4) {
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/*
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* On Supersparc, we try to reenable the store buffers
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* to force a retry.
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*/
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printf("store buffer copy-back failure at 0x%x. Retrying...\n",
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sfva);
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@ -278,8 +282,9 @@ memerr4m(type, sfsr, sfva, afsr, afva, tf)
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oldtype = T_STOREBUFFAULT;
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addrold = sfva;
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sta(SRMMU_PCR, ASI_SRMMU, lda(SRMMU_PCR, ASI_SRMMU) |
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SRMMU_PCR_SB); /* reenable store buffer */
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/* reenable store buffer */
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sta(SRMMU_PCR, ASI_SRMMU,
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lda(SRMMU_PCR, ASI_SRMMU) | VIKING_PCR_SB);
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} else if (type == T_DATAFAULT && !(sfsr & SFSR_FAV)) { /* bizarre */
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/* XXX: Should handle better. See SuperSPARC manual pg. 9-35 */
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@ -1,4 +1,4 @@
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/* $NetBSD: pmap.c,v 1.74 1997/03/21 16:29:34 pk Exp $ */
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/* $NetBSD: pmap.c,v 1.75 1997/03/22 19:17:09 pk Exp $ */
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/*
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* Copyright (c) 1996
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@ -1022,7 +1022,7 @@ mmu_reservemon4m(kpmap, kmemtop)
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*/
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if (cpuinfo.cpu_vers == 4 && cpuinfo.mxcc) {
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sta(SRMMU_PCR, ASI_SRMMU, /* set MMU AC bit */
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((mmupcrsave = lda(SRMMU_PCR,ASI_SRMMU)) | SRMMU_PCR_AC));
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((mmupcrsave = lda(SRMMU_PCR,ASI_SRMMU)) | VIKING_PCR_AC));
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}
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te = lda(rom_ctxtbl, ASI_BYPASS); /* i.e. context 0 */
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